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Alright, at least the multilinx cable is working, so the LED flashes. I connected the GND, VCC, TDO, TDI, TCK and TMS. Still I cant get a connection over the serial port which is quite weird. I used automatic detection but I get the following error blog from Impact. Is there an issue with the drivers? In addition, I use two DB25 adapters in order to connect the cable to the board. Shouldnt be an issue either, is that correct? iMPACT Version: H.38 iMPACT log file started on 2007/11/27 17:22:31 // *** BATCH CMD : setPreference -pref UserLevel:NOVICE // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE // *** BATCH CMD : setPreference -pref UseHighz:FALSE // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION // *** BATCH CMD : setPreference -pref AutoSignature:FALSE // *** BATCH CMD : setPreference -pref KeepSVF:FALSE // *** BATCH CMD : setPreference -pref svfUseTime:FALSE // *** BATCH CMD : setPreference -pref UserLevel:NOVICE // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE // *** BATCH CMD : setPreference -pref UseHighz:FALSE // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION // *** BATCH CMD : setPreference -pref AutoSignature:FALSE // *** BATCH CMD : setPreference -pref KeepSVF:FALSE // *** BATCH CMD : setPreference -pref svfUseTime:FALSE GUI --- Boundary-Scan Mode selected // *** BATCH CMD : setMode -bs GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. CB_PROGRESS_START - Starting Operation. Connecting to cable (USB Port). Cable connection failed. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 8.1.1.0. LPT base address = 0378h. ECP base address = 0778h. Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. Connecting to cable (Parallel Port - LPT3). Checking cable driver. Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. Connecting to cable (Parallel Port - LPT4). Checking cable driver. Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. Driver file not found. Inf file version = 0. Driver xusbdfwu.sys version: 1017 (2001). Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. Connecting to cable (COM1 Port). Cable connection failed. Cable connection failed. Cable connection failed. Cable connection failed. CB_PROGRESS_END - End Operation. Elapsed time = 16 sec. Cable autodetection failed. ***** Closing iMPACT program. *****Article: 126551
hi, thanks for the answers. because board area is very limited i was looking for a possibility to do a (kind of) quick and dirty address data-bus extention on demand where i additionally can write hardware peripherals in the fpga connected to this bus but also extend the bus through the fpga if desired (as i said, kind of "dirty")... regards Jonathan Bromley wrote: > On Sat, 24 Nov 2007 12:56:34 +0100, joe <nospam@gmail.com> wrote: > >> i would like to use a small fpga (or cpld) on a pcb to make direct >> bidirectional connections between pins. >> basically it should act like a programmable "cable". >> is this kind of application possible using programmable logic? > > Not with a conventional CPLD. You would need to know enough > about the signal flow to control the CPLD's output buffers. > > There are plenty of bidi switch devices around (QuickSwitch > and suchlike). It might be a good idea to build a crosspoint > matrix of such switches, and then use a small CPLD to control > the enables. > > Lattice have a really interesting product that might suit > your needs: > http://www.latticesemi.com/products/digitalinterconnect/ispgdx2.cfm > > I have no idea about price, availability and development tools > for those parts.Article: 126552
On 2007-11-27, fpga-dev@web.de <fpga-dev@web.de> wrote: > > Any suggestions and comments are welcome! I'm curious: Why the XC9572 instead of some Altera part? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 126553
Hi,
currently I am designing (as an amateur project) a 32bit Stack
oriented CPU with two stack-pointers (Data Stack/Return Stack) and some
additional registers, that are partly purely auxiliary, partly dedicated
for the intended purpose of the CPU as a specialized Lisp-Processor.
The control is microcoded and the greater part of the microcode is
already written and successfully tested (in simulation with Icarus).
Missing at the moment is parts of the ALU functions and the complete
interrupt/exception logic.
Nevertheless the design (done in Verilog), when synthesized, occupies
already about 1100 slices in a Spartan 3 FPGA, which I feel is a bit
heavy for what seems to me a very simple design.
Below I give the output of the Xilinx ISEWebpack synthesis tool
Logic Utilization Used Available Utilization Note(s)
Number of Slice Flip Flops 621 3,840 16%
Number of 4 input LUTs 2,561 3,840 66%
Logic Distribution
Number of occupied Slices 1,517 1,920 79%
Number of Slices containing only related logic 1,517 1,517 100%
Number of Slices containing unrelated logic 0 1,517 0%
Total Number 4 input LUTs 2,751 3,840 71%
(about 400/500 slices can be subtracted from the above figures, as they
result from accompanying structures like VGA driver and the like).
What catches my eye is, how small the utilization of Slice Flip/Flops
compared to the utilization of slices is: Can this be an expression of
the fact, that there is much combinatorial logic (adders, multiplexors)
and, relative to that, few registers/state elements? Are especially
adders, that I used quite generously to speed up the instructions, a
source of slices consumption? Or are multiplexors with many alternative
inputs more likely the culprits?
I would be very happy, if someone with more experience than me (being
just an hobbyist) could look at the Verilog source of the CPU and give
me some hints how to possibly lower the amount of resources needed by
the design.
Greetings,
Jürgen
--
Jürgen Böhm www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?" R. Thom
Article: 126554Hi, I am trying to install ISE 9.2 on a Fedora 8 machine, but have numerous problems. Is there anyone that managed to do this? /michaelArticle: 126555
> I'm curious: Why the XC9572 instead of some Altera part? Because - I already used this CPLD for configuration purposes on a Virtex II Pro board, - it's only CPLD in VQFP-64 package I found, - cheaper than comparable Altera parts. regards, Valerij MatroseArticle: 126556
Hi, The following is from Xilinx "Synthesis and Simulation Design Guide". Could you give me an example to show their differences? And explain a little to me? Thank you very much. You may need to modify your code to successfully synthesize your design because certain design constructs that are effective for simulation may not be as effective for synthesis. The synthesis syntax and code set may differ slightly from the simulator syntax and code set.Article: 126557
Jürgen Böhm wrote: > What catches my eye is, how small the utilization of Slice Flip/Flops > compared to the utilization of slices is: Can this be an expression of > the fact, that there is much combinatorial logic (adders, multiplexors) > and, relative to that, few registers/state elements? Yes, precisely. Are especially > adders, that I used quite generously to speed up the instructions, a > source of slices consumption? Or are multiplexors with many alternative > inputs more likely the culprits? > Yes, wide adders use a lot of LUTs. Multiplexers use up LUTs too. A single 4-input LUT could form a single bit of a 2-input mux, wasting one input. If you need more inputs, then you have to combine several LUTs to perform one bit's worth of multiplexer. Xilinx has pretty detailed info on what the basic structure of their chips are, and you should be able to see how one would form basic logic functions out of that. It may be that Virtex would give more resources for this particular task than Spartan. JonArticle: 126558
On Nov 27, 3:43 pm, fl <rxjw...@gmail.com> wrote:
> Hi,
> The following is from Xilinx "Synthesis and Simulation Design Guide".
> Could you give me an example to show their differences? And explain a
> little to me? Thank you very much.
>
> You may need to modify your code to successfully synthesize your
> design because certain
> design constructs that are effective for simulation may not be as
> effective for synthesis. The synthesis syntax and code set may differ
> slightly from the simulator syntax and code set.
'Differ slightly' is being way too generous. Usually it means more
along the lines of 'not supported at all' for synthesis even though it
is perfectly legitimate code. Some examples and how you would write
the code for simulation are shown below.
1. A delay line (commercially available part from many sources....but
not inside an FPGA typically).
x <= y after 3 ns; -- VHDL representation
2. Division is hard for 2nd graders...not to mention FPGA vendors.
It's not that it can't be synthesized(it can), but it will chew up a
lot of resources and be pretty slow so I guess they figure nobody
would want to do division.
x <= y / z; -- VHDL representation
3. Wait for this event, then that event, then some other thing to
happen
process -- VHDL representation
wait for (This = '1');
wait for rising_edge(That);
wait for (Some_Other_Thing = Happen);
.....
end process;
4. Time? What is that? Without a delay line resource available, a
delay must be synthesized by using counters and clocks to count clock
cycles that roughly mimic the intended delay.
wait for 50.3 ns; -- VHDL representation
There are many others, this is just one tip of the iceberg. In order
to create a design (i.e. to synthesize) something that does each of
the above mentioned things one would make various tradeoffs and would
need to be skilled in basic digital design practices and then could
whip something up that is functionally nearly equivalent to all of the
above.
KJ
Article: 126559On Nov 27, 4:11 am, fpga-...@web.de wrote: > I've made another Cyclone II development board: > english user manual :http://fpga-dev.de/docs/cyclone2_user_manual_eng.pdf > german project page with high-resolution photos:http://fpga-dev.de/index.php?site=ep2c35_beschreibung Wow, that doesn't look half-bad. I'm excited to see the use of SODIMMs. Has this been tested with a 512 MiB DIMM? Too bad about the Europe restriction (but given the current dollar ...). Off-topic: A battery power optimized FPGA board in a compact form factor would be most welcome. I have the LPRP (http:// www.arrowdevtools.com/pg_webc?full_domain_name=www.arrowdevtools.com&domain=ARROW_DEV_TOOLS&application=SEARCH&start_index=1&rows_to_display=20&ORDER_BY_COLUMN=3&ORDER_BY_DIRECTION=A&TOTAL_ROWS_RETURNED=-1&PUBLIC_SEARCH_SEQUENCE=&&event=5020&search_token=LPRP&search_type=click_through) but it's about 4X too big. Also, something larger than the EP3C25 would be good. TommyArticle: 126560
On Nov 27, 9:43 pm, fl <rxjw...@gmail.com> wrote: > Hi, > The following is from Xilinx "Synthesis and Simulation Design Guide". > Could you give me an example to show their differences? And explain a > little to me? Thank you very much. > > You may need to modify your code to successfully synthesize your > design because certain > design constructs that are effective for simulation may not be as > effective for synthesis. The synthesis syntax and code set may differ > slightly from the simulator syntax and code set. There are several possible cases (non exhaustive) : - Code that's just _not_ syntesizable : process begin wait until reset='0'; wait for 3 ns; sig <= '1'; end process; - Code that may / may not be (i.e. if the synthesizer was smart, he could do it ... but it might not be ) a <= b / c; - Code that is syntesizable but will most likely result in huge code ... e.g. a complete behavioral description of some big stuff but only using 'simple' behaviors (no unsynthesizable constructs) ... VHDL is a hardware description language. Meaning that you should _not_ use it to describe what you want the hardware to do. But you should use it to describe the hardware you want built. It's up to you to find what hardware to build to do what you want it to do ... SylvainArticle: 126561
On Nov 27, 3:57 pm, Jon Elson <el...@wustl.edu> wrote: > J=FCrgen B=F6hm wrote: > > What catches my eye is, how small the utilization of Slice Flip/Flops= > > compared to the utilization of slices is: Can this be an expression of > > the fact, that there is much combinatorial logic (adders, multiplexors) > > and, relative to that, few registers/state elements? > > Yes, precisely. > Are especially> adders, that I used quite generously to speed up the ins= tructions, a > > source of slices consumption? Or are multiplexors with many alternative > > inputs more likely the culprits? > > Yes, wide adders use a lot of LUTs. Multiplexers use up LUTs too. A > single 4-input LUT could form a single bit of a 2-input mux, wasting one > input. If you need more inputs, then you have to combine several LUTs > to perform one bit's worth of multiplexer. > Another point to make is that unless you change some defaults, the mapper will not pack slices to capacity until the whole part becomes mostly full. So the number of occupied slices does not necessarily represent the most compact placement of your design. The statistics for LUTs and flip-flops are more useful for determining your actual logic usage. However given the fact that your number of slices is not a whole lot more than half the number of LUTs, I'd say that further packing of "unrelated logic" won't make your design much smaller. > Xilinx has pretty detailed info on what the basic structure of their > chips are, and you should be able to see how one would form basic logic > functions out of that. It may be that Virtex would give more resources > for this particular task than Spartan. > > Jon To benefit from changing families, you probably need to go to Virtex 5, which has 6-input LUTs. Other Virtex families look very similar to Spartan 3 from the viewpoint of the fabric. From m.nguyen@arcor.de Tue Nov 27 14:40:55 2007 Path: newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!multikabel.net!feed20.multikabel.net!newsfeed.freenet.de!npeer.de.kpn-eurorings.net!npeer-ng2.kpn.DE!newsfeed.arcor.de!newsspool2.arcor-online.net!news.arcor.de.POSTED!not-for-mail Message-Id: <474c9bde$0$13114$9b4e6d93@newsspool2.arcor-online.net> From: Minh Nguyen <m.nguyen@arcor.de> Subject: Re: can't read/load memory contents Newsgroups: comp.arch.fpga Date: Tue, 27 Nov 2007 23:40:55 +0100 References: <a237d8ac-8862-4f20-8996-274dd3149101@d61g2000hsa.googlegroups.com> <474823d0$0$27140$9b4e6d93@newsspool1.arcor-online.net> <2682078d-2248-45ed-b91d-f2d83ebb33ce@s6g2000prc.googlegroups.com> <474b1bfd$0$13117$9b4e6d93@newsspool2.arcor-online.net> <b4a41312-6b4e-4086-8143-03ec49c9429c@a39g2000pre.googlegroups.com> User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 27 Organization: Arcor NNTP-Posting-Date: 27 Nov 2007 23:36:15 CET NNTP-Posting-Host: 56492d74.newsspool2.arcor-online.net X-Trace: DXC=FOIK91Z:]1bJ00P1S40fZgA9EHlD;3Ycb4Fo<]lROoRa4nDHegD_]Rea6=9k]^2;Ckj??9;AV]e>afj;_WNd3hafnTEXl8m<FDg X-Complaints-To: usenet-abuse@arcor.de Xref: prodigy.net comp.arch.fpga:138630 On Tue 27 Nov 2007 17:47 dartanian wrote: > I see your point Minh thank you very much. > >> Ah yes. This should be >> sw r8, rA, rB >> where the address (rA + rB) must be word-aligned again--and 0xbbbbbbbb * >> 2 isn't. You could also use an IMM, so you don't need to fill rA and rB: >> swi r8, r0, addr > > One more think. What do you mean that the data 0xbbbbbbbb are not word- > aligned? The hardware supported data types for MicroBlaze are byte (8 bits), half-word (16 bits) and word (32 bits). Data access must be aligned, which means it must be on boundaries that depend on the type. Since a word has the size of 4 bytes the boundaries lie at addresses which are divisible by 4. > Should be maximum up to 0x80000000? No, each address space has a 32-bit range. So you can handle up to 4 GB of memory. > I'll follow your advice! > Thanks againArticle: 126562
Jürgen Böhm wrote: > Hi, > > currently I am designing (as an amateur project) a 32bit Stack > oriented CPU with two stack-pointers (Data Stack/Return Stack) and some > additional registers, that are partly purely auxiliary, partly dedicated > for the intended purpose of the CPU as a specialized Lisp-Processor. > The control is microcoded and the greater part of the microcode is > already written and successfully tested (in simulation with Icarus). > Missing at the moment is parts of the ALU functions and the complete > interrupt/exception logic. > Nevertheless the design (done in Verilog), when synthesized, occupies > already about 1100 slices in a Spartan 3 FPGA, which I feel is a bit > heavy for what seems to me a very simple design. > > Below I give the output of the Xilinx ISEWebpack synthesis tool > > Logic Utilization Used Available Utilization Note(s) > Number of Slice Flip Flops 621 3,840 16% > Number of 4 input LUTs 2,561 3,840 66% > > Logic Distribution > Number of occupied Slices 1,517 1,920 79% > Number of Slices containing only related logic 1,517 1,517 100% > Number of Slices containing unrelated logic 0 1,517 0% > Total Number 4 input LUTs 2,751 3,840 71% > > (about 400/500 slices can be subtracted from the above figures, as they > result from accompanying structures like VGA driver and the like). > > What catches my eye is, how small the utilization of Slice Flip/Flops > compared to the utilization of slices is: Can this be an expression of > the fact, that there is much combinatorial logic (adders, multiplexors) > and, relative to that, few registers/state elements? Are especially > adders, that I used quite generously to speed up the instructions, a > source of slices consumption? Or are multiplexors with many alternative > inputs more likely the culprits? > > I would be very happy, if someone with more experience than me (being > just an hobbyist) could look at the Verilog source of the CPU and give > me some hints how to possibly lower the amount of resources needed by > the design. You could download the Lattice Mico32, and reality check against that, as that is open source. Most FPGAs these days have multiport RAM, so it makes sense to optimise your architecture to use that - in your case for registers, and maybe even for micocode storage. -jgArticle: 126563
What about "no" do you not understand? No, you cannot use global resources for a logic signal in S3. Yes, you can use a global clock for a logic signal in V5, but the entry into the resource, and the exit from that resource may use additional local routes (depending on what the logic signal is connected to/from). You missed the entire issue of Ken's note: asynchronous resets may "break" synchronous circuits. Since we don't support any asynchronous circuits in the FPGA (everything assumes a synchronous logic design flow, and we support no asynchronous logic synthesis), I think you may be confused. AustinArticle: 126564
Mr. Decaluwe, you do great work ! Do not listen any disrespectful troll who has no idea what is MyHDL. What is still missed on MyHDL page are clear informative examples and tutorials. Current domain name is also bad to remember. Menu structure is also poor. Thanks in advance!Article: 126565
HI I have a Xilinx Spartan3e IO pin connected to a system bus signal. The system bus signal can be active (3.3v/0v) even when the Spartan device is powered off. When the signal is at 3.3, I suspect the ESD protection diode between pad and VCCO on the Spartan IOB is going to turn on. Does anybody know what would be the current drawn? -DipankarArticle: 126566
On Nov 27, 3:38 pm, dipum...@hotmail.com wrote: > HI > > I have a Xilinx Spartan3e IO pin connected to a system bus signal. The > system bus signal can be active (3.3v/0v) even when the Spartan device > is powered off. When the signal is at 3.3, I suspect the ESD > protection diode between pad and VCCO on the Spartan IOB is going to > turn on. Does anybody know what would be the current drawn? > > -Dipankar Get a multimeter and measure the current! I would also observe the Vcco (I/O supply voltage) while the pin is being driven High. Most devices have a strong diode between any I/O pin and its Vcco supply pin. Some devices claim to be "hot pluggable" and avoid this diode-clamping somehow. Peter Alfke, Xilinx ApplicationsArticle: 126567
psihodelia@googlemail.com wrote:
> What is still missed on MyHDL page are clear informative examples and
> tutorials.
What's wrong with this one?
http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp
-- Mike Treseler
Article: 126568austin writes: > No, you cannot use global resources for a logic signal in S3. I've heard you say that before, and I don't dispute it, but I'm curious as to the reason. How does the S3 "know" whether the signal I've got driving a global clock net is actually a clock? Is there a minimum frequency for the clock net? I don't see one in the datasheet. EricArticle: 126569
Hello together, in my vhdl design for ISE 9.2 I want to partition the component instances of the submodules in my toplevel into defined areas of my fpga ic. I have never done this but had seen some examples before, where it might have worked (e.g. projects with reconfiguration). So I adapted my ucf-file accordingly by adding several area group constraints and assigned an instance for each area group like in this short example snippet: AREA_GROUP "ag1" RANGE = SLICE_X0Y0:SLICE_X50Y50; INST instance_name_of_first_component_from_toplevel AREA_GROUP = ag1; AREA_GROUP "ag2" RANGE = SLICE_X51Y0:SLICE_X100Y50; INST instance_name_of_second_component_from_toplevel AREA_GROUP = ag2; ... But now I'm getting an error (while implementation stage - don't know exactly at the moment). The error message says roughly, that the instances cannot be found (something like that) and i'm proposed to delete the relevant constraint to go on. I use the label name of the component port map statement in my toplevel as the instance names inside the ucf. Is this wrong or what's the problem? Any suggestions? I can't post the exact error message at the moment, but it will be given later if it's necessary. I have read, that it is possible to generate or extract such area constraints by using the floorplanner. Does anyone know a helpful and not too sparse tutorial for the floorplanner, especially for my purpose? Thanks a lot. L. SchreiberArticle: 126570
Minh Nguyen wrote: > On Tue 27 Nov 2007 17:47 dartanian wrote: (snip) >> One more think. What do you mean that the data 0xbbbbbbbb >> are not word-aligned? > The hardware supported data types for MicroBlaze are byte (8 bits), > half-word (16 bits) and word (32 bits). Data access must be aligned, which > means it must be on boundaries that depend on the type. Since a word has > the size of 4 bytes the boundaries lie at addresses which are divisible by > 4. Is the address really X'BBBBBBBB'? Or is the b supposed to mean something else? If it is really the hex digit B then yes, the address is odd. Otherwise, it doesn't seem like a likely address. -- glenArticle: 126571
Hello all, can you please tell us what tools you prefer? Please give some arguments, why you like them. I currently use very intensively Linux shell and GHDL compiler for simulations and XST for synthesis. GHDL is very fast and powerful. You can for example colorize your files directly into HTML, call foreign functions (e.g. from C library), and many more. My VHDL projects have typical Linux-way directory tree structure: ./bin/ for binaries ./include/ for includes ./work/ for generated modules ./src/ for sources inside src directory is a Makefile, which is automatically generated by GHDL. In order to build a binary, I use "make sim" command. If I need to create some additional component in other language (C or Python), I use "foreign" declarations in VHDL code and link them using GHDL, just like with well-known GCC. For example if you need to verify your VGA-Controller Design, you can create a special C-function which will create JPG file with the current frame. For synthesis I use XST from Xilinx ISE. It is very simple to type: "make syn; make load" and bitfile will be uploaded into an FPGA. For communication with FPGA board, real-time visualization, and so on, I use small Python scripts. I use VIM as a text editor. It also helps me to be very productive and to work remotely using SSH (e.g. it's nice thing to use VIM on your cell phone like Nokia N200 which has Linux onboard). So, this are my tools: GHDL, XST, GNU Tools(make, bintools, bash, libc, etc.), VIM, Python, GCC and of course Linux itself. Frankly, only XST is not under Open Source license and it mostly slow- downs hole development flow because of XST's bugs and its poor performance. All other programs I use are previously compiled using optimization flags targeted my server's hardware. What tools do you prefer? Why ?Article: 126572
"joe" <nospam@gmail.com> wrote in message news:90dd8$474c5fbd$3eb2d6c4$8433@news.chello.at... > hi, > > thanks for the answers. > because board area is very limited i was looking for a possibility to do a > (kind of) quick and dirty address data-bus extention on demand where i > additionally can write hardware peripherals in the fpga connected to this > bus but also extend the bus through the fpga if desired (as i said, kind > of "dirty")... > But now that you make known your real desire to extend a bus and have some registers to access, an FPGA solution is plenty viable. Thinking that you needed a bi-directional connection with no sense of which end is driving or receiving as you stated in your original post is a completely different problem. In any case, extending a bus is easily doable in any FPGA that has enough I/O pins and meets voltage standards of the things that it is connected with. KJArticle: 126573
Eric Smith wrote: > austin writes: >> No, you cannot use global resources for a logic signal in S3. > > I've heard you say that before, and I don't dispute it, but I'm curious > as to the reason. How does the S3 "know" whether the signal I've got > driving a global clock net is actually a clock? Is there a minimum > frequency for the clock net? I don't see one in the datasheet. It's not a case of classifying the input as a "clock", but one of "you can't get there from here". The global clock nets go to clock pins, if your destination is something other than a clock pin then it has to "hop off" and use the regular routing resources to get there. Ed McGettigan -- Xilinx Inc.Article: 126574
Ed McGettigan wrote: > It's not a case of classifying the input as a "clock", but one of "you > can't get there from here". The global clock nets go to clock pins, if > your destination is something other than a clock pin then it has to > "hop off" and use the regular routing resources to get there. Thanks for the explanation; that's certainly a very good reason to not try to use the clock net for something else.
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