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Didi wrote: >> I'm not sure what you are expecting, the flow IS pretty simple : >>[I suspect you are being too paranoid :) ? ] > > > Of course I am paranoid - and I do not think I can be nearly > enough that when it comes to xilinx programming data... > > >>>eg : I trawl my PC for a Xilinx JED file, >> >>and find this >> >>D:\Xilinx\DesignPaths\Design.JED: >>... > > > Are you sure you don't have the xilinx paid software installed > somewhere on that PC? If this is the case we cannot tell whether > there is no fuse address mapping going on behind the scenes > (transparent at user level). I am sure the system is not that clever. It just loads a JED file, and programs the device. You can download the Pgmr file yourself from eetools, and it runs in demo-mode with no pgmr found, so you can move that around as much as you like, and load JED files. They would be less likely to > do that over the net as this would be way easier to catch, > but it would take an unplugged RJ-45 to make sure :-). > Please keep the issue in background and keep me posted if > you stumble across some related news (I seldomly read com.arch.fpga > but a do read pretty often comp.arch.embedded). > I would have tried to talk to some other vendor if anyone > else had a coolrunner-like part (practically 0 static power), > sadly xilinx bought the philips line only to shut it down - and > now I cannot do what I could do while there were Philips devices. Which part and package are you using, and what specs do you need ? > I'll try to ask xilinx support for the .xls document which > translates jedec address <-> jtag_stream_bit_offset; I wonder > how many millions/quarter revenue they'll ask me to make for them > this time before they consider my chance of getting the data (last > time I asked it was $20M/quarter). They do not have any revenue stipulation for Device Porgrammer suppliers, Indeed they expect to sell nothing to the vendor, but they do benefit from the infrastructure of programmers that support the devices. -jgArticle: 126276
What has happend to c.a.f? Only rickman was even close to being on the ball. Altera agree that I've found a bug and sent me a temporary workaround (I haven't yet tested it): module single_port_ram ( input [(DATA_WIDTH-1):0] data, input [(ADDR_WIDTH-1):0] addr, input we, clk, output [(DATA_WIDTH-1):0] q ); parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 6; // Declare the RAM variable reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; reg [ADDR_WIDTH-1:0] addr_reg; always @ (posedge clk) begin // Write if (we) ram[addr] <= data; addr_reg <= addr; end // Read returns NEW data at addr if we == 1'b1. This is the // natural behavior of TriMatrix memory blocks in Single Port // mode assign q = ram[addr_reg]; endmoduleArticle: 126277
On Nov 17, 2:22 am, rickman <gnu...@gmail.com> wrote: > I am looking at a low end Dell laptop, the Vostro 1500, as a new > computer for work. I may supplement this later with a new desktop > unit for crunching FPGA designs, but I will also be using this laptop > for this sort of work. I am looking for advice on the differences in > CPUs for FPGA work and anything else that is relevant. > > I know that parallel ports are going the way of the serial port and > the dodo bird, but I can live with that. Most tools are available as > USB devices now. > > This particular computer comes with WindowsXP rather than Vista. From > what I have heard, that is an advantage. But I notice that the > internal bluetooth adapter is specific for XP and others from Dell are > specific for Vista. Any idea what is up with that? Is there any > significant advantage to using XP pro over XP home? > > This machine also has the "Intel(R) Integrated Graphics Media > Accelerator X3100". Is that just another way of saying "integrated > video"? Several of my other machines have had integrated video and it > does seem to drag down the CPU noticeably. Any idea if I will notice > the drag on the Core 2 Duo? They also offer an Nvidia Gforce 8400 GS > adapter for $100 and an 8600 for $200 more. Any idea if these are > worth it? The 1500 says it has "VGA video output & S-Video". Does > that mean I can connect two monitors for dual display? > > The CPU is a T5270 (1.4 GHz, 2 MB cache) with upgrades to various > processors for significant money. The first stepup is to a T5470 (1.6 > GHz) for $75 and others range up to $575! I am thinking I can live > with the slower processor. The memory is 2GB. > > I was looking at the Vostro 1000 earlier this week with an AMD TK-53 > processor (1.5 GHz, 512 KB cache) and a smaller hard drive. It was > $50 more so the 1500 looks like the better deal. Are there any > significant differences in the two CPUs for FPGA work? I guess the > small cache of the TK-53 would make it significantly slower for FPGA > work. > > I saw a thread from earlier this year discussing some of this. I > wonder how much laptops have improved since then. About the display: 15.4" in not enough for a real work. You should better buy a 17", your eyes would be pleased. As they say: integrated graphic card is OK if you do not use 3D programs. GuruArticle: 126278
Pasacco wrote: > In EDK 8.2, I am finding how to set up XST synthesis option > "KEEP_HIERARCHY = YES", with no luck. > > Could someone tell me how to set "hierarchy" for synthesis step? You could add this option to the vhdl source file(s) if you want to keep the hierarchy for a specific module. If you have an architecture called "arch" you should add attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of arch : architecture is "yes"; to the declaration part of the architecture. Regards, AndreasArticle: 126279
Tommy Thorn wrote: (snip) > "Warning: Inferred RAM node "ram~0" from synchronous design logic. > Pass-through logic has been added to match the read-during-write > behavior of the original design." > Indeed, the template is pass-through, but that is be directly > supported by the M4K memory blocks in the context I'm using (no mixed > port sizes or clocks). I thought pass through logic was for a FIFO (and presumably for the two port RAM used to generate it) when it currently has no data. New data written must then immediately be available at the output. If you don't need that ability (in either FIFO or RAM) turn the option off. Or is it something completely different? -- glenArticle: 126280
> I am sure the system is not that clever. It just loads a JED file, and > programs the device. > You can download the Pgmr file yourself from eetools, and it runs in > demo-mode with no pgmr found, so you can move that around as much as you > like, and load JED files. Well I did look for that Chipmax programmer of theirs you mentioned in your other post and located it at http://www.eetools.com/index.cfm?fuseaction=product.display&Product_ID=7 Does not look like a JTAG adaptor to me and there are no Xilinx devices on it list of supported parts - how can you read/write a coolrunner using this? Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ On Nov 19, 4:18 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Didi wrote: > >> I'm not sure what you are expecting, the flow IS pretty simple : > >>[I suspect you are being too paranoid :) ? ] > > > Of course I am paranoid - and I do not think I can be nearly > > enough that when it comes to xilinx programming data... > > >>>eg : I trawl my PC for a Xilinx JED file, > > >>and find this > > >>D:\Xilinx\DesignPaths\Design.JED: > >>... > > > Are you sure you don't have the xilinx paid software installed > > somewhere on that PC? If this is the case we cannot tell whether > > there is no fuse address mapping going on behind the scenes > > (transparent at user level). > > I am sure the system is not that clever. It just loads a JED file, and > programs the device. > You can download the Pgmr file yourself from eetools, and it runs in > demo-mode with no pgmr found, so you can move that around as much as you > like, and load JED files. > > They would be less likely to > > > do that over the net as this would be way easier to catch, > > but it would take an unplugged RJ-45 to make sure :-). > > Please keep the issue in background and keep me posted if > > you stumble across some related news (I seldomly read com.arch.fpga > > but a do read pretty often comp.arch.embedded). > > I would have tried to talk to some other vendor if anyone > > else had a coolrunner-like part (practically 0 static power), > > sadly xilinx bought the philips line only to shut it down - and > > now I cannot do what I could do while there were Philips devices. > > Which part and package are you using, and what specs do you need ? > > > I'll try to ask xilinx support for the .xls document which > > translates jedec address <-> jtag_stream_bit_offset; I wonder > > how many millions/quarter revenue they'll ask me to make for them > > this time before they consider my chance of getting the data (last > > time I asked it was $20M/quarter). > > They do not have any revenue stipulation for Device Porgrammer > suppliers, Indeed they expect to sell nothing to the vendor, but > they do benefit from the infrastructure of programmers that support the > devices. > > -jgArticle: 126281
Didi wrote: >>I am sure the system is not that clever. It just loads a JED file, and >>programs the device. >>You can download the Pgmr file yourself from eetools, and it runs in >>demo-mode with no pgmr found, so you can move that around as much as you >>like, and load JED files. > > > Well I did look for that Chipmax programmer of theirs you mentioned > in your other post and located it at > http://www.eetools.com/index.cfm?fuseaction=product.display&Product_ID=7 Sorry, should have given you a link: http://www.eetools.com/downloads/ml27h.exe > Does not look like a JTAG adaptor to me and there are no Xilinx > devices on it list of supported parts - how can you read/write a > coolrunner using this? Download that .exe, unpack, and the device list is under Chipmax2 Their Topmax 2 model also has a back-socket for jtag, but the ZIF48's also use JTAG. We have made an adaptor, that takes the ZIF48, and buffers to a IDC10 header, to match the Atmel CPLD programmer. So with this, you can ISP pgm, into a cable/pcb. Programs ATF1502BE much faster via ChipMAX than via the AtmelISP SW. (and we can vector test via the ZIF48, prior to PCB fab ) Which device did you need ? -jgArticle: 126282
I think your being paranoid to the point of needing some medication! In the lab, where engineers constantly think "what if?" Xilinx and others excercise a lot of control, your welcome to argue that it is too much control. Austin and others will argue with you about the cost of tech support. Xilinx make money by selling hundreds of thousands of everything. If more than .01% of their devices get programmed using their kit I'll be astounded. I have sent JEDEC filess all round the world, mainly to the far east, (unfortunately) and I assure you the manufacturer doesn't have a clue what the device is or what it does let alone have XILINX webpack installed. Right now I've just designed a system with multiple IO modules. I've routed a JTAG chain through each IO connector so that we can bit bang JEDEC (or simillar) files and do field upgrade to the CPLDs on every IO module. We've done it before and it's pretty painless, with no support from Xilinx. ColinArticle: 126283
On Sun, 18 Nov 2007 10:34:06 -0800 (PST), "u_stadler@yahoo.de" <u_stadler@yahoo.de> wrote: >On 17 Nov., 23:27, John Retta <jre...@rtc-inc.com> wrote: >> [1] As others suggest, make sure that all >> inputs are known ... not X. X in results in >> X out. >thanks for all the replies. >well of course i checked my input signals and i applie values to them. >the rd and wr signals are good aswell as the clk and >the address signal (good meaning that they have a defined level >(either '0' of '1' applied to them)). >a strange thing is that the data_in signal has all 'U' althoug i apply >for example all '0' to it. >this is probably the reason that when i write to the memory and then >read from the same address i get all 'U' in my data_out. >any idea whats wrong here? > >entity spi_memory is > PORT ( CLK : in STD_LOGIC; > Data_in : inout STD_LOGIC_VECTOR (31 downto 0); > Data_out : inout STD_LOGIC_VECTOR (31 downto 0); > Address : in STD_LOGIC_VECTOR (9 downto 0); > WR : in STD_LOGIC; > RD : in STD_LOGIC); >end spi_memory; > >architecture Behavioral of spi_memory is > > signal s_write_strobe : std_logic; > type mem_array is array(0 to 1023) of std_logic_vector(31 downto 0); > signal ram : mem_array; > signal rd_addr_ram : std_logic_VECTOR(9 downto 0); >begin > > >i drive the data_in signal from the outside testbench.. > This may be the problem. The testbench also drives any signal connected to it via an Out or InOut or Buffer port... but with what? If you do not explicitly drive them, .. with "U". This will override any drivers you add outside the testbench. You may drive any such signals with 'Z' or (others => 'Z') in the testbench to overcome this. But first, (assuming you are using Modelsim) try the "drivers" command on your signal, in the console window e.g. drivers testbench/u1/data_in You should get a list of all drivers connected to that signal; their full name in the design hierarchy, and the value they are driving onto the signal in question. Follow the "U" or "X" back top its source, and fix the problem. - BrianArticle: 126284
On Nov 17, 4:31 am, "HT-Lab" <han...@ht-lab.com> wrote: > "rickman" <gnu...@gmail.com> wrote in message > > news:d2fd7e80-2f5f-4366-b704-03fcee01bbfd@a28g2000hsc.googlegroups.com... > > >I am looking at a low end Dell laptop, the Vostro 1500, as a new > > computer for work. I may supplement this later with a new desktop > > unit for crunching FPGA designs, > > Consider a small form factor PC, they are small enough to carry home and you > get all the power of a desktop. The only disadvantage is that you can't use > them at an airport :-) That is a neat idea. The slim Vostro "desktops" look pretty small and can be had with something considerably more powerful for considerably less expense. Either way, you might check out one of the MANY deal sites (like http://www.techbargains.com/ - but there are lots of others) that keep track of the latest "best deals" from Dell. Just browse the left column. If you don't like what you see, wait a week, they usually morph slightly. > > The CPU is a T5270 (1.4 GHz, 2 MB cache) with upgrades to various > > processors for significant money. The first step-up is to a T5470 (1.6 > > GHz) for $75 and others range up to $575! I am thinking I can live > > with the slower processor. The memory is 2GB. > > Go for 4Gbyte, this will make your P&R run a lot faster. Yes you can only > use 3.2GByte under XP but even the extra 1.2Gbyte will make a difference. I'm not sure I agree completely with this part. If your design is large enough to use that memory, it will help. And honestly, it may be less about the size of the design and more about the size/number of contraints in the .ucf (at least according to the warning ISE gives on a few of our designs). MarcArticle: 126285
"Marc Randolph" <mrand@my-deja.com> wrote in message news:d59d857e-535b-4878-8b44-5df963f44617@f13g2000hsa.googlegroups.com... > On Nov 17, 4:31 am, "HT-Lab" <han...@ht-lab.com> wrote: >> "rickman" <gnu...@gmail.com> wrote in message ..snip.. > > I'm not sure I agree completely with this part. If your design is > large enough to use that memory, it will help. And honestly, it may > be less about the size of the design and more about the size/number of > contraints in the .ucf (at least according to the warning ISE gives on > a few of our designs). You are absolutely right, it is the number of constraints that seems to eat memory like there is no tomorrow. I had a design which had a reasonable number of false-path which couldn't be routed on 4Gbyte+4Gbyte swap machine, however, when I removed the constraints it only consumed 1Gbyte. The point I should have made is that memory prices are at an all time low so don't skimp on it especially since most laptops are now dual core so you might need some reserves for your VMware session :-) Hans www.ht-lab.com > > MarcArticle: 126286
On Nov 19, 8:30 am, "HT-Lab" <han...@ht-lab.com> wrote: > > The point I should have made is that memory prices are at an all time low so > don't skimp on it especially since most laptops are now dual core so you > might need some reserves for your VMware session :-) Thanks to all for their insights. Isn't memory at all time low prices most of the time? That alone does not make any given amount cheap. Especially with Dell! They will give you 1 or 2 GB with the machine and then charge you another $300 or more to bump it up to 4 GB! If you think memory is cheap now, just give it until after Christmas! It has been predicted for some time that both RAM and Flash prices would be creeping up with the extra demand for the holidays. But instead it has continued to creep down. With the softening of demand following the holidays, memory prices should come down another 10 to 20% by February. Besides, this will be *a* work machine, but if I have large designs to deal with, I will come up with a desktop that can easily (and cheaply) be maxed out on memory. BTW, if I am running Win2K, does it have the same 3.2 GB limitation or is it less? I assume the 3.2 GB limit is from the 32 bit address size? Why is it 3.2 instead of 4 GB? The small form factor machine is not really the best way to go since not only can you not use it in an airport, you can't use it anywhere you don't have a monitor and keyboard. At this time I feel I really need a laptop.Article: 126287
Joseph H Allen wrote: > In article <A35%i.17632$pr6.16558@newsfe06.phx>, > Colin Hankins <Colin.Hankins@touit.com> wrote: > >> My particular interest developed in the >> Lattice ECP2M because I need a FPGA/SERDES combo and the price for the ECP2M >> seems unbelievable compared to their competitor's equivalent FPGAs. > > How about Altera's Aria GX? The 60K LE device is $262.50 from Arrow, about > the same as the 70K device from Lattice. The SERDES in the Lattice device > looks better (and there are more of them), but Altera's synthesis tools are > better. The free web edition software supports this device. > > I know they support x4 PCIe, if that's why you need the SERDES. The Altera Arria GX may be a technically good device but the prices from the factory were - at least at the time - double what we were quoted for the Lattice and Xilinx alternatives. These were quantity quotes with production over a year away. Double? Maybe the quote was a fluke since prototype pricing for a larger part came in much better than I expected (given the recent experience) when our coworkers on another coast got quotes from their local sales folks. - John_HArticle: 126288
>MyHDL looks really nice! >Is it possible to have in a FSM one procedure-or-function for each >state? It should make the program code easy to read. It will be also >better to have an array of functions and call them according FSM state >number. Do you have any idea how to implement this in MyHDL? >Here is a vivid wishful pseudo-Python example of what I mean: > >def read(args): > do smth. >def write(args): > do smth. > ... >function = [1:read, 2:write, 3:sleep, 4:wake] >next_state = [1:3, 2:3, 3:3, 4:1] >def FSM_states_switch: > state = next_state[state] >def FSM_output_function: > function[state](args) > Try putting Python and MyHDL on your CV/resume instead of VHDL or (System)Verilog and see how many job offers you get... ;-) As and when (potential) employers adopt more modern development methodologies, then so do/will I.Article: 126289
Hi Sorry, for putting this question here but I have heard that the Xilinx support is quite busy so perhaps someone can help me out here a little bit quicker ;). I am just wondering if there is an easy option to upgrade an older version, in our case ISE version 7.1 to the new release? It would first of all be interesting to know how much it would cost and how long it would take to get a copy, or is it perhaps possible to have access to the software distributions via FTP? Thanks a lot!Article: 126290
"austin" <austin@xilinx.com> wrote in message news:fhq5o1$1721@cnn.xilinx.com... > > Thanks for taking the time to let us know how all of the FPGA vendors fare > through their distributors. We don't often get that sort of feedback. Austin, My experience (also as a small company in the UK, like some of the other respondents) is that the franchised distributors are all entirely useless for every aspect of everything to do with electronic design, whether it's technical info, prices or delivery of parts. They're an infuriating intermediary who do nothing except turn us against manufacturers who have been ill-advised enough to abandon all their customer-facing activities to distributers. To the utmost degree possible, we only select components where we can find a *guide* volume price using Findchips or on the manufacturer's website, buy ex-stock parts from RS, Farnell or Digikey and obtain the technical information we need directly from the manufacturer (without filling in forms). Over the lifetime of any product I've worked on, obtaining the actual parts to actually build things has been just as big a deal as doing the original design. As a customer, putting oneself at the mercy of the Arrows of the world is crazy - and I've never been able to work out why the manufacturers do it. I can't believe that X or A have more than a few hundred shipping products at any one time (even with all the speed/package variants). Why on earth can't you sell the wretched things directly from your website - your average corner-store handles a large range of products with more sophisticated storage and handling requirements. As far as I can tell, the conventional distributors: 1. Don't hold stock 2. Don't break volume in any useful way, so you can't buy small quantities 3. Can't give proper prices without going back to the mfg 4. Can't offer hard technical advice (i.e. not in the published litterature) without going back to the mfg What are they for? Why are you still using them? WillArticle: 126291
hello all, I am looking for some books for microblaze and some examples with assembly for microblaze. since now i havent found anything helpful. thank you regardsArticle: 126292
Tommy Thorn wrote: > I tried asking this in the Altera forum, but to no avail. > The crux of my question is why the template that Quatus itself > suggests results in a warning and how to fix that? http://www.altera.com/support/examples/verilog/ver_ram.htmlArticle: 126293
On Nov 19, 10:13 am, Harald <Har...@yahoo.co.uk> wrote: > Hi > > Sorry, for putting this question here but I have heard that the Xilinx > support is quite busy so perhaps someone can help me out here a little > bit quicker ;). I am just wondering if there is an easy option to > upgrade an older version, in our case ISE version 7.1 to the new > release? It would first of all be interesting to know how much it would > cost and how long it would take to get a copy, or is it perhaps possible > to have access to the software distributions via FTP? > > Thanks a lot! You can download a free version, the ISE WebPack, from the Xilinx website. The full version costs around US$2500, I believe. The free version is pretty good, though, but it doesn't support some of the newer and denser chips.Article: 126294
you should learn Rossetta as Well. pretty cool attempt. I am looking to hire MyHDL designers:P:P:P ..heheheArticle: 126295
> You can download a free version, the ISE WebPack, from the Xilinx > website. The full version costs around US$2500, I believe. The free > version is pretty good, though, but it doesn't support some of the > newer and denser chips. Wow thats for free? Cool, well i have a quite old Virtex|| board to I assume that should be fine. Can this tool compete with the Synopsis and Cadence Design Compilers? Cheers!Article: 126296
Dear All, The TPS75003 is a triple voltage regulator designed for the Spartan-3 & Spartan-3E series. It's got some quite specific component requirements. Unfortunately, the datasheets and appnotes list parts that aren't that easy to source in the UK. I've put together a list of parts available from Farnell (UK) that seem to work well. The list and a PCB design are available here: http://www.bioinspired.com/users/ajg112/circuits/tps75003.shtml Hopefully this will save time for anyone else who plans to use the device. Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432828 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 432335 Web: http://www.bioinspired.com/users/ajg112 From laurent.pinchart@skynet.be Mon Nov 19 08:13:41 2007 Path: newssvr27.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder.news-service.com!feeder1.cambrium.nl!feeder5.cambrium.nl!feed.tweaknews.nl!68.142.88.75.MISMATCH!hwmnpeer01.ams!news.highwinds-media.com!kramikske.telenet-ops.be!nntp.telenet.be!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <4741b635$0$22317$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: TPS75003 Spartan-3(E) Regulator Design Newsgroups: comp.arch.fpga Date: Mon, 19 Nov 2007 17:13:41 +0100 References: <fhsbvi$67r$1@netty.york.ac.uk> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 33 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 76c64631.news.skynet.be X-Trace: 1195488821 news.skynet.be 22317 194.78.198.49:56406 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:138350 Hi Andrew, Andrew Greensted wrote: > Dear All, > > The TPS75003 is a triple voltage regulator designed for the Spartan-3 & > Spartan-3E series. It's got some quite specific component requirements. > Unfortunately, the datasheets and appnotes list parts that aren't that > easy to source in the UK. > > I've put together a list of parts available from Farnell (UK) that seem > to work well. > > The list and a PCB design are available here: > http://www.bioinspired.com/users/ajg112/circuits/tps75003.shtml > > Hopefully this will save time for anyone else who plans to use the device. Thanks a lot for this. I've been struggling with a TPS75003 design for a few days, trying to find parts that would be easy to get (inductors are the major issue). Have you tested the design ? Application notes and reference design I found were all able to supply 2.5A-3.0A @ 1.2V. I'm a bit concerned about this, as typical FPGA consumption for the Spartan3E-500 FPGA I plan to use is much lower than that. Have you measured ripple on 1.2V at low load and no load ? I'm also concerned about load change (such as when the FPGA is configured/unconfigured), have you made any measurement there ? Best regards, Laurent PinchartArticle: 126297
> Right now I've just designed a system with multiple IO modules. I've > routed a JTAG chain through each IO connector so that we can bit bang > JEDEC (or simillar) files and do field upgrade to the CPLDs on every > IO module. We've done it before and it's pretty painless, with no > support from Xilinx. So how do you do the jedec_bit_address -> jtag_stream_bit_offset? Do you have the .xls files from xilinx which do that for the Coolrunner? > I think your being paranoid to the point of needing some medication! Of course I am. The right medication would come in .xls format, namely the excel files which map the above mentioned translation. Unfortunately, no sign of that medicine anywhere on the net (except being mentioned in their programmer related .pdf files, to be found there only if you know there is something missing). I got infected with this paranoya ever since Xilinx bought the coolrunner and hid the .xls file from me - those which Philips had provided me with for their generation of devices and which I have successfully used while such devices were to be found. Dimiter P.S. I am still waiting for "approval" of their web support in order to be allowed to ask for these files, I'll post my experience in this thread. Last time I talked to them they asked me to make $20M revenue/quorter before they would review my case for handing me the data.... That was about 5 years ago, let me check that again. ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ On Nov 19, 1:49 pm, colin <colin_toog...@yahoo.com> wrote: > I think your being paranoid to the point of needing some medication! > > In the lab, where engineers constantly think "what if?" Xilinx and > others excercise a lot of control, your welcome to argue that it is > too much control. Austin and others will argue with you about the cost > of tech support. > > Xilinx make money by selling hundreds of thousands of everything. If > more than .01% of their devices get programmed using their kit I'll be > astounded. > > I have sent JEDEC filess all round the world, mainly to the far east, > (unfortunately) and I assure you the manufacturer doesn't have a clue > what the device is or what it does let alone have XILINX webpack > installed. > > Right now I've just designed a system with multiple IO modules. I've > routed a JTAG chain through each IO connector so that we can bit bang > JEDEC (or simillar) files and do field upgrade to the CPLDs on every > IO module. We've done it before and it's pretty painless, with no > support from Xilinx. > > ColinArticle: 126298
Laurent Pinchart wrote: > Have you tested the design ? Application notes and reference design I found > were all able to supply 2.5A-3.0A @ 1.2V. I'm a bit concerned about this, > as typical FPGA consumption for the Spartan3E-500 FPGA I plan to use is > much lower than that. Have you measured ripple on 1.2V at low load and no > load ? I'm also concerned about load change (such as when the FPGA is > configured/unconfigured), have you made any measurement there ? > > Best regards, > > Laurent Pinchart > Hi Laurent, Yep, it does work. I've built up the board, and tested it. Currently it's powering four Spartan-3Es, the total current drawn (for 3.3V, 2.5V & 1.2V) is only about 150mA, but each FPGA is doing _very_ little. I've not had a chance to do any testing of ripple etc... or try different load conditions. When I do, I'll add the results to the web page. Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432828 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 432335 Web: http://www.bioinspired.com/users/ajg112Article: 126299
Laurent Pinchart wrote: > Have you measured ripple on 1.2V at low load and no > load ? I've just done a quick measure of the ripple: 3.3V is about 90mV 1.2V is about 20mV (The 2.5V is the LDO, so ripple is low, about 10 mV, general noise really) Again, this is under low load conditions. Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432828 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 432335 Web: http://www.bioinspired.com/users/ajg112
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