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Hi Andreas, Thanks for your feedback, I cant understand why this is not working with ISE? I have ISE 9.2.03i for Win32, really strange that I cant choose the Virtex2 board xc2v6000? Anyone an idea whats wrong? Cheers! Andreas Wassatsch wrote: > Dear Harald, > > i have in the ISE9.2_03i(lin64) the xc2v6000 in the device option tab > > my problem is the edk and not the ise > > Regards, > > Andreas > > Harald wrote: >>> i'm currently trying to make an virtex2 project with edk 9.2i. >>> Unfortunately all virtex2 based boards are removed from the bsb dialog >>> (also boards with older spartan devices). >> I have the same problem. I have a Virtex2-XC2V6000 board that I wanna >> use for sythesis. In the device properties of ISE 9.2 I just have the >> option to chose between the following devices: >> >> - XC2V40 >> - XC2V80 >> - XC2V250 >> - XC2V500 >> >> Is there a way to run synthesis for my board? I assume the other boards >> wont be compatible with the one I am using? >> >> Cheers, >> HaraldArticle: 126351
Harald wrote: > Hi Andreas, > > Thanks for your feedback, I cant understand why this is not working with > ISE? I have ISE 9.2.03i for Win32, really strange that I cant choose > the Virtex2 board xc2v6000? > > Anyone an idea whats wrong? I was explicitly told by EDK 9.2 that it no longer supports Spartan-II, Virtex, Virtex-E, Virtex-II, or Virtex-II Pro devices. ISE 9.2 may be the same. As a result I'm sticking with EDK 9.1 for the forseeable future, since the board I've got is the Xilinx University Program Virtex-II Pro board. PhilipArticle: 126352
> I was explicitly told by EDK 9.2 that it no longer supports Spartan-II, > Virtex, Virtex-E, Virtex-II, or Virtex-II Pro devices. ISE 9.2 may be > the same. So the question is, if I am able to get a copy of ISE 9.1 ... have to check the xilinx homepage... Cheers!Article: 126353
Dear Philip, on the web site xilinx claims that edk9.2i is also support virtex2 and the other mentioned older xilinx devices. So the message in the bsb dialog is not conform to the contens of the xilinx web. Regards, Andreas Philip Potter wrote: > Harald wrote: >> Hi Andreas, >> >> Thanks for your feedback, I cant understand why this is not working >> with ISE? I have ISE 9.2.03i for Win32, really strange that I cant choose >> the Virtex2 board xc2v6000? >> >> Anyone an idea whats wrong? > > I was explicitly told by EDK 9.2 that it no longer supports Spartan-II, > Virtex, Virtex-E, Virtex-II, or Virtex-II Pro devices. ISE 9.2 may be > the same. > > As a result I'm sticking with EDK 9.1 for the forseeable future, since > the board I've got is the Xilinx University Program Virtex-II Pro board. > > PhilipArticle: 126354
Dear Harald, in the mean time i have made a test design for xc2v6000 on a windows ise92.03i installation without any problems. Perhaps you have not installed the full ise or the service packs ? Regards, Andreas Harald wrote: > >> I was explicitly told by EDK 9.2 that it no longer supports >> Spartan-II, Virtex, Virtex-E, Virtex-II, or Virtex-II Pro devices. ISE >> 9.2 may be the same. > > So the question is, if I am able to get a copy of ISE 9.1 ... > have to check the xilinx homepage... > > Cheers!Article: 126355
rickman schrieb: > BTW, if I am running Win2K, does it have the same 3.2 GB limitation or > is it less? I assume the 3.2 GB limit is from the 32 bit address > size? Why is it 3.2 instead of 4 GB? The devices on the PCI bus, for example, are memory mapped and eat up quite a lot of address space. There are ways to use the RAM between 3 and 4 GB, but you're on the safer side if you put 3 GB in your machine if you can live with that. Otherwise think about using an 64-bit OS. Xilinx has a web page that gives some details about the memory requirements of ISE depending on the target device. http://www.xilinx.com/ise/products/memory.htm Regards AndreasArticle: 126356
Matthew Hicks wrote: > I have created a custom peripheral in EDK 9.1/ISE 9.1 that needs to have > 100 registers and communicates with the PowerPC CPU via the PLB bus. [snip] > Therefore, I selected 32 registers and tried to change the USER_NUM_CE > constant in the top-level module in the > created template to 128, as opposed to 32. I have read the PLB IPIF > datasheet from Xilinx, which only says that USER_NUM_CE needs to be a > power of two, which is why I used 128 versus 100. After implementation, > access to any register above 32 leads to a returned value of zero, when > it should be non-zero. Any suggestions of what else I need to change in > the generated IPIF code to get this working? The wizard generates 2 files, the top file and the user logic file. Make sure that the constants are set up correctly in both files. --- JoeArticle: 126357
techG wrote: > How can I do to let EDK notice changes in vhdl files? project -> clean all generated files OR hardware -> clean hardware should do the trick. -JeffArticle: 126358
> Perhaps you have not installed the full ise or the service packs ? Thanks for your effort Andreas, I just updated the tool yesterday so this seems pretty strange. As I said, I have the same version as you, really weird that I cant find the Virtex2-XC2V6000 board in my options? Have to check this further!Article: 126359
> in the mean time i have made a test design for xc2v6000 on a windows > ise92.03i installation without any problems. I have Release Version 9.2.03i, Application version J.39 Have you probabaly got a full version? I just have downloaded the evaluation version, perhaps thats the reason? Cheers, HaraldArticle: 126360
Harald wrote: > >> in the mean time i have made a test design for xc2v6000 on a windows >> ise92.03i installation without any problems. > > I have Release Version 9.2.03i, Application version J.39 > Have you probabaly got a full version? I just have downloaded the > evaluation version, perhaps thats the reason? I have a full version. No V2, V2Pro, or S2 designs seemed to be available.Article: 126361
Dear Harald, i think you are currently using the ise webpack edition. the webpack is limited to the from you reported devices see also the list http://www.xilinx.com/ise/products/webpack_config.htm the ise 9.2.03i that i use is a full version, not a webpack edition Regards, Andreas Harald wrote: > >> Perhaps you have not installed the full ise or the service packs ? > > Thanks for your effort Andreas, I just updated the tool yesterday so > this seems pretty strange. As I said, I have the same version as you, > really weird that I cant find the Virtex2-XC2V6000 board in my options? > > Have to check this further!Article: 126362
Jim, > Do you have the xsvf file size handy, for your XC2C64 design ? > That would give Didi some info on the svf pathway. > (to go with the player info you've given) I am quite sure I can reproduce the entire chain of hoops in xapp058. It would allow me to eventually reverse engineer their jedec -> jtag mapping in a matter of days or may be weeks if I want to include more devices. The "impact" tool Antonio is using is not available on the xilinx website, but I am sure I could find it as well, it must be out there. Yet the question remains - _why_ do they keep the mapping data secret? I predicted we may wait for a century or so for a plausible answer - the first one we got from their CPLD support is more arrogant than it is ridiculous. Who does this person think is talking to, housewifes? Their JTAG interface is too complex for us to handle, yeah, in fact some of us have handled the coolrunner jtag interface before xilinx had a clue what the coolrunner was. I wonder if this reply is more arrogant and rude than the one I got from their "support" department 5-6 years ago, then they wanted me to make the $20M/quarter revenue before they would consider talking to me. I'll dig that message and post it here as well, this is the least their arrogance deserves. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ On Nov 20, 11:54 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Antonio Pasini wrote: > > Il 20/11/2007 0.06, Didi ha scritto: > > >>> 3) use Impact (free download) to translate the jedec in a XSVF binary > >>> file. You can do on GUI by hand, or by makefile as I prefer; syntax is: > > >> Now this is a hoop I can do without. XAPP058 actually states you have > >> to do jedec -> svf -> xsvf, and I see only the svf->xsvf tool freely > >> available. Is the tool for doing jedec->svf also freely available? > >> Can you point me to it please? > > > Impact makes the jedec -> svf OR jedec ->XSVF translation, with the > > commands of my previous posts. > > At the time of XAPP058, it wasn't able to. > > Now you can just go stright from jedec to XSVF with Impact alone. > > > Impact is free with the Webpack > > (http://www.xilinx.com/ise/logic_design_prod/webpack.htm). > > > (I remember that there's also a "production" package with just the > > Impact tool, but I don't find the link). > > Do you have the xsvf file size handy, for your XC2C64 design ? > That would give Didi some info on the svf pathway. > (to go with the player info you've given) > > (the XC2C64 has 3226.5 Bytes of fuse info.) > Usually svf have quite an overhead : > (eg an Atmel device with 2101.75 bytes of fuse info, > spawns a 110925 byte SVF file ~ 50:1 ) > > I have not tried to compress the SVF, but I'd guess 5-10 > simple compression should be easy, esp for a known brand. > So that brings it down to 10-20K bytes, for a 2K binary image. > > I also notice the Atmel tools can create a PCF via SVF2PCF, > for an even larger file, but one that is a logic analyser > storage - 191K lines, to JED pgm the 2KB fuses. > > -jgArticle: 126363
> see also the list http://www.xilinx.com/ise/products/webpack_config.htm > > the ise 9.2.03i that i use is a full version, not a webpack edition Yepp, that exactly seems to be the problem :( Not good news I have to admit.Article: 126364
> I wonder if this reply is more arrogant and rude than > the one I got from their "support" department 5-6 years > ago, then they wanted me to make the $20M/quarter revenue > before they would consider talking to me. My mistake, it has been $9M, not $20M. I put my archived thread at http://tgi-sci.com/misc/xiw.txt Here is the cutest excerpt: ======================================================================= To: <Caroline.Hughes@xilinx.com> From: Dimiter Popoff <tgi@bulnet.bg> Subject: Case # 293733 Coolrunner ZIA decoder bits Date: Wed, 15 Mar 2000 14:58:39 +0200 Mrs. Hughes, thank you for your reply - it answers my questions to a great extent. What I still do not understand is: >Our Major Accounts only have access to this information >i) When they have generated approximately $9M of revenue per quarter >with us. >ii) If they specifically ask for this information. Do only those comapnies get the information who cover both i) and ii) ? Does that mean that they all get access to the information only after they have made the first $9M/quarter for you, wether they have asked for this information before this or not? Regards, Dimiter Popoff ======================================================================= From: "Caroline Hughes" <Caroline.Hughes@xilinx.com> To: Dimiter Popoff <tgi@bulnet.bg> Date: Wed, 15 Mar 2000 13:41:55 +0000 Subject: Re: Case # 293733 Coolrunner ZIA decoder bits Mr. Popoff, I'm glad I managed to answer part of your question. In answer to the question below: > Does that mean that they all get access to the information only after > they have made the first $9M/quarter for you, wether they have asked > for this information before this or not? > They will not get automatic access to this information, they must first have made the $9M/quarter and then they must ask for it. Some customers may generate more than $9M/quarter, but if they do not ask for the information, they will not get it! I hope this resolves your query fully. Regards, Caroline Hughes. ======================================================================= Now we have them worried about our JTAG chain wellbeing. They are so hostile about these issues it is obviosly not just about the data being kept secret, there is more to it than that. I wish I knew what... Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ On Nov 20, 4:05 pm, Didi <didi...@gmail.com> wrote: > Jim, > > > Do you have the xsvf file size handy, for your XC2C64 design ? > > That would give Didi some info on the svf pathway. > > (to go with the player info you've given) > > I am quite sure I can reproduce the entire chain of hoops > in xapp058. It would allow me to eventually reverse engineer > their jedec -> jtag mapping in a matter of days or may be > weeks if I want to include more devices. > The "impact" tool Antonio is using is not available on the > xilinx website, but I am sure I could find it as well, it > must be out there. > Yet the question remains - _why_ do they keep the mapping > data secret? I predicted we may wait for a century or so > for a plausible answer - the first one we got from their > CPLD support is more arrogant than it is ridiculous. Who > does this person think is talking to, housewifes? Their > JTAG interface is too complex for us to handle, yeah, > in fact some of us have handled the coolrunner jtag interface > before xilinx had a clue what the coolrunner was. > I wonder if this reply is more arrogant and rude than > the one I got from their "support" department 5-6 years > ago, then they wanted me to make the $20M/quarter revenue > before they would consider talking to me. I'll dig that > message and post it here as well, this is the least their > arrogance deserves. > > Dimiter > > ------------------------------------------------------ > Dimiter Popoff Transgalactic Instruments > > http://www.tgi-sci.com > ------------------------------------------------------ > > On Nov 20, 11:54 am, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > > Antonio Pasini wrote: > > > Il 20/11/2007 0.06, Didi ha scritto: > > > >>> 3) use Impact (free download) to translate the jedec in a XSVF binary > > >>> file. You can do on GUI by hand, or by makefile as I prefer; syntax is: > > > >> Now this is a hoop I can do without. XAPP058 actually states you have > > >> to do jedec -> svf -> xsvf, and I see only the svf->xsvf tool freely > > >> available. Is the tool for doing jedec->svf also freely available? > > >> Can you point me to it please? > > > > Impact makes the jedec -> svf OR jedec ->XSVF translation, with the > > > commands of my previous posts. > > > At the time of XAPP058, it wasn't able to. > > > Now you can just go stright from jedec to XSVF with Impact alone. > > > > Impact is free with the Webpack > > > (http://www.xilinx.com/ise/logic_design_prod/webpack.htm). > > > > (I remember that there's also a "production" package with just the > > > Impact tool, but I don't find the link). > > > Do you have the xsvf file size handy, for your XC2C64 design ? > > That would give Didi some info on the svf pathway. > > (to go with the player info you've given) > > > (the XC2C64 has 3226.5 Bytes of fuse info.) > > Usually svf have quite an overhead : > > (eg an Atmel device with 2101.75 bytes of fuse info, > > spawns a 110925 byte SVF file ~ 50:1 ) > > > I have not tried to compress the SVF, but I'd guess 5-10 > > simple compression should be easy, esp for a known brand. > > So that brings it down to 10-20K bytes, for a 2K binary image. > > > I also notice the Atmel tools can create a PCF via SVF2PCF, > > for an even larger file, but one that is a logic analyser > > storage - 191K lines, to JED pgm the 2KB fuses. > > > -jgArticle: 126365
On Nov 19, 4:19 pm, Didi <didi...@gmail.com> wrote: > > > Well the fact of the matter is that there is no CPLD on the market > > > to compete with all the coolrunner parameters at the same time - and > > > I do use them. > > > Across the size range, you may be right. > > But at the highest volume end Atmel and Lattice have good low power > > offerings. Actel may start to impact > 128MC CPLDs > > I would be really happy to see an alternative to the coolrunner, > especially if its documentation is less secretive. Until then, > we are all stuck with xilinx for CPLDs above a certain complexity > and below some power, which is why I am still trying to get some > way to use them (notice I even accept to use their software to > produce the jedec file, something unprecedented here). > > > My understanding there is the parts were not externally foundry fab'd > > and when the plug was pulled on the fab line, that then killed the > > product line. ... > > Well I do not find it very plausible - making a new coolrunner line > from scratch cannot have been easier than repeating an existing > product, mask sets and all being available. > But whatever, their agreement with Philips was to support all > existing customers the way Philips had supported them. > This has not been the case with us - we do have the jedec -> jtag > maps from Philips and we do not have these from Xilinx. > > Dimiter > > ------------------------------------------------------ > Dimiter Popoff Transgalactic Instruments > > http://www.tgi-sci.com > ------------------------------------------------------ Hi Dimiter, Could you elaborate why you can't use other low power CPLD's, Lattice 4000Z, for example? I'm asking this question because in Lattice case there is C code supplied for you to make the kind of CPLD programming discussed in this thread very easy. AlexArticle: 126366
On Mon, 19 Nov 2007 09:12:30 -0800 (PST), "u_stadler@yahoo.de" <u_stadler@yahoo.de> wrote: >hi > >well yes i'm using model sim: >the driver listing from modelsim for the data_in signal is as follows: > >drivers spi_memory_tb_vhd/data_in ># Drivers for /spi_memory_tb_vhd/data_in(31:0): ># U : Signal /spi_memory_tb_vhd/data_in(31) ># 0 : Driver /spi_memory_tb_vhd/tb ># U : Element /spi_memory_tb_vhd/uut/data_in(31) This tells you the U is driven onto data_in by your "uut" component. Therefore Duane's advice applies. Why does your memory need to drive its Data_In bus? If it doesn't; simply make Data_in an IN port. If it does, make the UUT itself ... not the testbench... drive Data_In with 'Z' as Duane suggested, to replace the "U"... Either of these should solve the problem. Having changed the design, use the Drivers command again to verify the change. - BrianArticle: 126367
hi thanks for all your advices! i found the problem. somehow the signals in the component instantiation got messd up (although i used the testbench generated by ise). anyway the problem was that data_in, data_out and RD, WR, CLK where in the wrong order. the only thing im wondering is, shouldn't ise or modelsim throw a warning? urbanArticle: 126368
Hi We are thinking of buying a Xilinx Virtex5 evaluation board. At the moment this one seems to be our favorite: http://www.xilinx.com/products/devkits/HW-V5-ML505-UNI-G.htm Price is 1195$, which is quite reasonable. Are there perhaps other good products with a Virtex5 on it out there, perhaps some that have special prices for universities? Thanks P.Article: 126369
Luc, I understand your decision. And, I hope all goes well with your project. I will say that after what happened during the introduction of V4 FX, that Xilinx has placed many "gates" and "systems" to prevent a re-occurrence of that terrible time. To that end, the release of Virtex 5, and the GTP's, has been a real pleasure (for us, and our customers). AustinArticle: 126370
> Could you elaborate why you can't use other low power CPLD's, Lattice > 4000Z, for example? I'm asking this question because in Lattice case > there is C code supplied for you to make the kind of CPLD programming > discussed in this thread very easy. > > Alex I cannot - have not checked them recently, will do and will report :-). Dimiter On Nov 20, 4:38 pm, Alex <engin...@gmail.com> wrote: > On Nov 19, 4:19 pm, Didi <didi...@gmail.com> wrote: > > > > > Well the fact of the matter is that there is no CPLD on the market > > > > to compete with all the coolrunner parameters at the same time - and > > > > I do use them. > > > > Across the size range, you may be right. > > > But at the highest volume end Atmel and Lattice have good low power > > > offerings. Actel may start to impact > 128MC CPLDs > > > I would be really happy to see an alternative to the coolrunner, > > especially if its documentation is less secretive. Until then, > > we are all stuck with xilinx for CPLDs above a certain complexity > > and below some power, which is why I am still trying to get some > > way to use them (notice I even accept to use their software to > > produce the jedec file, something unprecedented here). > > > > My understanding there is the parts were not externally foundry fab'd > > > and when the plug was pulled on the fab line, that then killed the > > > product line. ... > > > Well I do not find it very plausible - making a new coolrunner line > > from scratch cannot have been easier than repeating an existing > > product, mask sets and all being available. > > But whatever, their agreement with Philips was to support all > > existing customers the way Philips had supported them. > > This has not been the case with us - we do have the jedec -> jtag > > maps from Philips and we do not have these from Xilinx. > > > Dimiter > > > ------------------------------------------------------ > > Dimiter Popoff Transgalactic Instruments > > >http://www.tgi-sci.com > > ------------------------------------------------------ > > Hi Dimiter, > > Could you elaborate why you can't use other low power CPLD's, Lattice > 4000Z, for example? I'm asking this question because in Lattice case > there is C code supplied for you to make the kind of CPLD programming > discussed in this thread very easy. > > AlexArticle: 126371
Philipp, Are you a university or school? If so, you should contact the XUP (Xilinx University Program). We often grant (gift), or partially fund university boards (like the Virtex II Pro board from Digilent that we will provide the FPGA on -- the school only pays for the pcb, not the FPGA). Otherwise (not a university), our distributors also have an array of Virtex 5 pcbs for sale, too. http://www.xilinx.com/onlinestore/v5_boards.htm (don't miss the HiTech Global, and TED/Inrevium links, at the bottom left). Austin Philipp wrote: > Hi > > We are thinking of buying a Xilinx Virtex5 evaluation board. At the > moment this one seems to be our favorite: > > http://www.xilinx.com/products/devkits/HW-V5-ML505-UNI-G.htm > > Price is 1195$, which is quite reasonable. Are there perhaps other good > products with a Virtex5 on it out there, perhaps some that have special > prices for universities? > > Thanks P.Article: 126372
The Virtex 5 Library has two design elements for the ISERDES. The ISERDES_NODELAY obviously does not include the delay element, but it has another difference. It has a secondary clock input (CLKB) that is not included in the ISERDES. CLKB is supposed to receive the inverted CLK for DDR mode. So I don't understand the difference - why doesn't ISERDES also have the CLKB input, and which is better to use for DDR mode? TIA, BarryArticle: 126373
austin wrote: > Philipp, > > Are you a university or school? If so, you should contact the XUP > (Xilinx University Program). We often grant (gift), or partially fund > university boards (like the Virtex II Pro board from Digilent that we > will provide the FPGA on -- the school only pays for the pcb, not the FPGA). Thanks for your answer Austin, yes I am at university. So I will check with the Xilinx University program. Unfortunately it seems that the board you are offering is too small for my purposes. I would need a evaluation board with at least a Virtex4 on it and around 25000 to 30.000 slices. If anyone knows a good resource where I could get such a board I would be thankful for some feedback ;) Cheers, PhilippArticle: 126374
Patrick Have a look at Broaddown4 http://www.enterpoint.co.uk/moelbryn/broaddown4.html. An alternative solution is the combination of our Broaddown2 (Spartan-3) with a add on Swinyard1 module. The Broaddown4 can support between 1-4(with 2 Swinyard1 modules) Virtex-4 LX40-160 or SX55 parts. Swinyard1 has a single Virtex-4 LX40-160 or SX55. Some outline details on our university program (UAP) is here http://www.enterpoint.co.uk/uap/uap.html. Discounts are listed there on some products, others are available, as are details of our Synplicity deal for universities where they effectively get a free license with a small pack of our low cost board Raggedstone1 and soon hopefully some others. John Adair Enterpoint Ltd. On 20 Nov, 16:04, Philipp <Patrick.Batema...@gmx.at> wrote: > austin wrote: > > Philipp, > > > Are you a university or school? If so, you should contact the XUP > > (Xilinx University Program). We often grant (gift), or partially fund > > university boards (like the Virtex II Pro board from Digilent that we > > will provide the FPGA on -- the school only pays for the pcb, not the FPGA). > > Thanks for your answer Austin, yes I am at university. So I will check > with the Xilinx University program. Unfortunately it seems that the > board you are offering is too small for my purposes. I would need > a evaluation board with at least a Virtex4 on it and around 25000 > to 30.000 slices. > > If anyone knows a good resource where I could get such a board I would > be thankful for some feedback ;) > > Cheers, > Philipp
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