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Messages from 125875

Article: 125875
Subject: Re: Non-volatile FPGA in a small package
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 08 Nov 2007 12:16:58 +1300
Links: << >>  << T >>  << A >>
rickman wrote:
> I am looking for my usual FPGA in a small package.  This is a contract
> design and the customer has a preference to avoid BGAs.  The only
> leaded part that will fit the board is a 100 pin TQFP.  I found a
> couple of MAX II devices in this package and Lattice has some MACHXO
> parts as well as one XP part.  Of the three, I like the XP better as
> it has 3000 LUTs to work with as well as PLLs.
> 
> Lattice also has an XP2 line which should be lower cost/higher density
> as well as lower power.  But they don't seem to be available yet.  I
> don't see stock on any parts and it looks like they are not supporting
> the TQ100 package.
> 
> I also wanted to consider the Xilinx XC3S-AN parts.  The combinations
> of device and package are very limited with a one to one
> relationship.  Each part comes in a different package and *only* that
> package.  So there is no chance to upgrade to a different density part
> once you design the board.  Of course, I don't think this is a real
> issues for this app, since any of the FPGA types are well large
> enough.  But I also can't find any pricing.  The other parts are all
> in the $10 - $15 range.  I have no idea if the XC3S-AN is in that same
> range.
> 
> So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts
> are ready for prime time?  Should I skip these parts and go with one
> of the other choices?  BTW, the customer has experience with the
> Altera parts and can already program them in system.  So that is a
> definite plus for the MAX II.  But it is otherwise at the back of the
> field with the least available LUTs and no PLL.  So I really want to
> use a different part.

Missing from the 'usual suspects' list seems to be Actel ?

I see their IGLOO series offers both VQ100 and QFN132 ?

VQ100 (14 x 14 mm)  	79  	71  	71  	68/13  	   	   	
QN132 (8 x 8 mm) 	81 	80 	84 	87/19

-jg



Article: 125876
Subject: Re: Custom processor developement issues
From: "KJ" <kkjennings@sbcglobal.net>
Date: Wed, 7 Nov 2007 18:33:46 -0500
Links: << >>  << T >>  << A >>

"argee" <nope@nope.com> wrote in message news:fgt7ir$4ie$1@ss408.t-com.hr...
> Hi all,
>
> I'm trying to find a simple way to check the functional correctness of a 
> custom processor/coprocessor/thingy on an FPGA (I'm kindo new at this). 
> The core itself is generated automatically (and as such should behave as 
> planned), so I only need to check if the algorithm that the processor is 
> supposed to run is working correctly. The processor operates on the data 
> in it's data memory and I'm looking for a simple way to check that 
> memory's contents, both during simulation and from the FPGA. Available 
> tools include Xilinx ISE Webpack + ModelSim XE and Altium Designer + 
> Nanoboard NB1 (Spartan2). During simulation I wasn't able to access the 
> memory's internal content (the VHDL variable) from ModelSim so I tried to 
> verify the design by observing processor/memory comunication which is 
> tedious and error-prone process (so is using a soft logical analyzer after 
> implementation). Btw. the implementation uses memories generated with 
> CoreGenerator if it makes any difference.
> So, is there a simple way to run the program on the FPGA and (after the 
> processor HALTs) read the results on my PC?

I usually add non-synthesizable code that monitors the memory controller and 
appends a line to a .CSV file every time a read or write is performed. 
Basic template for such logging is...

-- synthesis translate_off
process
  if (Reset = '1') then
    -- Overwrite existing xxx.csv file with a header line showing
    -- what signals will be written
else
    if (Memory_Write = '1') then
        -- Append to xxx.csv file with the address and data being written
    end if;
    if (Memory_Read = '1') then
        -- Append to xxx.csv file with the address and data being read from.
    end if;
end process;
-- synthesis translate_on

You can use standard VHDL text file I/O procedures to do the file stuff.  If 
you don't have one, you'll need something to convert std_logic_vectors into 
strings so that they can be output.  I use Ben Cohen's image package to do 
that work  Google link is
http://www.google.com/search?hl=en&q=image_pkg+Ben+Cohen

Formatting the output as a simple comma separated variable file means you 
can easily import it into a spreadsheet and do additional work if necessary. 



Article: 125877
Subject: Re: Non-volatile FPGA in a small package
From: "Marc A. Baker" <marc.baker@xilinx.com>
Date: Wed, 7 Nov 2007 15:34:18 -0800
Links: << >>  << T >>  << A >>
The Spartan-3AN family recently went into full production, with the XC3S50AN 
release imminent.  I would say that they are ready for prime time.  Pricing 
is definitely in the same range, partly as a result of the very limited 
package options - see the press release from the announcement, which notes a 
sub-$5 price for the XC3S200AN 
(http://www.xilinx.com/prs_rls/2007/silicon_spart/0734_spartan3an.htm).  Or 
you can get a Spartan-3AN Starter Kit with an XC3S700AN for only $225 
(http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3AN-SK-UNI-G-PROMO&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS) 
Unfortunately it takes a while to get pricing and availability onto 
distributor web sites, but that will come soon.

Marc Baker
Xilinx

"rickman" <gnuarm@gmail.com> wrote in message 
news:1194472016.283388.97470@50g2000hsm.googlegroups.com...
>I am looking for my usual FPGA in a small package.  This is a contract
> design and the customer has a preference to avoid BGAs.  The only
> leaded part that will fit the board is a 100 pin TQFP.  I found a
> couple of MAX II devices in this package and Lattice has some MACHXO
> parts as well as one XP part.  Of the three, I like the XP better as
> it has 3000 LUTs to work with as well as PLLs.
>
> Lattice also has an XP2 line which should be lower cost/higher density
> as well as lower power.  But they don't seem to be available yet.  I
> don't see stock on any parts and it looks like they are not supporting
> the TQ100 package.
>
> I also wanted to consider the Xilinx XC3S-AN parts.  The combinations
> of device and package are very limited with a one to one
> relationship.  Each part comes in a different package and *only* that
> package.  So there is no chance to upgrade to a different density part
> once you design the board.  Of course, I don't think this is a real
> issues for this app, since any of the FPGA types are well large
> enough.  But I also can't find any pricing.  The other parts are all
> in the $10 - $15 range.  I have no idea if the XC3S-AN is in that same
> range.
>
> So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts
> are ready for prime time?  Should I skip these parts and go with one
> of the other choices?  BTW, the customer has experience with the
> Altera parts and can already program them in system.  So that is a
> definite plus for the MAX II.  But it is otherwise at the back of the
> field with the least available LUTs and no PLL.  So I really want to
> use a different part.
> 



Article: 125878
Subject: Re: Custom processor developement issues
From: austin <austin@xilinx.com>
Date: Wed, 07 Nov 2007 15:39:43 -0800
Links: << >>  << T >>  << A >>
RG,

There is the ChipScope(tm) core in which you choose to capture events
and data, but unless you know exactly what the "answer" is, then it gets
difficult (you get lost in all the 1's and 0's).

You might like to take a page from manufacturing engineering, and use a
common technique to recognize the "right" answer quickly, which is the
use of "signatures."

A common method is to use a sum, an XOR, or a CRC generator (a running
LFSR on the data) to combine all of the results expected, and reduce
them to a single (short) number of perhaps 16 to 64 bits.  Parity alone
is a bit too simple (poor coverage), but multiple parities is sometimes
used (horizontal, vertical, and diagonal).

Then, the expected result is also calculated for the check, and compared
with the actual result.

It isn't 100% (you can find methods which are, but you don't really need
them if the probabilities are low enough, or you do enough tests
generally).  A 7 bit CRC will catch 100% of all single, double, etc. up
to 6 bit errors, for example in any data set.

Inside the FPGA, is is a pretty simple matter to place the expected
result, the calculated result, and a comparator, so that all you have to
do is look at one wire/bit/DFF/or LED (marked "answer was good").

Austin

Article: 125879
Subject: Re: Custom processor developement issues
From: "KJ" <kkjennings@sbcglobal.net>
Date: Wed, 7 Nov 2007 18:40:10 -0500
Links: << >>  << T >>  << A >>

"KJ" <kkjennings@sbcglobal.net> wrote in message 
news:vXrYi.1155$0Q5.815@nlpi070.nbdc.sbc.com...
>
Also add "wait on Reset, Memory_Write, Memory_Read;" to the start of the 
process in the previous post.

KJ 



Article: 125880
Subject: Re: Non-volatile FPGA in a small package
From: Alex <enginven@gmail.com>
Date: Wed, 07 Nov 2007 15:54:27 -0800
Links: << >>  << T >>  << A >>
On Nov 7, 2:46 pm, rickman <gnu...@gmail.com> wrote:
> I am looking for my usual FPGA in a small package.  This is a contract
> design and the customer has a preference to avoid BGAs.  The only
> leaded part that will fit the board is a 100 pin TQFP.  I found a
> couple of MAX II devices in this package and Lattice has some MACHXO
> parts as well as one XP part.  Of the three, I like the XP better as
> it has 3000 LUTs to work with as well as PLLs.
>
> Lattice also has an XP2 line which should be lower cost/higher density
> as well as lower power.  But they don't seem to be available yet.  I
> don't see stock on any parts and it looks like they are not supporting
> the TQ100 package.
>
> I also wanted to consider the Xilinx XC3S-AN parts.  The combinations
> of device and package are very limited with a one to one
> relationship.  Each part comes in a different package and *only* that
> package.  So there is no chance to upgrade to a different density part
> once you design the board.  Of course, I don't think this is a real
> issues for this app, since any of the FPGA types are well large
> enough.  But I also can't find any pricing.  The other parts are all
> in the $10 - $15 range.  I have no idea if the XC3S-AN is in that same
> range.
>
> So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts
> are ready for prime time?  Should I skip these parts and go with one
> of the other choices?  BTW, the customer has experience with the
> Altera parts and can already program them in system.  So that is a
> definite plus for the MAX II.  But it is otherwise at the back of the
> field with the least available LUTs and no PLL.  So I really want to
> use a different part.

Hi Rick,

Just wanted to let you know that XP2-5 engineering samples are
available now (and the FPGA should be in production by the end of the
year). TQ100 package isn't supported though, however if your customer
will agree to change the anti-BGA preference there is very small 132
pin csBGA package (8x8 mm, only three rows of pins going around the
perimeter) available.

Alex


Article: 125881
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: ghelbig@lycos.com
Date: 7 Nov 2007 16:53:36 -0800
Links: << >>  << T >>  << A >>
On Nov 5, 2:11 pm, Wojciech Zabolotny <w...@ipebio15.ise.pw.edu.pl>
wrote:
> Hi All,
>
> I'm looking for a possibility to run Linux (may be a ucLinux) on a
> XC3S500E containing CPU and some custom peripherials.
> The hardware platform should be a Spartan3E Starter Kit (rev. D),
> or something like this.
>
> I have found the almost ready to use solution here:http://muranaka.info/pukiwiki/index.php?MicroBlaze%20uClinux%20and%20...
> but it is MicroBlaze based, which is not acceptable for me due to
> licensing terms (which are even worse for the Ethernet MAC controller).
> Has anybody tried to use the aeMB clone with the free OpenCores Ethernet
> MAC controller with the MicroBlaze ucLinux?
>
> The OpenRisc and LEON3 seem to be too big for XC3S500E (or at least I
> was not able to trim them sufficiently for this FPGA).
>
> The most preferable solution seem to be a CPU which has a standard
> instruction set (e.g. Plasma, which is MIPS I compatible), because in
> this case the toolchain is well supported.
>
> However I could not find any information if it is possible to run Linux
> on the Plasma (or mips789) SOFT CPU.
> Has anybody any experience in that subject?
>
> There is an ideal solution announced on the OpenCores:http://www.opencores.org/projects.cgi/web/m1_core/overview
> But it is only an idea (Development status :: alpha)
> --
> TIA & Regards,
> Wojtek Zabolotny

Linux will run on a soft CPU, including ones that fit into the
XC3S500.  There are uClinux ports for both the MicroBlaze and NIOS.

A point to mention is that uClinux runs without a memory manager.
There just aren't enough gates to fit one in an FPGA.

If you can't find an open-source port to MicroBlaze or NIOS, look for
an ARM7 port.  An ARM7 is an ARM9 with the memory manager removed.

Hope that helps,
G.


Article: 125882
Subject: Re: Non-volatile FPGA in a small package
From: rickman <gnuarm@gmail.com>
Date: Wed, 07 Nov 2007 21:20:15 -0800
Links: << >>  << T >>  << A >>
On Nov 7, 6:54 pm, Alex <engin...@gmail.com> wrote:
> On Nov 7, 2:46 pm, rickman <gnu...@gmail.com> wrote:
>
> > I am looking for my usual FPGA in a small package.  This is a contract
> > design and the customer has a preference to avoid BGAs.  The only
> > leaded part that will fit the board is a 100 pin TQFP.  I found a
> > couple of MAX II devices in this package and Lattice has some MACHXO
> > parts as well as one XP part.  Of the three, I like the XP better as
> > it has 3000 LUTs to work with as well as PLLs.
>
> > Lattice also has an XP2 line which should be lower cost/higher density
> > as well as lower power.  But they don't seem to be available yet.  I
> > don't see stock on any parts and it looks like they are not supporting
> > the TQ100 package.
>
> > I also wanted to consider the Xilinx XC3S-AN parts.  The combinations
> > of device and package are very limited with a one to one
> > relationship.  Each part comes in a different package and *only* that
> > package.  So there is no chance to upgrade to a different density part
> > once you design the board.  Of course, I don't think this is a real
> > issues for this app, since any of the FPGA types are well large
> > enough.  But I also can't find any pricing.  The other parts are all
> > in the $10 - $15 range.  I have no idea if the XC3S-AN is in that same
> > range.
>
> > So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts
> > are ready for prime time?  Should I skip these parts and go with one
> > of the other choices?  BTW, the customer has experience with the
> > Altera parts and can already program them in system.  So that is a
> > definite plus for the MAX II.  But it is otherwise at the back of the
> > field with the least available LUTs and no PLL.  So I really want to
> > use a different part.
>
> Hi Rick,
>
> Just wanted to let you know that XP2-5 engineering samples are
> available now (and the FPGA should be in production by the end of the
> year). TQ100 package isn't supported though, however if your customer
> will agree to change the anti-BGA preference there is very small 132
> pin csBGA package (8x8 mm, only three rows of pins going around the
> perimeter) available.
>
> Alex


Ok, that is good to know.  But I still don't have any idea of the
price.  I would have thought that these parts would be a bit cheaper
than the XP line, but it looks like the smallest member of the family
is a bit bigger than in the XP line and has a lot more features.  So I
don't know if it will be any cheaper and may actually be a lot more
expensive since it only comes in packages with higher pin counts.  I
know that price correlates very strongly with I/O count.

Other than the issues with customer confidence (he had a bad
experience with Lattice tools once) either the XP or the MachXO line
seem to provide the most flexibility.  The XP is a lot larger and has
the PLL that I might need.  The MachXO uses the TQ100 package for all
four device sizes and the two largest also have a PLL.  The one
advantage of the Altera chips is that they appear to support a user
flash memory while the Lattice parts don't seem to have that.  This is
not a show stopper, just something to note.

Looking at the tools, it is not clear to me if I can really evaluate
them using ispLever Starter.  This package seems to not include the
full set of tools including the simulator and programmer.  So I can't
actually program a device with the starter tool, right?  Is the
simulator that comes with the ispLever package limited in any way?
The web site does not describe it very well.



Article: 125883
Subject: Re: Non-volatile FPGA in a small package
From: rickman <gnuarm@gmail.com>
Date: Wed, 07 Nov 2007 21:28:25 -0800
Links: << >>  << T >>  << A >>
On Nov 7, 6:34 pm, "Marc A. Baker" <marc.ba...@xilinx.com> wrote:
> The Spartan-3AN family recently went into full production, with the XC3S50AN
> release imminent.  I would say that they are ready for prime time.  Pricing
> is definitely in the same range, partly as a result of the very limited
> package options - see the press release from the announcement, which notes a
> sub-$5 price for the XC3S200AN
> (http://www.xilinx.com/prs_rls/2007/silicon_spart/0734_spartan3an.htm).  Or
> you can get a Spartan-3AN Starter Kit with an XC3S700AN for only $225
> (http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j...)
> Unfortunately it takes a while to get pricing and availability onto
> distributor web sites, but that will come soon.
>
> Marc Baker
> Xilinx

Thanks for the info.  If the XC3S50AN is not even in production yet I
am not so sure I am ready to use it.  Xilinx does not have a good
reputation for making parts available to the masses in early
production, much less preproduction.  Besides, I still have no idea
how much it will cost.  Saying it is $5 in qty 250,000 would make me
think I could get 100 at $10 each, but past experience has shown it
can be anywhere North of $20 instead.  That would not be very
competitive.

One thing Xilinx has in its favor is the reputation of the tools.
Even the web pack version seems to be pretty good.

But the skids are greased for Altera with the customer already having
support for programming them in-system.  Too bad the MAX II parts are
not the first choice technically.



Article: 125884
Subject: Re: Non-volatile FPGA in a small package
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Thu, 8 Nov 2007 08:47:08 +0000 (UTC)
Links: << >>  << T >>  << A >>
Marc A. Baker <marc.baker@xilinx.com> wrote:
> The Spartan-3AN family recently went into full production,  
> with the XC3S50ANrelease imminent.  I would say that they 
> are ready for prime time.  Pricing ...

As long as Digikey doesn't carry them, they are not ready...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 125885
Subject: Re: Non-volatile FPGA in a small package
From: Maki <prase.ruzicasto@gmail.com>
Date: Thu, 08 Nov 2007 09:08:41 -0000
Links: << >>  << T >>  << A >>
<snip>
> Looking at the tools, it is not clear to me if I can really evaluate
> them using ispLever Starter.  This package seems to not include the
> full set of tools including the simulator and programmer.  So I can't
> actually program a device with the starter tool, right?  Is the
> simulator that comes with the ispLever package limited in any way?
> The web site does not describe it very well.

No simulator but programmer is there. As for a hardware they offer a
cheap parallel and pricey USB programmer. I've used ispLever Starter
in several projects IMHO it is a good tool.

Regards,
Maki


Article: 125886
Subject: Re: Custom processor developement issues
From: argee <nope@nope.com>
Date: Thu, 08 Nov 2007 10:14:52 +0100
Links: << >>  << T >>  << A >>
Thank you all!

RG

Article: 125887
Subject: Re: Non-volatile FPGA in a small package
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 08 Nov 2007 11:53:36 +0000
Links: << >>  << T >>  << A >>
On Wed, 07 Nov 2007 21:28:25 -0800, rickman <gnuarm@gmail.com> wrote:

>On Nov 7, 6:34 pm, "Marc A. Baker" <marc.ba...@xilinx.com> wrote:
>> The Spartan-3AN family recently went into full production, with the XC3S50AN
>> release imminent.  I would say that they are ready for prime time.  Pricing
>> is definitely in the same range, partly as a result of the very limited
>> package options - see the press release from the announcement, which notes a
>> sub-$5 price for the XC3S200AN

>> Marc Baker
>> Xilinx
>
>Thanks for the info.  If the XC3S50AN is not even in production yet I
>am not so sure I am ready to use it.  Xilinx does not have a good
>reputation for making parts available to the masses in early
>production, much less preproduction.  Besides, I still have no idea
>how much it will cost.  Saying it is $5 in qty 250,000 would make me
>think I could get 100 at $10 each, but past experience has shown it
>can be anywhere North of $20 instead.  That would not be very
>competitive.

Searching em.avnet.com shows  	  XC3S50AN-4TQG144CES at $14.89 - no
stock of course, but "they say" 4 week leadtime. I believe that's a
notional 1-off price (no: "buy qty 22")  so  100-off is likely to be
closer to $14 than $5.

As for development, you can presumably use the equivalent  XC3S50A part
($12, for the -I grade, 16 in stock) to get started, and move to the -AN
when they appear. (Xilinx wouldn't make the pinouts incompatible, would
they? :-)

- Brian

Article: 125888
Subject: P160 Communication Module 3
From: ratemonotonic <niladri1979@gmail.com>
Date: Thu, 08 Nov 2007 12:06:05 -0000
Links: << >>  << T >>  << A >>
Hi All ,

I used the P160 Communication Module 3  add on card for memec xilinx
FPGA dev boards a year ago. Where has it gone? I cant find it on the
avnet memec site. Is it obsolete now?

BR
Rate


Article: 125889
Subject: Re: P160 Communication Module 3
From: Sean Durkin <news_nov07@durkin.de>
Date: Thu, 08 Nov 2007 13:31:18 +0100
Links: << >>  << T >>  << A >>
ratemonotonic wrote:
> Hi All ,
> 
> I used the P160 Communication Module 3  add on card for memec xilinx
> FPGA dev boards a year ago. Where has it gone? I cant find it on the
> avnet memec site. Is it obsolete now?
Since Avnet bought Memec, they were in a dilemma: Memec-boards used the
P160-connector, Avnet-boards something else. So for new boards designed
by Avnet-Memec they decided to introduce something new altogether, so
now P160 is obsolete... I suppose they just sold the rest of their stock
of P160-modules and didn't make any new ones...

cu,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 125890
Subject: Re: P160 Communication Module 3
From: ratemonotonic <niladri1979@gmail.com>
Date: Thu, 08 Nov 2007 12:56:54 -0000
Links: << >>  << T >>  << A >>
On 8 Nov, 13:31, Sean Durkin <news_no...@durkin.de> wrote:
> ratemonotonic wrote:
> > Hi All ,
>
> > I used the P160 Communication Module 3  add on card for memec xilinx
> > FPGA dev boards a year ago. Where has it gone? I cant find it on the
> > avnet memec site. Is it obsolete now?
>
> Since Avnet bought Memec, they were in a dilemma: Memec-boards used the
> P160-connector, Avnet-boards something else. So for new boards designed
> by Avnet-Memec they decided to introduce something new altogether, so
> now P160 is obsolete... I suppose they just sold the rest of their stock
> of P160-modules and didn't make any new ones...
>
> cu,
> Sean
>
> --
> My email address is only valid until the end of the month.
> Try figuring out what the address is going to be after that...

Oh no ! I Have done a preliminary system design with the assumption
that a addon ethernet MAC/PHY Chip like P160 comms 3 module will be
available, for my memec Spartan 3 LC devlopment kit. Is there any way
out of this dilemma?

BR
rate


Article: 125891
Subject: FIFO interface design
From: Readon <xydarcher@gmail.com>
Date: Thu, 08 Nov 2007 13:15:00 -0000
Links: << >>  << T >>  << A >>
   i want to read & write data to/from a fifo placed in fpga.  MCU's
external bus is connected to the chip. I am using the sync-fifo ip of
Altera CycloneII. The data bus and control signal are connected to
fifo directly. it's unfortune that when i read once from bus, data
would be read twice from fifo because there are two clock rising edges
during read signal(low active) is resetted. I think it will read more
datas from fifo if the read signal is resetted long enough.
   Is there any good design for fifo interface connecting on the
exteranl bus?


Article: 125892
Subject: Re: P160 Communication Module 3
From: Sean Durkin <news_nov07@durkin.de>
Date: Thu, 08 Nov 2007 14:15:26 +0100
Links: << >>  << T >>  << A >>
ratemonotonic wrote:
> Oh no ! I Have done a preliminary system design with the assumption
> that a addon ethernet MAC/PHY Chip like P160 comms 3 module will be
> available, for my memec Spartan 3 LC devlopment kit. Is there any way
> out of this dilemma?
When I asked my FAE about a year ago, I got the following response:

Re: XILINX MEMEC Boards Future:
We have developed a new expansion standard called EXP.  All new boards
will use this format, and AvBus and P160/P240 will go away.  We have
created a EXP-to-P160 adaptor to allow P160 modules to connect to the
new EXP boards.  You can see more info on EXP at www.em.avnet.com/exp

HTH,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 125893
Subject: Maximum current drive according to datasheet ?!
From: jidan1@hotmail.com
Date: Thu, 08 Nov 2007 05:30:14 -0800
Links: << >>  << T >>  << A >>
Hi,


I am using a Spartan-3 FPGA and want to drive an I/O pin to the
maximum current without damaging this pin. In the datasheet in
"Absolute Maximum Ratings", there it says:
 Iik Input clamp curent per I/O pin: ( -0.5 V < VIN < VCCO + 0.5 V):
=B1100 mA.



So, does that mean I connect a 33 OHM (=3D 3.3V/100 mA) from GND to an I/
O pin, and drive this pin high wihtout damaging the FPGA I/O pin?

Thanks,

JJ


Article: 125894
Subject: Re: Non-volatile FPGA in a small package
From: rickman <gnuarm@gmail.com>
Date: Thu, 08 Nov 2007 05:33:48 -0800
Links: << >>  << T >>  << A >>
On Nov 8, 6:53 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Wed, 07 Nov 2007 21:28:25 -0800, rickman <gnu...@gmail.com> wrote:
> >On Nov 7, 6:34 pm, "Marc A. Baker" <marc.ba...@xilinx.com> wrote:
> >> The Spartan-3AN family recently went into full production, with the XC3S50AN
> >> release imminent.  I would say that they are ready for prime time.  Pricing
> >> is definitely in the same range, partly as a result of the very limited
> >> package options - see the press release from the announcement, which notes a
> >> sub-$5 price for the XC3S200AN
> >> Marc Baker
> >> Xilinx
>
> >Thanks for the info.  If the XC3S50AN is not even in production yet I
> >am not so sure I am ready to use it.  Xilinx does not have a good
> >reputation for making parts available to the masses in early
> >production, much less preproduction.  Besides, I still have no idea
> >how much it will cost.  Saying it is $5 in qty 250,000 would make me
> >think I could get 100 at $10 each, but past experience has shown it
> >can be anywhere North of $20 instead.  That would not be very
> >competitive.
>
> Searching em.avnet.com shows      XC3S50AN-4TQG144CES at $14.89 - no
> stock of course, but "they say" 4 week leadtime. I believe that's a
> notional 1-off price (no: "buy qty 22")  so  100-off is likely to be
> closer to $14 than $5.
>
> As for development, you can presumably use the equivalent  XC3S50A part
> ($12, for the -I grade, 16 in stock) to get started, and move to the -AN
> when they appear. (Xilinx wouldn't make the pinouts incompatible, would
> they? :-)
>
> - Brian

Thanks, I had searched there, but I forgot to check "Search All Items"
rather than just stock.  I'll take a look for the 256BGA.


Article: 125895
Subject: Re: Maximum current drive according to datasheet ?!
From: "RCIngham" <robert.ingham@gmail.com>
Date: Thu, 08 Nov 2007 08:06:14 -0600
Links: << >>  << T >>  << A >>
>Hi,
>
>
>I am using a Spartan-3 FPGA and want to drive an I/O pin to the
>maximum current without damaging this pin. In the datasheet in
>"Absolute Maximum Ratings", there it says:
> Iik Input clamp curent per I/O pin: ( -0.5 V < VIN < VCCO + 0.5 V):
>=B1100 mA.
>
>
>
>So, does that mean I connect a 33 OHM (=3D 3.3V/100 mA) from GND to an
I/
>O pin, and drive this pin high wihtout damaging the FPGA I/O pin?
>
>Thanks,
>
>JJ
>
It is a very bad idea to operate at "Absolute Maximum Ratings" for
extended periods. These are "NEVER exceed" limits. You should not
intentionally exceed the "standard" output current limit (possibly 24mA,
depending on which output type you set this to be). If you need about an
amp of current drive, you will need an external high current driver, such
as an emitter follower.



Article: 125896
Subject: Re: Non-volatile FPGA in a small package
From: lb.edc@telenet.be
Date: Thu, 08 Nov 2007 14:06:44 GMT
Links: << >>  << T >>  << A >>
HI Rick,

I don't know where you are based, but there is a company in Germany
(www.hardware-design.de) that sells an XO-640 starter kit for
something like 75. This kit can be used as USB based programmer too
(it has all the pins available to the outside world).

I've seen prices for the XP2 (5K LUT) in T144 package for less then
$10 in normal quantities.

Besides - I've made a 50x50mm board with this device on it, got my ES
silicon pretty fast. This board has about 50 pins to be uses as a
mezzanine board.

Best regards,

Luc

On Wed, 07 Nov 2007 21:20:15 -0800, rickman <gnuarm@gmail.com> wrote:

>On Nov 7, 6:54 pm, Alex <engin...@gmail.com> wrote:
>> On Nov 7, 2:46 pm, rickman <gnu...@gmail.com> wrote:
>>
>> > I am looking for my usual FPGA in a small package.  This is a contract
>> > design and the customer has a preference to avoid BGAs.  The only
>> > leaded part that will fit the board is a 100 pin TQFP.  I found a
>> > couple of MAX II devices in this package and Lattice has some MACHXO
>> > parts as well as one XP part.  Of the three, I like the XP better as
>> > it has 3000 LUTs to work with as well as PLLs.
>>
>> > Lattice also has an XP2 line which should be lower cost/higher density
>> > as well as lower power.  But they don't seem to be available yet.  I
>> > don't see stock on any parts and it looks like they are not supporting
>> > the TQ100 package.
>>
>> > I also wanted to consider the Xilinx XC3S-AN parts.  The combinations
>> > of device and package are very limited with a one to one
>> > relationship.  Each part comes in a different package and *only* that
>> > package.  So there is no chance to upgrade to a different density part
>> > once you design the board.  Of course, I don't think this is a real
>> > issues for this app, since any of the FPGA types are well large
>> > enough.  But I also can't find any pricing.  The other parts are all
>> > in the $10 - $15 range.  I have no idea if the XC3S-AN is in that same
>> > range.
>>
>> > So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts
>> > are ready for prime time?  Should I skip these parts and go with one
>> > of the other choices?  BTW, the customer has experience with the
>> > Altera parts and can already program them in system.  So that is a
>> > definite plus for the MAX II.  But it is otherwise at the back of the
>> > field with the least available LUTs and no PLL.  So I really want to
>> > use a different part.
>>
>> Hi Rick,
>>
>> Just wanted to let you know that XP2-5 engineering samples are
>> available now (and the FPGA should be in production by the end of the
>> year). TQ100 package isn't supported though, however if your customer
>> will agree to change the anti-BGA preference there is very small 132
>> pin csBGA package (8x8 mm, only three rows of pins going around the
>> perimeter) available.
>>
>> Alex
>
>
>Ok, that is good to know.  But I still don't have any idea of the
>price.  I would have thought that these parts would be a bit cheaper
>than the XP line, but it looks like the smallest member of the family
>is a bit bigger than in the XP line and has a lot more features.  So I
>don't know if it will be any cheaper and may actually be a lot more
>expensive since it only comes in packages with higher pin counts.  I
>know that price correlates very strongly with I/O count.
>
>Other than the issues with customer confidence (he had a bad
>experience with Lattice tools once) either the XP or the MachXO line
>seem to provide the most flexibility.  The XP is a lot larger and has
>the PLL that I might need.  The MachXO uses the TQ100 package for all
>four device sizes and the two largest also have a PLL.  The one
>advantage of the Altera chips is that they appear to support a user
>flash memory while the Lattice parts don't seem to have that.  This is
>not a show stopper, just something to note.
>
>Looking at the tools, it is not clear to me if I can really evaluate
>them using ispLever Starter.  This package seems to not include the
>full set of tools including the simulator and programmer.  So I can't
>actually program a device with the starter tool, right?  Is the
>simulator that comes with the ispLever package limited in any way?
>The web site does not describe it very well.
>

Article: 125897
Subject: Re: Maximum current drive according to datasheet ?!
From: jidan1@hotmail.com
Date: Thu, 08 Nov 2007 06:19:34 -0800
Links: << >>  << T >>  << A >>
On 8 Nov., 15:06, "RCIngham" <robert.ing...@gmail.com> wrote:
> >Hi,
>
> >I am using a Spartan-3 FPGA and want to drive an I/O pin to the
> >maximum current without damaging this pin. In the datasheet in
> >"Absolute Maximum Ratings", there it says:
> > Iik Input clamp curent per I/O pin: ( -0.5 V < VIN < VCCO + 0.5 V):
> >=B1100 mA.
>
> >So, does that mean I connect a 33 OHM (=3D 3.3V/100 mA) from GND to an
> I/
> >O pin, and drive this pin high wihtout damaging the FPGA I/O pin?
>
> >Thanks,
>
> >JJ
>
> It is a very bad idea to operate at "Absolute Maximum Ratings" for
> extended periods. These are "NEVER exceed" limits. You should not
> intentionally exceed the "standard" output current limit (possibly 24mA,
> depending on which output type you set this to be). If you need about an
> amp of current drive, you will need an external high current driver, such
> as an emitter follower.- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -


I don't want actually to drive a load with 100mA;the thing is that I
will connect different boards on this board with the FPGA. I want to
protect the FPGA output pins from short-circuits to GND, without
effecting the maximum datatransfer (100 MHz). The simplest solution I
found  is connecting a series resistor. The question now is what
resistor value should I use. If I used a resistor as high as 150 Ohm
(~3.3V/24ma) I might not be able to transfer data rate up to 100 MHz.
Yous see what my problem is!

JJ


Article: 125898
Subject: Spartan 3E config
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Thu, 08 Nov 2007 08:27:19 -0600
Links: << >>  << T >>  << A >>

Hi

Does anyone know if it is possible to configure a Virtex 4 using a Spartan
3E. I want to connect a Flash memory to the Spartan and set this to be the
master.  Once configured I want the Virtex 4 that is the slave to
configure.

Cheers

Jon 

Article: 125899
Subject: Re: Non-volatile FPGA in a small package
From: Alex <enginven@gmail.com>
Date: Thu, 08 Nov 2007 06:39:30 -0800
Links: << >>  << T >>  << A >>
On Nov 8, 2:08 am, Maki <prase.ruzica...@gmail.com> wrote:
> <snip>
>
> > Looking at the tools, it is not clear to me if I can really evaluate
> > them using ispLever Starter.  This package seems to not include the
> > full set of tools including the simulator and programmer.  So I can't
> > actually program a device with the starter tool, right?  Is the
> > simulator that comes with the ispLever package limited in any way?
> > The web site does not describe it very well.
>
> No simulator but programmer is there. As for a hardware they offer a
> cheap parallel and pricey USB programmer. I've used ispLever Starter
> in several projects IMHO it is a good tool.
>
> Regards,
> Maki

You can get a 60 days evalution for full ispLever tool including
Modelsim for Lattice (without any performance limitations) it,
probably, will cover the time-frame you'll need.

Alex




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