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Mordehay, It is hardware, part of the IBM PPC, designed for adding auxiliary processing capability to the processor. It gets used with a "soft core" Floating Point Unit (FPU), for example. The APU allows for faster transfers of data to and from CPU registers, and also transfers to and from memory. The APU has direct access to the instruction decoder, too. AustinArticle: 125776
Hi I am designing a board with a Virex 4 and a DDR2 component. I have used the MIG tool to generate an interface. However the pinout it has generted is not ideal as there are a lot of crossed nets. Can I tweak the nets to give me better routing or will this leave me with a non working interface. I cant really see any reason why it still wouldn't work. Cheers JonArticle: 125777
I think it should be possible to design a 16-bit interface wrapper around the GTP. Buf if you are using the PCIE_EP hard block then the Transceiver interface is 8-bit PIPE interface. So we don't gain much by having a 16-bit interface wrapper for GTP. In my design I have registers in all the connections between PCIE_EP and GTP. It works fine for x1 and x4. There wasn't any timing issue. My core_clock is 250 MHz and user_clock is 125 MHz. -Sovan.Article: 125778
Jon, Did you create or edit the UCF (user constraint file) as noted in: http://direct.xilinx.com/bvdocs/whitepapers/wp260.pdf Step 2 of the flow chart? This is where you choose the pins you want to use (constraint eh design to use the pins you would like to use). If you don't chose, the tools will choose for you. If you choose pins that can not work, the tools will tell you that timing can't be met. For example, choice of pins that should be together (like a data bus) need to be in the same bank, or for wide interfaces, adjacent banks. AustinArticle: 125779
"G Iveco" <G.Iveco@google.com> wrote in message
news:fgi30n$245$1@reader01.singnet.com.sg...
> Hi, there
>
> My design needs a 16X16 matrix, each of 32-bit. The matrix must
> be read row by row or column by column each in one clock..
>
> Direct register implementation takes a lot of resources and routing can
> be difficult. Will 256 pieces of 32-bit RAM with single address work
> in Xilinx?
>
> TIA!
>
>>IF<< you can garantee that all R/W accesses will be row or column based,
you can get away with 16 BRAMs arranged in a diagonal pattern.
r0c0
r1c1
r2c2
...
r15c15
Regards,
Alvin.
Article: 125780On 11 5 , 4 45 , sovan <sovan.ku...@gmail.com> wrote: > I think it should be possible to design a 16-bit interface wrapper > around the GTP. Buf if you are using the PCIE_EP hard block then the > Transceiver interface is 8-bit PIPE interface. So we don't gain much > by having a 16-bit interface wrapper for GTP. > > In my design I have registers in all the connections between PCIE_EP > and GTP. It works fine for x1 and x4. There wasn't any timing issue. > My core_clock is 250 MHz and user_clock is 125 MHz. > > -Sovan. I only need the PCIE GTP wrapper of Xilinx Endpoint Block,no Endpoint Block hard core.I have customized my PCIE controller.it works well. But i need a 16bit interface wrapper around the GTP.so,my user_clk can be reduced 125MHz. my steps is 1>generate a standard 16bit PCIE wrapper with Xilinx Coregen wizard1.7 2>overwritte the all 16bit file tile header parameters with 8bit PCIE Endpoint Block parameter any other modified?Article: 125781
Hello, I would like to try to get some audio output from my Spartan 3 starter kit board, but as a hardware novice I worry about damaging my board. Is there any risk of damage if I connect a piezoelectric speaker directly to the pins of my FPGA? I have read that because of the high impedance of this device it should be OK, but I would like to have a better understanding. Thanks, BryanArticle: 125782
water9580@yahoo.com wrote: > There are some MAXDELAY=1ns constrain for TX signals inside PCIE > coregen. > eg: > (* MAXDELAY="1.0" *) wire [1:0] tile0_txcharisk0_r; > (* MAXDELAY="1.0" *) wire tile0_txdetectrx0_r; > (* MAXDELAY="1.0" *) wire tile0_txelecidle0_r; > (* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispmode0_r; > (* MAXDELAY="1.0" *) wire [15:0] tile0_txdata0_r; > (* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispmode1_r; > (* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispval1_r; > (* MAXDELAY="1.0" *) wire tile0_txdetectrx1_r; > (* MAXDELAY="1.0" *) wire [19:0] tile0_txdata1_r; > (* MAXDELAY="1.0" *) wire tile0_txelecidle1_r; > > > but,my core_clk is 4ns(250MHz) and user_clk is 8ns(125MHz). does it > still meet the MAXDELAY=1ns timing requirement? The MAXDELAY is an attribute for a net route and has nothing to do with clocks. From the driver of this net to the destination, the place & route must keep the delay under a nanosecond or it WILL report a timing violation. You can even use MAXDELAY attributes on clockless logic.Article: 125783
Now that Xilinx has released Microblaze 7.0 with an optional MMU (in EDK 9.2), has anyone started working on a Linux port? There's already a uClinux port to Microblaze with no MMU, but for some applications it would be nice to run "normal" Linux.Article: 125784
i am having two PROCESS to take advantage of dual-edge behavior of the clock pulse. one process takes care of the rising edge while the other process takes care of the falling edge. For the two processes, they are basically doing exactly the same thing just that one does it during rising and the other does it during falling.. i have a problem here, bcos i have two sets of variables that does the same thing, i would to ask how do i change it to global variables.. example PROCESS1 variable countera; variable check1; PROCESS2 variable counterb; variable check2; both countera/b and check1/2 are exactly the same thing but they are being declared in the process loop. may i know how do i write the code to change it to a shared variable that can be used in both process 1 and 2, that means i only have two variables in counter and check rather than the four that i am having now.. pls help. thanksArticle: 125785
Antti wrote: > eh the bmm approuch works. > after some months-years ;) > > is your memory 8 or 16 bits? > if 8 then make the bram block 8 not 16 as in your bmm > > connect chipscope to the ram add and data and let it run and look > > Antti > Just to record the solution which I found last week: Indeed 8 bits. The bmm file only needed to changed into cpu_inst/rom/Mrom_D1 [7:0]; The problem occurred because the declaration of the romsize was bigger than actually initialized which is corrected in the xilinx software, but during the ngdbuild phase the reduced romsize should be taken into account. Very logical actually, but that's with many things... taco > > > On 31 Okt., 15:58, taco <trala...@joepie.nl> wrote: >> hello, >> Has anybody experience with xilinx bitfile merging using a bmm file? >> I've a small processor core running in a spartan 3A using romcode which I >> install into a generated vhdl file. >> like >> entity ROM is >> port( >> Clk : in std_logic; >> A : in std_logic_vector(12 downto 0); >> D : out std_logic_vector(7 downto 0) >> ); >> end ROM; >> >> architecture rtl of ROM is >> signal A_r : std_logic_vector(12 downto 0); >> type rom_type is array(0 to 1951) of std_logic_vector(7 downto >> 0); signal ROM:rom_type := ( >> X"02", >> X"00", >> X"08", >> etc. >> This works fine (programming running), but I would like to replace this >> with a generic rom file without any initialization or just zero's and >> merge the romhexfile into the bitfile using a bmm. For the situation >> above the following bmm file doesn't give any errors: >> ADDRESS_MAP TV51MAP PPC405 0 >> ADDRESS_BLOCK CPU_INST_ROM RAMB16 [0X0000:0X7ff] >> BUS_BLOCK >> cpu_inst/rom/Mrom_D1 [15:0]; >> END_BUS_BLOCK; >> END_ADDRESS_BLOCK; >> END_ADDRESS_MAP; >> It's possible to force a location etc. and a _bd.bmm is generated like >> the documentation describes. >> I call ngdbuild with: >> if ngdbuild -bm cpu_rom.bmm -intstyle ise -dd _ngo -uc $(CONSTRAINTFILE) >> -p $(DEVICE) $(DESIGN).ngc $(DESIGN).ngd >> and bitgen with >> bitgen -bd src/test.mem -w -g UnusedPin:PullNone $< $@ $(DESIGN).pcf >> (so only the -bm and -bd arguments are added into the Makefile.) >> The mem file looks like: >> @00 02 >> @01 00 >> @02 08 >> @03 12 >> @04 00 >> @05 95 >> @06 80 >> The new bitfile is generated, but no luck. Program not running. >> Anybody an idea how to tackle this? >> Taco walstraArticle: 125786
Specification EDK version:8.2i FPGA Board: Virtex II Pro My source code requires g++ compiler. However, when trying to use g++ to compile a very simple code on EDK 8.2i, the following error appears. /microblaze_a0/lib//libxil.a(xilfatfs_wd.o): In function `make_root_directory': /cygdrive/c/............/microblaze_a0/libsrc/xilfatfs_v1_00_a/src/src/ xilfatfs_wd.c(.text+0x238): undefined reference to `get_partition_info' collect2: ld returned 1 exit status This linker error does not occur when using gcc compiler, but my source code requires g++ compilation. Has anyone encountered this problem before? Maybe its possible the xilfatfs_fat.c file is written for gcc compiler only..... Priyantha De SilvaArticle: 125787
>I would like to try to get some audio output from my Spartan 3 starter >kit board, but as a hardware novice I worry about damaging my board. > >Is there any risk of damage if I connect a piezoelectric speaker >directly to the pins of my FPGA? I have read that because of the high >impedance of this device it should be OK, but I would like to have a >better understanding. The main danger is that mechanical shock to the speaker can produce a high voltage at its terminals (even where your equipment is turned off). This can damage a semiconductor device. Does anyone here know the simplest way to avoid this? I'd guess that a 5V zener diode across the speaker should work, but maybe there's a better way. (Some semiconductor devices have internal "clamp" diodes to their power rails and this provides some protection, but an FPGA intended for use in a "hot insertion" product probably doesn't have these diodes). The (electrical) impedance of the speaker depends on frequency: there will be (mechanical) resonances at certain frequencies. Generally, you can expect the impedance to be less when the sound is louder. However, for a small speaker such as you might use for experiments, even the minimum impedance is unlikely to overload an FPGA output. MikeArticle: 125788
>i am having two PROCESS to take advantage of dual-edge behavior of the >clock pulse. one process takes care of the rising edge while the other >process takes care of the falling edge. For the two processes, they >are basically doing exactly the same thing just that one does it >during rising and the other does it during falling.. i have a problem >here, bcos i have two sets of variables that does the same thing, i >would to ask how do i change it to global variables.. > >example > >PROCESS1 > variable countera; > variable check1; > >PROCESS2 > variable counterb; > variable check2; > >both countera/b and check1/2 are exactly the same thing but they are >being declared in the process loop. may i know how do i write the code >to change it to a shared variable that can be used in both process 1 >and 2, that means i only have two variables in counter and check >rather than the four that i am having now.. pls help. thanks > > Is this meant to be VHDL, and is it intended to be synthesized to an FPGA? If synthesizeable VHDL, I strongly suggest "DO NOT USE SHARED VARIABLES." You normally declare signals in the architecture scope if you need to write them in one process and read them in another. However, no FPGA of which I am aware has dual edge triggered flip-flops, except in DDR IO blocks (and even there they are rather tricky). What problem are you actually trying to solve?Article: 125789
>Be specific. What do you mean by "this" ? Your posting is #10 in a >thread... >Peter Alfke > >On Nov 2, 3:10 am, "RCIngham" <robert.ing...@gmail.com> wrote: >> This looks like "voodoo design" to me. >> Seehttp://foldoc.org/?voodoo+programmingfor the software equivalent. >> >> If you know what the problem really is, design for that. Use series or >> parallel termination to mitigate ground-bounce, for instance. > The originally-posted circuit and the various minor modifications to it to cover for unknown circumstances...Article: 125790
On Nov 5, 1:15 am, Eric Smith <e...@brouhaha.com> wrote: > Now that Xilinx has released Microblaze 7.0 with an optional MMU (in > EDK 9.2), has anyone started working on a Linux port? > > There's already a uClinux port to Microblaze with no MMU, but for > some applications it would be nice to run "normal" Linux. I've heard word that some distro's may be working on supporting it, but no specifics. It shouldn't be too difficult to take the non-MMU version and add MMU capability.Article: 125791
On Nov 5, 6:11 am, "RCIngham" <robert.ing...@gmail.com> wrote: > >i am having two PROCESS to take advantage of dual-edge behavior of the > >clock pulse. one process takes care of the rising edge while the other > >process takes care of the falling edge. For the two processes, they > >are basically doing exactly the same thing just that one does it > >during rising and the other does it during falling.. i have a problem > >here, bcos i have two sets of variables that does the same thing, i > >would to ask how do i change it to global variables.. > > >example > > >PROCESS1 > > variable countera; > > variable check1; > > >PROCESS2 > > variable counterb; > > variable check2; > > >both countera/b and check1/2 are exactly the same thing but they are > >being declared in the process loop. may i know how do i write the code > >to change it to a shared variable that can be used in both process 1 > >and 2, that means i only have two variables in counter and check > >rather than the four that i am having now.. pls help. thanks > > Is this meant to be VHDL, and is it intended to be synthesized to an FPGA? > If synthesizeable VHDL, I strongly suggest "DO NOT USE SHARED VARIABLES." > > You normally declare signals in the architecture scope if you need to > write them in one process and read them in another. However, no FPGA of > which I am aware has dual edge triggered flip-flops, except in DDR IO > blocks (and even there they are rather tricky). > > What problem are you actually trying to solve? DDR registers in FPGAs can be emulated with two flops and three XOR gates (no clock gating, glitchless output, 100% STA compatible), as has been posted on here many times. Unfortunately, there are no synthesis tools that will implement a general two clock process with the circuit. Those that even accept two clock processes insist on not updating the same signal/variable on both clocks. AndyArticle: 125792
Hi Vince, There is an example for the ProASIC3 board on Actel webpage with complete design files and documentation. But this design does not use the PLL. http://www.actel.com/products/hardware/devkits_boards/proasic3_starter.aspx Check that the POWERDOWN input signal for the PLL is connected correctly. By default this input is Active low and should therefore be connected to '1'. When generating the PLL macro you can see/change this configuration. If this is not the problem let me know and I can send you an example. BR RouzbehArticle: 125793
On Oct 31, 2:08 am, sendt...@gmail.com wrote:
> SoI'veimplementedaNIOSIIboardusingtheSOPCbuilder. I ran out
> of on-chip memorysoI went off-chip to the DE2's SRAM. Suddenly my
> programs stopped working and the for loops has an unusual behavior.
>
> It'll go outside of the for loop..
>
> for instance:
> -----------------
> //assume variables defined
>
> For (i = 0; i < 3999999; i++)
> {
> IOWR_8DIRECT(memory_base, i, 0xff); //Writes all 1's to SDRAM
>
> }
>
> printf("Finished...\n");
>
> ... more code...
>
> ------------------
>
> What ends up happening is that the loop will run with the
> printf("Finished...") statement and repeat for the duration of the
> loop.
>
> Output:
> Finished...
> Finished...
> Finished...
> .
> .
> You get the idea... I didn't let it loop 4 million times you see what
> happened.
>
> This ONLY happens when I use the SRAM. If I use the SDRAM or the on-
> chip memory it works fine.
>
> Any one run into this problem?
>
> Thanks,
> el
There are no reported problems with the DE2 SRAM behavior in the field
(from many thousands of users), so at least the problem you are seeing
is not common. One possible explanation could be timing constraints.
As I'm sure you know, it is a good idea to include proper Tco and Tsu
constraints when dealing with any device outside of the FPGA. We have
previously seen a similar error for one customer, and the error was
fixed when they added I/O timing constraints for the SRAM.
Article: 125794My memory served me poorly, and Ed McGettigan corrected me, thanks: Virtex outputs have an optional week keeper. as described in the User guide: PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers, the output can havea weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. For input IBUF) buffers, the input can have either a weak pull-up resistor or a weak pull-down resistor. This feature can be invoked by adding the following possible constraint values to the relevant net of the buffers: =B7 PULLUP =B7 PULLDOWN =B7 KEEPER On Nov 4, 9:22 am, Peter Alfke <al...@sbcglobal.net> wrote: > On Nov 2, 4:19 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > > > > Peter Alfke wrote: > > > Kolja, I see it differently: > > > A weak keeper has two disadvantages: > > > It is weak, and might be overridden by crosstalk > > > It consumes constant power when the signal is pulled Low. > > > What you have described is a pullup ? > > Keepers, also called Bus-hold, or PinKeepers (depends on which vendor > > you are), are snap-action positive feedback 'very light' drivers, and > > they draw no power in either state. (typically hundreds of uA) > > > Of course, a disadvantage of that, is the Pin state is now undefined at > > PowerUP, and that may be a bad thing. > > > The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis. > > > -jg > > Since Xilinx FPGAs never had weak keepers on the user I/O, I got the > nomenclature confused. Sorry. > You can of course emulate a weak keeper by using the output driver at > its weakest setting, but that may still be too strong in some > applications (but not for switch debouncing). > BTW, I should have mentioned that the switch must be break-before-make > (obviously). > Peter AlfkeArticle: 125795
I have an application with a Xilinx Spartan3 FPGA where I would like to use a single FPGA binary to support to I/O voltage levels: 2.8v and 1.8v. My question is as follows: Why does the UCF file include the selected IO standard for each pin? I understand that the drive strengths and slew may change based on the I/O standard. Are there any other functional hardware changes made based on the selected standard? What are the potential consequences of telling the compiler that I am using 2.8v but then running the application with 1.8v? ThanksArticle: 125796
On 5 nov, 16:13, rouzbe...@actel.com wrote: > Hi Vince, > > There is an example for the ProASIC3 board on Actel webpage with > complete design files and documentation. > But this design does not use the PLL.http://www.actel.com/products/hardware/devkits_boards/proasic3_starte... > > Check that the POWERDOWN input signal for the PLL is connected > correctly. > By default this input is Active low and should therefore be connected > to '1'. > When generating the PLL macro you can see/change this configuration. > > If this is not the problem let me know and I can send you an example. > > BR > Rouzbeh Hi Rouzbeh, I just have problems with the PLL macro, I have developed some examples on this board already using CoreABC, UART, VHDL Project etc. so I know how to work with the board. But always when I use the STATIC PLL Macro it gives me problems... I can't get it running correctly. Can you send me an example (where I get a 10MHz and 40MHz clock out of the static pll macro? (I can't find a static pll example on the ACTEL website) Thanks for your help, kind regards. VinceArticle: 125797
On Nov 5, 4:26 pm, jtin...@gmail.com wrote: > I have an application with a Xilinx Spartan3 FPGA where I would like > to use a single FPGA binary to support to I/O voltage levels: 2.8v and > 1.8v. My question is as follows: > > Why does the UCF file include the selected IO standard for each pin? It doesn't have to, but if you don't include the IO standard you get the global default (which depends on the device family). > I understand that the drive strengths and slew may change based on the > I/O standard. Are there any other functional hardware changes made > based on the selected standard? What are the potential consequences > of telling the compiler that I am using 2.8v but then running the > application with 1.8v? > > Thanks The obvious changes in hardware are the Vcco (Bank IO power supply) and Vref (reference voltage for single-ended standards requiring a reference). The placement tools make sure that the standards are compatible for all IO's in each bank. i.e you can't mix IO's that require Vcco at 1.8V with those that require Vcco at 2.5V in the same bank. Similar for inputs requiring different Vref in a bank. Some input standards don't use a reference voltage, but may need a particular Vcco voltage. Output standards all need a specific Vcco. Telling the tools you are running at 2.5V (did you mean 2.5 and not 2.8?) but powering Vcco with 1.8V will result in hardware that does not match the simulation in terms of timing and drive capability and in some cases just won't work.Article: 125798
On Nov 5, 3:26 pm, jtin...@gmail.com wrote: > I have an application with a Xilinx Spartan3 FPGA where I would like > to use a single FPGA binary to support to I/O voltage levels: 2.8v and > 1.8v. My question is as follows: > > Why does the UCF file include the selected IO standard for each pin? > I understand that the drive strengths and slew may change based on the > I/O standard. Are there any other functional hardware changes made > based on the selected standard? What are the potential consequences > of telling the compiler that I am using 2.8v but then running the > application with 1.8v? > > Thanks Different IO standards have different voltage tolerances for determining 1 vs 0. Also, they have different termination methods for signal integrity and drive strength. If you use a lower voltage in a higher voltage setting, its possible that you'll never 'see' a transition inside the FPGA since its being set for higher tolerances. Also, FPGAs usually have a voltage requirements for their IO banks. An IO bank being a group of IO pins. This IO bank should (probably) have a requirement that all pins in a bank use a compatible IO standard. This can be limited to requiring the same voltage used in the bank, or maybe even the same type of signalling in the bank.Article: 125799
jt, The strength of the driver depends on the selected number of "legs" enabled, and the attributes (FAST or SLOW) for any particular Vcco voltage. IO's that require a Vref will require a different Vref voltage externally to operate properly. LVDS only works at 2.5 volts (in the latest parts). But, a LVCMOS IO that is set for 12 mA in the highest Vcco, will still be fairly strong at a lower Vcco. Timing, rise and fall times will be slower at lower Vcco, but the LVCMOS IO will still function just fine. To really make sure this will work, I would download the SPICE models, and run them at the different Vcco voltages, and make sure the signal integrity met all of your needs. The reason for simulating with SPICE is that you can change the Vcco, and see the result of fast and slow process corner material, as well as how the IO behaves with temperature. Austin
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