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There are a number of companies that have either reduced cost, or free, tools for academic use. We do special deals on our development boards. Our partners Aldec, Synplicity and Xilinx have development tools available under university programs. Some details of our university program and some of joint offerings with our partners here http://www.enterpoint.co.uk/uap/uap.html. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 17 Jul, 10:25, gouaich <goua...@lirmm.fr> wrote: > Hi all, > > First of all I just joined this group so let me salute all members !! > > I have a request and I would be happy is someone could help. > > You all probably know that embedded systems are more and more > considered as hot topics to be though at universities. I will be in > charge of managing a complete course for graduate students on embedded > system with a focus on software engineering and operating systems for > embedded platforms. > > Since having only a theoretical course is quite a boring activity : ) > I am looking for the best platform students can experiment and play > with (doing labs, projects and so on) > > Obviously, free and open source platforms are privileged since this is > an education purpose in a university that cannot afford paying money > for licences; or even managing a complex relation with an industrial > partner with some 'discounts' on licences. > > So if anyone has a suggestion I would be happy to know about it. At > the end of the process, I'll send a table summarising all the > suggestions so other people/teachers could benefit from it. > > Kind regards,Article: 122051
On 12 Jul., 01:41, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > I'd say a far bigger cost issue in the FPGA sector, is Tool quality, > and regression. I can understand their issues - the Silicon changes > at a rapid rate, in EDA software terms, so they always have to juggle > support for the hot-new-chips, with stability on older devices. > Things like the open-source cable drivers, look like a very good move. Open source cable drivers? Have I missed something? As of today, I am still using an unsupported, third party cable driver (that is open source, true) for programming my dev board from Linux. And it's completely user space so that I can run any kernel I want :-) None the less, having an officially supported driver from Xilinx would be better as I finally could complain about impact being unstable without fear that it will be attributed to my cable driver. Greetings, TorstenArticle: 122052
devices schrieb: > I chose the simple following example (perhaps > too simple or too specialized). Here's a flip > flop with an enable pin: > process (clk) > begin > if (clk'event and clk='1') then > > if (ce = '1') then > q <= d; > end if; > > end if; > end process; For most target libraries this will result in a D-Flipflop and a multiplexer controlled by ce. The multiplexer selected d or q as input to the D-FF. > - FIGURE B > > +---------------------+ > | _ | > | | \ +--------+ | > +--|0 | | | | > | |---|In Out|--+-> q > d--|1 | | | > | / | FF | > - +-|> | > | | +--------+ > | | > ce clk That is correct. > 1) If Figure B holds true, does it ALWAYS > go like this? Yes. Because you did not model a latch. A latch is a storage element. A D-latch has an enable signal and a data input. process(en,data) begin if (en='1') then latch<=data; end if; end process; The process you have written first could be changed into: process (clk) begin if (clk'event and clk='1') then q<=q_next; end if; end process; process(ce,d,q) begin if (ce = '1') then q_next<=d; else q_next<=q; end process; This describes the same behavior. As you can see, there is always a value assigned to q_next. This means: no storage needed. RalfArticle: 122053
On Tue, 17 Jul 2007 20:53:42 -0500, Jon Elson <elson@pico-systems.com> wrote: >x@x.com wrote: >> On Tue, 17 Jul 2007 12:25:05 -0500, Jon Elson <elson@pico-systems.com> >> wrote: >> <snipped> >> >>>I'm using Xilinx ise 4.2i, which is one of the last versions that supported the 5 V chips. >> >> <snipped> >> >>>Jon >> >> >> Jon; >> Last year I was using ISE 7.1 (SP4) for doing XC95108 and XC95216 >> (XC95288?) CPLD designs. BTW, ISE v6.3 was reasonably sized; the code >> bloat started with v7.1. ISE v8 and up are so huge they will only fit >> on DVDs. >Hmm, maybe I believed Xilinx's own material, which I think in >ise 5.2 or whatever said it would be the last release to support >the 5 V chips. Very interesting to hear that 7.1 handles them >also. What about 5 V Spartan? I do more of that then 9500 parts. > >Jon Jon; ISE 6.3i doesn't support 5v Spartan. It supports Spartan II and 3. I'm guessing, but maybe ISE 4.2i was the last version that supported 5v Spartan. -Dave PollumArticle: 122054
I am designing a board. I splited the ground plane into one analog plane and one digital plane. Can multiple Ferrite Beads be used to connect the both planes or only one FB should be used? In some schematics I see multiple FB are used to connect two planes. Does that violate the rule of single point connection? Acutally, I do not definitely know the true definition of "single point connection". In my opinion, "single point connection" or "multiple points connection" mainly refers to the number of connected locations by conductor not by ferrite beads. As we all know the impedence of a ferrite bead is great at high frequency, so its hard for multiple ferrite beads to form ground loops if the high frequency signals always have low impedence return paths. So I am not sure if the locations of multiple FBs will affect the noise situation and how much. Also, I am not sure how multiple FBs could work better than a single FB.Article: 122055
'commone', What is it that you are trying to do? I will assume since you posted here, that this is a FPGA question. For the FPGA, the only time a 'single point' fed plane, or planelet (small plane) is suggested is with the MGTs (multi-gigabit transceivers). For the MGTs, it is best to follow the MGT User's Guide, which shows how we do our lay-outs. Our lay-outs are used for all the characterizations of the MGTs for eeach and every standard (there are some 40+ of these), so these lay-outs have been refined with each new generation to the point where we seem to know what works, and what doesn't work. Unless you have extensive field and wave modeling software and fields and waves experience, I do not suggest doing something different. We generally assume that we are on a pcb where there are no 'other' circulating currents (there is no large current loop from something on one side of the device, to something on the other side of the device). All circulating currents we assume are there, are from our own IO pins (driving things like DDR SDRAMs, etc.). AustinArticle: 122056
Hi Bill, You are right about the components that are needed. On Actels webpage you can find Fusion tutorials and design examples where you can download the complete Libero project and then work you way through it. With the latest software, Libero 8.0, you can now use a graphical entry tool called SmartDesign for creating the top level. With this tool you don't need to write a single line of Verilog. I have created a complete Libero 8.0 project where a LED is turned on when the potentiometer exceeds 2 volt. Please send me an email and I will forward it to you. Regards RouzbehArticle: 122057
Greetings, all, I have read through many postings about bypass/decoupling capacitors for Xilinx FPGAs at comp.arch.fpga. It seems to me common "solution" (there are many, I'm sure) to use at most 10 or 20 caps for the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF capacitor, 0603 package, perhaps). I guess I just want a quick a dirty suggestion of what best to do (in terms of bypass caps) for this board. It's goal is to be a small board (current size is 2 by 5 inches or less) and only has the most basic components: two SRAM modules, an EEPROM module, power regulation via a TPS75003, an oscillator, and a few miscellaneous components (LEDs, etc.) with the rest of the free pins on the Spartan 3 (PQ208 package) becoming User I/O pins. The goal is to be as small as possible, and the board will be used by students (like myself) on projects as an alternative to a microprocessor solution (though the Spartan-3 will likely be configured with Microblaze). Also, right now I'm limiting myself to just four layers, with the one inner layer as a GROUND plane and the other as a VCCO plane. I doubt we'll use the board for really high- speed projects (in the gigahertz range...), but regardless I still have doubts as to what caps to use. I know there are many, many postings of similar topics as this one but I just need confirmation that I can "get away" with using as few bypass caps as possible. There are discussions relating to more advanced electrical concepts that I do not fully understand, and some real-world experience and recommendation concerning my board setup and chip selection would be greatly appreciated. Thanks. Lue Her University of St. Thomas (St. Paul, MN)Article: 122058
"commone" <dechenxu@yahoo.com.cn> wrote in message news:ouqdnVr3XZ86sAPbRVn_vgA@giganews.com... > > I am designing a board. I splited the ground plane into one analog plane > and one digital plane. > Why did you do that? It's almost certainly a very bad move indeed. You should have one ground plane. You can separate power planes in to mini-planes, that's fine. Connect power planes together with ferrites, that's fine also. However, the ground plane should stay as one plane. HTH., Syms.Article: 122059
<Lue.Her@gmail.com> wrote in message news:1184776967.209392.21280@j4g2000prf.googlegroups.com... > Greetings, all, > > I have read through many postings about bypass/decoupling capacitors > for Xilinx FPGAs at comp.arch.fpga. It seems to me common > "solution" (there are many, I'm sure) to use at most 10 or 20 caps for > the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF > capacitor, 0603 package, perhaps). I guess I just want a quick a dirty > suggestion of what best to do (in terms of bypass caps) for this > board. It's goal is to be a small board (current size is 2 by 5 inches > or less) and only has the most basic components: two SRAM modules, an > EEPROM module, power regulation via a TPS75003, an oscillator, and a > few miscellaneous components (LEDs, etc.) with the rest of the free > pins on the Spartan 3 (PQ208 package) becoming User I/O pins. > Hi Her, One cap for each power pin is gonna be about as good as you can do with the PQ208 package. In fact, the package is bad enough so that you can probably share bypass caps between two power pins and it wouldn't degrade much further. Do yourself a favour and use a FBGA instead, the SI performance is a great deal better. (You can rework them with a toaster oven, apparently!) HTH., Syms.Article: 122060
Ralf Hildebrandt wrote:
> devices schrieb:
>
>> I chose the simple following example (perhaps
>> too simple or too specialized). Here's a flip
>> flop with an enable pin:
>
>> process (clk)
>> begin
>> if (clk'event and clk='1') then
>>
>> if (ce = '1') then
>> q <= d;
>> end if;
>>
>> end if;
>> end process;
>
> For most target libraries this will result in a D-Flipflop and a
> multiplexer controlled by ce. The multiplexer selected d or q as input
> to the D-FF.
>
>
>> - FIGURE B
>>
>> +---------------------+
>> | _ |
>> | | \ +--------+ |
>> +--|0 | | | |
>> | |---|In Out|--+-> q
>> d--|1 | | |
>> | / | FF |
>> - +-|> |
>> | | +--------+
>> | |
>> ce clk
>
> That is correct.
>
>
>> 1) If Figure B holds true, does it ALWAYS
>> go like this?
>
> Yes. Because you did not model a latch.
>
> A latch is a storage element. A D-latch has an enable signal and a data
> input.
>
> process(en,data)
> begin
> if (en='1') then
> latch<=data;
> end if;
> end process;
>
>
> The process you have written first could be changed into:
>
> process (clk)
> begin
> if (clk'event and clk='1') then
> q<=q_next;
> end if;
> end process;
>
> process(ce,d,q)
> begin
> if (ce = '1') then
> q_next<=d;
> else q_next<=q;
> end process;
>
> This describes the same behavior. As you can see, there is always a
> value assigned to q_next. This means: no storage needed.
Yes, and thanks for fixing the font.
The combined structure could
also be viewed as a latch
with a synchronous delay
rather than a wire in the feedback loop.
This example is also the limit case
in the one vs two process debate.
-- Mike Treseler
Article: 122061Lue Her, A student platform or educational project should first of all be robust: you have no idea how clever they are, and they will do all kinds of wonderful things that you did not think possible (I know, as I helped design the UC Berkeley FPGA CS150 pcb). I have also seen the Standford lab pcb, San Jose State University pcb, Digilent pcb's, etc etc etc etc... Every thing you have mentioned in your post will lead to certain failure, and disappointment. If you want to cut corners, go with someone besides Xilinx: I do not want to have bad things said about Xilinx! Limiting layers, limiting bypass, are all things that you might do if you are Samsung/Sony/LG, and the application is fixed and unchanging (a LCD TV). These are all things you would not do for a general purpose platform, intended to perform a wide range of intended applications. Rather, follow our user's guides to the letter, and be successful. AustinArticle: 122062
On Jul 16, 11:19 am, "RCIngham" <robert.ing...@gmail.com> wrote: > That should work. Make sure you clear the counter on entry to the waiting > state. It is good practice to exit on "greater than or equal to" rather > than "equal to" despite the former using slightly more combinatorial logic > resources. Better yet, set the count to whatever period you need immediately prior to entering the waiting state, and wait for it to go to zero by checking the carry bit out of the decrementer (down counter). AndyArticle: 122063
On 17 Jul., 16:32, "Symon" <symon_bre...@hotmail.com> wrote: > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > news:1184671314.268484.185600@i38g2000prf.googlegroups.com...> Hi > > > I just burnt my fingers trying to lift off the Xilinx Spartan 3A > > Starterkit > > the all corner with power supplies is extremly hot - I wonder if that > > is > > normal or not. > > > Any ideas? Should I be worry? The power supply IC are so tiny that it > > is defenetly not possible > > to mount any heat sink on them :( > > > Antti > > Antti, > > Which regulator gets hot? IC12, IC3 or IC5? All these ICs have thermal > protection, so you shouldn't have to worry about this causing it to fail. > They'll turn off if they get too hot. > > However, that's no help to your burnt fingers, is it? I hope you learnt a > lesson here. I notice that a lot of your work seems to be on the software > side of the FPGA world. Complex and challenging it may be, but perhaps you > should leave the real engineering (such as handling the boards) to us > hardware guys whose fingers are so much more used to abuse than yours? ;-) > > Cheers, Syms. Dear Syms where do you get those weird ideas that I am on the soft side? It doesnt sound like that you wanted to insult me, but I still wonder... as I am doing almost onle the "hard" stuff (that is hardware) since 1979. if you dont belive my mileage, try find some guy who knows what is ERA6000 - I have one of them in junk box. ... actually my fingers are ok, and nose also, I would normally not touch a board that would burn me, as that would already smell or smoke. It must have been something weird as the same board even with same bitstream is now behaving much better, but at one time it looked like really too hot. And yes, I can say when some IC is really overcooking, it wasnt the case yet, but it was also more then you normally would touch without feeling pain. Antti (withasmallsmile..)Article: 122064
Antti, "Hot" behavior is usually associated with something that pulled too much current out of, or into, the substrate/vcc's. It is not SCR Latch-up, but instead the memory cells themselves are de-programmed (loose their brains) because the substrate perhaps went too far negative or positive, and as a consquence, the device looks like it needs far more current than usual. In effect, you have forced a random bitstream into the device. This requires more than 200 mA sink or source. Of course, sinking or sourcing 200 mA to supplies above any chip vcc, or below ground (0 volts), is not something we recommend (or allow). But, it can happen (power sequence with another chip, connecting a cable to another pcb, ...). I suggest that if you ever see this again, you attempt to do a readback/verify (if it isn't too hot!). AustinArticle: 122065
Pete Fraser wrote: > I want to program an FPGA to generate two-dimensional, > 10-bit video white noise. Any suggestions? I'm not sure if an > independent LFSR per bit would work. If so, would I want > different lengths per bit, or would I just initialize the different > bits at different times? > > Thanks. > > Pete > > You can use an LFSR but use one that skips ten steps forward in the sequence on each cycle so that the lower ten bits are not correlated from cycle to cycle. If you used, for example, a 17-bit LFSR, you would cycle through all 2^17-1 sequences, since 2^17-1 mod 10 = 1. If that makes sense. I forget what this kind of LFSR is called, but they are easy to make, because you can usually write a double loop in HDL and a good synthesizer like Synplify will take care of the rest. -KevinArticle: 122066
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:1184782547.151846.105610@i38g2000prf.googlegroups.com... > On 17 Jul., 16:32, "Symon" <symon_bre...@hotmail.com> wrote: >> "Antti" <Antti.Luk...@googlemail.com> wrote in message >> >> news:1184671314.268484.185600@i38g2000prf.googlegroups.com...> Hi >> >> >> However, that's no help to your burnt fingers, is it? I hope you learnt a >> lesson here. I notice that a lot of your work seems to be on the software >> side of the FPGA world. Complex and challenging it may be, but perhaps >> you >> should leave the real engineering (such as handling the boards) to us >> hardware guys whose fingers are so much more used to abuse than yours? >> ;-) >> >> Cheers, Syms. > > Dear Syms > > where do you get those weird ideas that I am on the soft side? > It doesnt sound like that you wanted to insult me, but I still > wonder... > as I am doing almost onle the "hard" stuff (that is hardware) since > 1979. > > if you dont belive my mileage, try find some guy who knows > what is ERA6000 - I have one of them in junk box. > Of course I'm joking. Although I'm a little worried that you seem to know an awful lot about EDK! :-) > > actually my fingers are ok, and nose also, I would normally not touch > a board that would burn me, as that would already smell or smoke. > > It must have been something weird as the same board even with > same bitstream is now behaving much better, but at one time > it looked like really too hot. And yes, I can say when some IC > is really overcooking, it wasnt the case yet, but it was also > more then you normally would touch without feeling pain. > > Antti (withasmallsmile..) > > OK, glad all is well. Like I said, the regulator chips have thermal protection, so they should survive getting hot! Cheers, Syms. (withabigsmile!)Article: 122067
e2point@yahoo.com schrieb: > i've synthesized or1200 and ... What about serializing the problem into smaller parts and computing the OR equation over fractions of 1200? RalfArticle: 122068
Lue.Her@gmail.com wrote: >Greetings, all, > >I have read through many postings about bypass/decoupling capacitors >for Xilinx FPGAs at comp.arch.fpga. It seems to me common >"solution" (there are many, I'm sure) to use at most 10 or 20 caps for >the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF >capacitor, 0603 package, perhaps). I guess I just want a quick a dirty Bypassing each power pin with a 0402 10nf and a 0402 100nf capacitor is a good start. Connect the capacitor directly to the power supply pin and use 2 via's to ground for each capacitor. Place a 10uf MLCC capacitor for each supply close to the fpga for bulk decoupling. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 122069
Antti wrote: > > > if you dont belive my mileage, try find some guy who knows > what is ERA6000 - I have one of them in junk box. Bye hell you are going way back. That was a GPS equivalent of an FPGA. My boss worked on that. That was the good old days. AndyArticle: 122070
Torsten Landschoff wrote: > On 12 Jul., 01:41, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > >> I'd say a far bigger cost issue in the FPGA sector, is Tool quality, >>and regression. I can understand their issues - the Silicon changes >>at a rapid rate, in EDA software terms, so they always have to juggle >>support for the hot-new-chips, with stability on older devices. >> Things like the open-source cable drivers, look like a very good move. > > > Open source cable drivers? Have I missed something? Yes :) This comment from Steve Lass at Xilinx, in another thread (7 July): > We listened. The open source cable drivers are in alpha in 9.2.01i and > are being made available to select customers for evaluation. > > SteveArticle: 122071
"Nico Coesel" <nico@puntnl.niks> wrote in message news:469e6836.831123642@news.planet.nl... > Lue.Her@gmail.com wrote: > >>Greetings, all, >> >>I have read through many postings about bypass/decoupling capacitors >>for Xilinx FPGAs at comp.arch.fpga. It seems to me common >>"solution" (there are many, I'm sure) to use at most 10 or 20 caps for >>the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF >>capacitor, 0603 package, perhaps). I guess I just want a quick a dirty > > Bypassing each power pin with a 0402 10nf and a 0402 100nf capacitor > is a good start. Connect the capacitor directly to the power supply > pin and use 2 via's to ground for each capacitor. Place a 10uf MLCC > capacitor for each supply close to the fpga for bulk decoupling. > Hi Nico, I'd be interested to hear your reasoning as to why you would use two capacitors for each pin, especially bearing in mind this is a PQ208 package. Do you own Murata shares by any chance? ;-) Also, why would you use two different values? Thanks, Syms.Article: 122072
On 13 Juli, 04:07, we...@drexel.edu wrote: > Hi all, > > I recently purchased theActelFusion Starter Kit. I'm new to both > Libero IDE and Verilog and was hoping for some guidance. All I'm > trying to do is turn LED D1 on when the voltage from the potentiometer > exceeds 2 volts. This is as simple as you can get. So tell me if I'm > wrong, but I think my system needs to include the following: > > * Analog System Builder > * Flash Memory System > * RC Oscillator > * Static PLL > > If this is correct, I think my problem is most likely in the top level > verilog description. > > Also, say I wanted to look at an even simpler case of just turning on > LED D1. Then I could eliminate the ASB and the Flash Memory, right? > > Thanks in advance, > -Bill Green Hi Bill, You are right about the components that are needed. On Actels webpage you can find Fusion tutorials and design examples where you can download the complete Libero project and then work you way through. With the latest software, Libero 8.0, you can now use a graphical entry tool called SmartDesign for creating the top level. With this tool you don't need to write a single line of Verilog. I have created a complete Libero 8.0 project for you where a LED is turned on when the potentiometer exceeds 2 volt. Please send me an email and I will forward it to you. Regards RouzbehArticle: 122073
Damc wrote: Hello, I run into a problem/bug where I currently don't see a solution, probably somebody can give me some hints. I encoded data frames with 8B/10B, filled the gaps between the data with K28.5 characters and then transmitted the data stream via a serial line. On the receiver side I did the same backwards and run their into a problem: The serial data stream of the following bytes (0x6E, 0x74, 0x77, 0x65 or D14.3, D20.3, D23.3, D5.3) contains a bit sequence that is identical to the K28.5 character and therefore my receiver recognises also this K char instead of the intended data byte. [snip] No valid D character sequence should produce the K28.5 sequence! Check your generation logic and make sure you are following the rules for running disparity. Gabor (posting via Xilinx website - Google groups seems broken today)Article: 122074
"Ralf Hildebrandt" <Ralf-Hildebrandt@gmx.de> wrote in message news:5g77h2F3ei54tU1@mid.individual.net... > e2point@yahoo.com schrieb: >> i've synthesized or1200 and ... > > What about serializing the problem into smaller parts and computing the > OR equation over fractions of 1200? > > Ralf Were you trying to be funny? The OR1200 is an open-source risc core. It's also been a while since the original post.
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