Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Jul 12, 12:03 am, Yao Sics <yao.s...@gmail.com> wrote: > Hi Xilinx Killers, > > It is really annoying to rename and group all the signals everytime > when design is modified and new bit file is used to configure the > fpga. Anybody knows how to avoid renaming and regrouping signals in > the analyzer when new bit file is loaded to FPGA? When adding new signals to a Chipscope project, I try to add them at the end to avoid screwing up the project. That way you can simply import your new .cdc file into your Chipscope Analyzer project and all the previous signals will stay intact (and the new signals will appear). Avoid inserting new signals by moving other signal positions around, as this will screw up the project. In order to help you setting up the Chipscope Analyzer project, take a look at csptool: http://code.google.com/p/csptool/ It's a little Perl script that regroups buses for you. Might be overkill if you have a few buses, but if you have tens, it can be very handy. > And one more quick question, how to investigate state_reg of a FSM by > usingchipscope? Because the original name of the interesting > state_reg is modified after synthesis, I dont't know which signal I > should investigate now. You can look at the synthesis report to see how XST encoded the states. Then I suggest that you create a .tok file to display the name of the state in the waveform window. Look at \ChipScope_Pro_9_1i\bin\nt \token\token_sample.tok for an example. PatrickArticle: 121776
On Jul 12, 9:16 am, "Maurice Branson" <trauben...@arcor.de> wrote: > designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated > RocketIOs (Gigabit SerDes IOs) I am now facing the problem of how to get the > signals off the board in a most space-saving and elegant way? > > All 24 differential signals will be connected to some DACs Mass-produced SCSI internal and external cables and terminators are easy to find. The 68-pin cables go to 320 MHz nowadays, and connect 27 differential pairs plus some status wires and power wires for active terminators (which are commonly crimped onto the internal cable end- no need to populate your board with the terminators). If you can drive 110 ohm wiring, and if the low-voltage differential signal levels are the same as SCSI, your choice may be easy.Article: 121777
Jim, Hosting something, in effect, anonymously, is OK. The problem is what if someone finds out you are the host, and then makes life "difficult?" "There be trolls out there ..." Hosting 'open cores' would be something that would need to have benefit. To Xilinx. Imagine trying to manage an open cores site... No, Jim, I don't think we will host any open cores. We might not even continue to host what we do now, in the future (depends on the trolls). AustinArticle: 121778
Austin, I am using Xilinx ML523 board. This board uses V5 LXT device. As per the schematics AVTTTX and AVTTRX are connected to 1.2 Volts. Does this mean that the common mode voltage is 1.2V? If so why am I seeing common mode voltage of about 350mV? Thanks. EddieArticle: 121779
John, I am using Xilinx ML523 board to test the GTP outputs. Shoud it not be claibrated already? Why is it drastically different? EddieArticle: 121780
Hi all, I recently purchased the Actel Fusion Starter Kit. I'm new to both Libero IDE and Verilog and was hoping for some guidance. All I'm trying to do is turn LED D1 on when the voltage from the potentiometer exceeds 2 volts. This is as simple as you can get. So tell me if I'm wrong, but I think my system needs to include the following: * Analog System Builder * Flash Memory System * RC Oscillator * Static PLL If this is correct, I think my problem is most likely in the top level verilog description. Also, say I wanted to look at an even simpler case of just turning on LED D1. Then I could eliminate the ASB and the Flash Memory, right? Thanks in advance, -Bill GreenArticle: 121781
PFC wrote: > I'd be willing to relearn the Altera tools if someone can confirm > that you can get the full package for a decent price (ie the same or > cheaper than EDK) ; full package meaning full license to use Nios (not > time-limited or whatever), JTAG cpu debugging plus having a good core > library. Cuz I saw nice board modules with Altera chips on them... I did about half a project using Quartus/SOPC Builder 6. Quartus was fine. SOPC Builder was one of the worst bug-ridden programs I've ever seen. Moving to EDK was a major breath of fresh air. I haven't tried version 7, so for all I know everything got fixed. Nice part about the Altera is you get more useful stuff for your money. Xilinx seems to nickel-and-dime you with their IP offerings (a decent UART, I2C, etc.). Very few of their example designs can even be implemented without spending many $K for IP cores (I don't count the evaluation time-bombs as "implementing"). Altera seems to include a much richer set of peripherals in the base package. kenArticle: 121782
On Jul 12, 11:28 am, Mike Treseler <mike_trese...@comcast.net> wrote: > I feel your pain, but the > fpga manufacturers would have caused > more pain by going out business. There was absolutely no risk for Xilinx going out of business if it has spent another man year or two software engineering labor to include XC4K/Spartan support into XST. A few hundred thousand dollar cost to provide the expected support for probably $100M of product they forced early obsolecence of by that ommission., What they did do was hurt a lot of small businesses like mine and my clients at the time, and thousands of students. That created a burst of new product sales, as people scrambled to reengineer with Spartan 2's and Virtex parts. One of my former clients was so angry about almost being put out of business by it, they will never buy Xilinx again. And today we have Austin crowing about others circling the drain, and how they commit to customer support, and always have. Bull Pucky .... outright .... At any point since, they could have included XC4K/Spartan synthesis in XST while highly profitable, as Austin continuously touts, the highest margins in the industry. But no ... they screwed a lot of people, and didn't even look back to make a buck.Article: 121783
Hi Craig,
it's so simple:
sch2verilog
is the name of the program. and this is how to use it :
Release 9.1.01i - sch2verilog J.31
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Usage: sch2verilog [-intstyle <intstyle>] [-top] [-tf] [-tfonly] [-tfext
<ext>]
[-ti] [-tionly] [-tiext <ext>] [-nodrc] [-nets] [-NETS] [-inst] [-INST]
[-MODEL]
[-model] [-iterated] [-family <family>] [-synthesis <tool>] [-w]
<infile[.sch]>
[<outfile>]
-intstyle <intstyle> Indicate contextual information when
invoking Xilinx applications within a flow or project environment.
<intstyle> can be ise, xflow or silent
-top Write out the top-level schematic only
-tf Generate test fixture file
-tfonly Generate test fixture file only
-tfext <ext> Set test fixture file extension (Default: vf)
-ti Generate instantiation template file
-tionly Generate instantiation template file only
-tiext <ext> Set instantiation template file extension
(Default: vi)
-nodrc Disable DRC check
-NETS Force net and pin names to uppercase
-nets Force net and pin names to lowercase
-INST Force instance names to uppercase
-inst Force instance names to lowercase
-MODEL Force VeriModel names to uppercase
-model Force VeriModel names to lowercase
-iterated Don't Use underscores when expanding iterated
names
-family <family> Specify device family (Default: virtex)
-synthesis <tool> Specify synthesis tool: XST, EXEMPLAR,
PRECISION, SYNPLICITY (Default: XST)
-w Overwrite existing file without warning
<infile> Input file name (Default extension: .sch)
<outfile> Output file name (Default: <infile>.v)
So all you need for your everyday work is:
sch2verilog -family virtex_or_whatever_U_use circuit.sch circuit.vf
For your modelsim question:
Yes: if you split your script in two parts:
a shell script that converts the schematics (and does the compilation of
your sources if you like) and the modelsim do script that controls your
simulation. Remember: vlib vmap and vlog (vcom for vhdl users) are
independent programs that can run without a modelsim gui. depending on
your scripting skills you can even prevent the simulator to start before
the sources are all compiled successfully.
e.g.:
#! /bin/sh
# if you are a unix user
sch2verilog -family <your_family> circuit_1.sch circuit_1.vf
#...many more
sch2verilog -family <your_family> circuit_n.sch circuit_n.vf
vlib yourlib
vmap yourlib yourlib_path
vlog [options] circuit_1.vf
#...many more
vlog [options] circuit_n.vf
vsim -do sim_script.do
# end of sh script
#sim_script
vlog [options] testbench.v
vsim [options] testbench
view wave -undock
do wave_circuit.do
# or
add wave *
run -all
# end of sim_script
>>> divide et impera <<<
Have a nice simulation
Eilert
craigtmoore@googlemail.com schrieb:
> Is there a way to convert a schematic file (.sch) into a functional
> verilog module (.v/.vf) from the command line? I want to do this so I
> can compile the resulting verilog file with modelsim for simulation. I
> know how to do this from the ISE GUI, but it would be much easier if I
> could do it from the command line.
>
> Please bear in mind that I am using Xilinx ISE 9.1i or ModelSim XE III/
> Starter 6.2c when posing your answers.
>
> I appreciate any help you can provide.
>
> Kind Regards,
> Craig.
>
> P.S. Out of curiosity, is there a way to simulate a project with mixed
> verilog and schematic files in ModelSim from the command line?
>
Article: 121784Eddie H wrote: > John, > > I am using Xilinx ML523 board to test the GTP outputs. Shoud it not be claibrated already? Why is it drastically different? > > Eddie I don't know CML very well, but I know it needs the proper terminations for the right swing and common-mode range. Glancing through UG196, it seems the only place for the termination is on the transmitter. Are your signals open into 0.5 pF FET probes on an oscilloscope? Or are you driving them into 50-ohm probes, terminated to ground? Often the problem comes down to the method of observation, not the signal itself. - John_HArticle: 121785
Tanks for your answers so far! Oay, to make it more precise: I'm looking for an interconnect system (multi-channel plug + receptacle) for 24 differential pairs at signaling rates of 3 - 6 Gbps per channel.Article: 121786
Okay, let's be more precise: The clock frequencies I'd like to distribute are in the range of 180 - 300 MHz, i.e. it is a challenging task. The signal busses between the FPGAs should carry signals in that range, too. Data is exchanged synchronously, so there is not much room for synchronization I think...!? GeroArticle: 121787
On 9 Jul., 13:15, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > "Hofjue" <hof...@googlemail.com> wrote in message > > news:1183468984.304426.183320@o61g2000hsh.googlegroups.com... > > > > > On 3 Jul., 15:11, Zara <me_z...@dea.spamcon.org> wrote: > >> On Tue, 03 Jul 2007 05:07:28 -0700, hofmann.juer...@pc-future.de > >> wrote: > > >> >Hi all, > > >> >I'm developing a multicore system with up to four Microblaze cores. > >> >Now I'm searching for a solution to inform the cores about e.g. > >> >messages with a software interrupt. That means, one core writes a > >> >message in the shared memory and after that it informs the other cores > >> >to read the message. > >> >My first idea was to use a GPIO element with interrupts switched on. I > >> >tried to write to the element when the message was posted . But there > >> >is the problem, that the interrupt is only activated when the data > >> >will be changed from outside the microblaze core. > >> >So my new idea is to use two GPIO elements and link them together. But > >> >it doesn't run and I think, that the problem is the linking of the > >> >ports. > >> >Has anybody an idea, which ports I have to link (GPIO_d_out or GPIO_IO > >> >with GPIO_in or something else) or an idea how to implement software > >> >interrupts in such a combination? > > >> >I've got a Xilinx ML410 evaluation board. > > >> >Thank you for your help. > > >> What abiout using FSLs to communicate between processors? They have a > >> FIFO with somne capacity, they generate interrupts... it is the > >> firmware implem,entation of a queue. > > >> Zara > > > The problem is, that I have to link every core with each other. A > > Microblaze core only have eight FSL ports so I could only combine > > three cores. > > But I have to check the interrupt idea, perhaps I can use the > > interrupt signal in my global interrupt controller and all cores react > > to the interrupt. > > Hi, > > Each FSL port has one input connection (slave) and one output connection > (master). > So with 8 FSL ports, you can connect from one MicroBlaze to eight other > MicroBlazes. > > This should be enough for your system. > > G=F6ran Bilski Yes, that's right. But it doesn't work when MicroBlaze Nr. 3 should communication with MicroBlaze Nr. 2 - or? In my opinion the only solution in this configuration is to use a token ring communication. But then it must be a cyclic communication and not an interrupt driven.Article: 121788
In news:f72otn$cm32@cnn.xilinx.com timestamped Wed, 11 Jul 2007 07:19:34 -0700, austin <austin@xilinx.com> posted: |------------------------------------------------------------------------| |"[..] | | | |Additionally, a massive amount of work goes into testing and | |re-optimizing every core when the technology node changes. Who will pay| |for that? Who will warrant or guarantee operation? Who supplies the | |test bench vectors to verify proper operation? | | | |Austin" | |------------------------------------------------------------------------| In news:f74vto$s1c$1@newsserver.cilea.it Colin Paul Gloster posted with a malformed From header (sorry, that was my fault): |---------------------------------------| |Testing does not guarantee correctness.| |---------------------------------------| In news:f75gu9$fkp2@cnn.xilinx.com timestamped Thu, 12 Jul 2007 08:21:45 -0700, austin <austin@xilinx.com> posted: |-----------------| |"But it helps....| | | |Austin" | |-----------------| Agreed. C. P. G.Article: 121789
>Tanks for your answers so far! > >Oay, to make it more precise: I'm looking for an interconnect system >(multi-channel plug + receptacle) for 24 differential pairs at signaling >rates of 3 - 6 Gbps per channel. > That is an astonishingly high data rate (~70 Gbps to ~150 Gbps)! I won't ask what it's for, as I suspect you wouldn't be able to tell us. ;-) How far is the system architecture defined? Instead of a 'Digital' board + 'DAC' board, could you do it with a series of 'Digital + DAC' slices, even if that meant replicating some of the functions in each slice? On a previous project, the high potential interconnection data rates rendered the 'obvious' approach non-viable, and so a more communication-friendly architecture had to be developed.Article: 121790
On Jul 12, 6:16 pm, "Maurice Branson" <trauben...@arcor.de> wrote: > Are there > any other interface systems for the above described purpose or ways to build > a highly-parallel highspeed connection between two boards? Look at the data sheets for PCIe card edge connectors. Some manufacturers specify -1.5dB bandwidth of 7GHz and more for the differential pairs. You can use both receiver and transmitter pairs for transmitting (just make sure you do not plug the board into a PC). This provides you with 32 differential pairs for a 16x PCIe connector. Kolja SulimmaArticle: 121791
Hello, I require a counter which counts up on positive clock; can be reset to zero upon a reset signal; will stop counting when reached max or rollover; will restart counting only after a total reset, which is not the same as the counter reset. (2 resets) Waiting with anticipation. Thanks.Article: 121792
"Patrick Dubois" <prdubois@gmail.com> wrote in message news:1184290183.837237.48920@n2g2000hse.googlegroups.com... > On Jul 12, 12:03 am, Yao Sics <yao.s...@gmail.com> wrote: >> Hi Xilinx Killers, >> >> It is really annoying to rename and group all the signals everytime >> when design is modified and new bit file is used to configure the >> fpga. Anybody knows how to avoid renaming and regrouping signals in >> the analyzer when new bit file is loaded to FPGA? > > When adding new signals to a Chipscope project, I try to add them at > the end to avoid screwing up the project. That way you can simply > import your new .cdc file into your Chipscope Analyzer project and all > the previous signals will stay intact (and the new signals will > appear). Avoid inserting new signals by moving other signal positions > around, as this will screw up the project. > Hi Patrick, So I'm still using 8.2, and this isn't the behaviour I see. An import overwrites any previous edits. Is this a new feature for 9.1? > In order to help you setting up the Chipscope Analyzer project, take a > look at csptool: > http://code.google.com/p/csptool/ > I downloaded it, sounds interesting, many thanks. All the best, Syms.Article: 121793
On 13 Jul, 11:51, <miche> wrote: > Hello, > I require a counter which counts up on positive clock; > can be reset to zero upon a reset signal; > will stop counting when reached max or rollover; > will restart counting only after a total reset, which is > not the same as the counter reset. (2 resets) > Waiting with anticipation. > Thanks. Will this do: http://tools.arantius.com/stopwatch Cheers, JonArticle: 121794
"Jon Beniston" <jon@beniston.com> wrote in message news:1184325590.954425.86330@n2g2000hse.googlegroups.com... > On 13 Jul, 11:51, <miche> wrote: >> Hello, >> I require a counter which counts up on positive clock; >> can be reset to zero upon a reset signal; >> will stop counting when reached max or rollover; >> will restart counting only after a total reset, which is >> not the same as the counter reset. (2 resets) >> Waiting with anticipation. >> Thanks. > > Will this do: > > http://tools.arantius.com/stopwatch > > Cheers, > Jon > Hi Jon, :-) Actually that's quite a useful widget. Ta for the link! Cheers, Syms.Article: 121795
miche wrote: > Hello, > I require a counter which counts up on positive clock; > can be reset to zero upon a reset signal; > will stop counting when reached max or rollover; > will restart counting only after a total reset, which is > not the same as the counter reset. (2 resets) > Waiting with anticipation. > Thanks. > Would you like fries with that also :-) More seriously, there are a few things you could do to demonstrate that you're not just a lazy person looking for somebody else to do your homework for you: - Are you using VHDL or Verilog or some schematic-entry tool? - Have you made any attempt yourself to implement this? - Can we see your implementation? - Do you have any simulation stimuli (testbench) to test it?Article: 121796
> - Are you using VHDL or Verilog or some schematic-entry tool? Yes, verilo > - Have you made any attempt yourself to implement this? Yes, see my last post 2 day ago. > - Can we see your implementation? Yes, see my last post 2 day ago. > - Do you have any simulation stimuli (testbench) to test it? Yes, see my last post 2 day ago.Article: 121797
> Hi Jon, > :-) > Actually that's quite a useful widget. Ta for the link! Miserable gits. > Cheers, Syms. > >Article: 121798
On 13 Jul, 13:04, <miche> wrote: > > - Are you using VHDL or Verilog or some schematic-entry tool? > > Yes, verilo > > > - Have you made any attempt yourself to implement this? > > Yes, see my last post 2 day ago. > > > - Can we see your implementation? > > Yes, see my last post 2 day ago. > > > - Do you have any simulation stimuli (testbench) to test it? > > Yes, see my last post 2 day ago. I wait in anticipation for a link to your previous post 'cos I'm too lazy to search for it.Article: 121799
In alt.engineering.electrical Geronimo Stempovski <geronimo.stempovski@arcor.de> wrote: | a) connection of the clock in a star-like topology, feeding each of the | three FPGAs with the same clock signal (which has to be possibly duplicated | by a clock buffer to generate three out of one clock reference signal, | thereby introducing additional jitter) Do you really need it buffered for isolation? If you have enough clock power, could you not feed all three from the one clock with impedance matched lines? What is the frequency, anyway? -- |---------------------------------------/----------------------------------| | Phil Howard KA9WGN (ka9wgn.ham.org) / Do not send to the address below | | first name lower case at ipal.net / spamtrap-2007-07-13-0740@ipal.net | |------------------------------------/-------------------------------------|
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z