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Is it possible to synchronise the 1MHz clock to the 100MHz domain and keep that clock for all the operations like ADC. (This may not be possible according to the spec i have but i am asking a general doubt).Article: 121501
On Jul 5, 8:30 pm, austin <aus...@xilinx.com> wrote: > Alan, > > I did bring up the 2.5 volt issue, but I guess you were chasing some > other issue. Virtex 4, Spartan 3 (basically, everything since the first > 90nm products) did change from 3.3 volts to 2.5 volts (3.3V > compatible...) on the JTAG. It is the "compatible" that is not so easy: > older programming cables, aren't. > > Sorry you got bit by this. Glad to hear you did not have a toasted chip. > > Austin Austin, the Xilinx "Cable problem" is pretty much serious one. It bites again and again. there are boards that can be programmer with USB cable or with Cable IV both not with both. there are boards that can be programmed using Impact 8.2 but not with Impact 9.1 the list is endless. so in case of Xilinx JTAG trouble: check ALL your cables you can get hands on try different version of software. try impact try download with chipscope, etc.. there have been cases where chipscope can configure but impact cant, etc... AnttiArticle: 121502
Hi, I started to learn ISE and EDK 9.1i, but I spent much much time to get things running because they did not work as described in the manuals. Now I write this posting in the hope that someone from Xilinx will read it and consider it for further software development. I tracked down the problems to two sloppinesses which never should be done in software development: a) The GUI does not evaluate the return code of programs it calls. This leads to situations where the GUI shows 100% complete, 0 errors but nothing has been done at all, which makes it very hard to find the real cause for subsequent errors. b) Some command line programs like "simgen" return 0 even if errors occurred. Thus makes it impossible for "make" to stop on errors, and again, makes it very very hard to find the cause for subsequent errors. Thus dear Xilinx programmers please note: - NEVER ignore the return code of a program. - Always return 0 on success and a value between 1 and 255 if an error has occured. If you follow this hint you will save us (your customers) and your support department much time, money and nerves. Is there a Xilinx manager out there who have ever considered how much money Xilinx must have wasted by not following this simple ground rules in software programming? Best regards, Franz HollererArticle: 121503
On Jul 6, 7:44 am, Franz Hollerer <franz.holle...@ims.co.at> wrote: > Hi, > > I started to learn ISE and EDK 9.1i, but I spent much much time to get > things running because they did not work as described in the manuals. > > Now I write this posting in the hope that someone from Xilinx will read > it and consider it for further software development. > > I tracked down the problems to two sloppinesses which never should be > done in software development: > > a) The GUI does not evaluate the return code of programs it calls. > This leads to situations where the GUI shows 100% complete, 0 errors but > nothing has been done at all, which makes it very hard to find the real > cause for subsequent errors. > > b) Some command line programs like "simgen" return 0 even if errors > occurred. Thus makes it impossible for "make" to stop on errors, and > again, makes it very very hard to find the cause for subsequent errors. > > Thus dear Xilinx programmers please note: > - NEVER ignore the return code of a program. > - Always return 0 on success and a value between 1 and 255 if an > error has occured. > > If you follow this hint you will save us (your customers) and your > support department much time, money and nerves. > > Is there a Xilinx manager out there who have ever considered how much > money Xilinx must have wasted by not following this simple ground rules > in software programming? > > Best regards, > > Franz Hollerer the amount of time Users of Xilin silicon devices spend "fighting" with Xilinx software is enorm. So far it really looks that Xilinx isnt listening. Things are not improving. Only new bug comes, and old ones re-apperar... AntiArticle: 121504
If you want to add Coregn cores there are a few choices: - .edn netlist (fine for memories), Remark: only contains top level for other cores than memories. - .ngc. Please use ngc2edif.exe from ISE installation directory. Generates .ndf netlist which actually is EDIF. Add file to project. You mentioned your design could not be synthesized successfully. Please be more precise what the problem is.Article: 121505
On Thu, 05 Jul 2007 22:58:37 -0700,
vssumesh <vssumesh_asic@yahoo.com> wrote:
>Is it possible to synchronise the 1MHz clock to the 100MHz domain and
>keep that clock for all the operations like ADC. (This may not be
>possible according to the spec i have but i am asking a general
>doubt).
Easy: just oversample and edge-detect it...
signal enable_1MHz: std_logic;
...
process (clk_100MHz)
variable resync1, resync2, delay: std_logic;
begin
if rising_edge(clk_100MHz) then
delay := resync2;
resync2 := resync1;
resync1 := clk_1MHz;
if (resync2 and not delay) = '1' then
enable_1MHz <= '1';
else
enable_1MHz <= '0';
end if;
end if;
end process;
This generates a pulse on enable_1MHz that is synchronous
with clk_100MHz and is exactly one 100MHz clock cycle wide.
So you can then use it to enable any activity in the
100MHz clock domain that must happen once per 1MHz clock.
Of course, it's important to note that this enable will take
effect on the third or fourth 100MHz clock after each rising
edge of the 1MHz clock. You need to check your system spec
to determine whether this is acceptable. Usually, though,
it works well. It's a fairly safe bet that everything in
the 1MHz clock domain is nicely stable by 30ns after a
rising edge on the 1MHz clock. If you need more settling
time in the 1MHz domain, simply add more delay stages to the
process.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 121506"austin" <austin@xilinx.com> wrote in message news:f6bcm0$h0h3@cnn.xilinx.com... > Alex, > > Have you looked into: > > http://www.tapr.org/kits_dsp10.html > > Generally, using a FPGA for SDR is only required when the radio is doing > something other than FM, AM, SSB, or low data rate digital mod/demod. > > http://hpsdr.org/ > > Details a 'solution' using the Cyclone FPGA. > > (This was before I gave my one day FPGA class to the TAPR folks). > > Austin Thanks but we want to just stick with xilinx as we get the tools as part of the uni program. Have looked at the dsp 10 kits. After something a lot more flexible. The http://hpsdr.org/ sasquatch board sounds like what we are after but we need something that is stand alone not with a backplane. Just working towards setting up a student lab for sdr using fpga's and dsps(TI). What they (professor and others) want is boards dsp and fpga on which students can program certain blocks like modulation, demodulation, encoders/decoders and the rest of the design is premade blocks. So dsp/fpga does the audio encoding and modulation then goes to an upconverter and output/power amp. Same for the decode. Want the the students(telecomms) to learn sdr using c , vhdl and matlab Thank you AlexArticle: 121507
Alan, I am not sure whether my own experiences have anything to do with your case but here they are: I had built me my own parallel-3 compatible jtag cable. Instead of 74HC125 (original) I used 74AHC125 buffers in the cable which should even perform better in the necessary level translation. With this cable I had programmed a lot of different Xilinx devices without any problem. Then came the day when I tried to program an XC3S400 with this cable with pretty much the same effect as you have noticed: Even reading the device idea failed. The person who had developed the board with the XC3S400 on it (http://www.siphec.com/) had also an matching download cable to sell, developed by himself. I ordered one and see: This one worked. By looking at the pcb I could not find any big differences to my own circuit, thats why I contacted the developer to ask for his advice. When I told him about my experiences he explained that he had had pretty the same problem and that he has found an solution for it. However, as he said, while he has an solution for it , he has NOT an deeper understanding WHY it is an solution. The solution is to terminate the TCK line behind the 100 Ohm resistor with abt 560 Ohms to ground and it is important that this termination happens on the driving side of the cable and not on the fpga side. That's all. I included the termination and my cable worked like charme with the XC3S400. Weeks later he called me on the phone to tell me that he had found a second way to make it run: Putting 470 Ohm instead of 100 Ohm into all jtag lines had also given him a stable result. So while I would not warrant for 100% it seems to be more a problem of clock conditioning than level translation. Clock conditioning in this case does not necessarily mean that the clock generated by the cable is by some means *bad* and needs to be conditioned. It may also be possible (which I believe in) that the Spartan device can source/sink high amounts of current on its TDO output and/or generate high slew rates on this pin. Both of that could be the source of crosstalk happening on the cable which (when big enough) may be the cause for additional false edges appearing on the TCK line. Please note that this is an assumption and that it is not easy to verify. Even the few picofarads capacity of an scope's probe applied to an jtag pin may make an big difference alone when it comes to really fast signals. Best regards Ulrich Bangert "Alan Nishioka" <alan@nishioka.com> schrieb im Newsbeitrag news:1183660087.898569.64290@d30g2000prg.googlegroups.com... > I have figured it out. (well part of it) > I finally tried it with a Platform USB cable belonging to my Avnet > FAE, and it WORKED! > > I had been using a Parallel Cable III (I guess I left that out). I > was certain that this would have no effect. > > I still can't explain why JTAG partially works, but won't read device > id. > I would love for someone to confirm this or explain it. > > My guess would be some sort of voltage incompatibility (But I was > *sure* changing the cable would have no effect, so how good are my > guesses?) > > Thank you to everyone for your suggestions. > Alan Nishioka > > > On Jul 3, 11:06 am, Alan Nishioka <a...@nishioka.com> wrote: > > I am trying to get an xc3s250e-4tq144c to configure using JTAG. > > > > 1. impact reads 0x00000000 as idcode > > This causes impact to error out during identify with a strange > > error about missing bsdl's > > 2. JTAG works using impact debug mode. I can put it in bypass and > > also see the length of the instruction register. I can see data > > shifting in and out so I know JTAG works. > > 3. Part markings are: > > XC3250E > > TQ144AGQ0601 > > D1392255A0 > > 4C > > so it is a step 0 part. > > 4. I have tried impact 8.1.3 and 9.1 > > 5. I get identical results with two pc boards. > > 6. Same software / computer / cable setup works fine with a virtex2p > > design. > > 7. All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio) > > 8. spartan-3e is the only part in the JTAG chain. > > > > I have tried removing all the parts except the spartan and power to > > make sure nothing else was interfering with it. > > > > I have not made any progress with my Avnet FAE and Xilinx webcase so I > > thought to try here. > > > > I have run out of things to try. Does this look familiar to anyone? > > Any ideas to try? > > > > Alan Nishioka > > a...@nishioka.com > >Article: 121508
I also arrived in the same solution, though i reduced the number of sync flops to two like "if (resync1 and not resync2)". My thought was now we have some fast FFs and this enable signal is going to be used only at the next +ve edge of 100MHz, so by that time we get a valid signal in the "enable_1MHz". Will this assumption work?Article: 121509
> the amount of time Users of Xilin silicon devices spend "fighting" > with Xilinx software is enorm. > So far it really looks that Xilinx isnt listening. Things are not > improving. > Only new bug comes, and old ones re-apperar... Yeah, this sums up well my experience with ISE and especially EDK ! On my first FPGA project which lasted about a month I spent : - 3 weeks learning ISE+EDK then fighting it - 2 days learning Verilog - 1 week implementing the stuff Is Altera better ? EDK's nice part is that it isn't really expensive, includes a full Microblaze licence, and you can use a $20 "compatible" cable, plus it includes a huge number of IP cores for the same price. And the Spartan chips are really nice. I'd be willing to relearn the Altera tools if someone can confirm that you can get the full package for a decent price (ie the same or cheaper than EDK) ; full package meaning full license to use Nios (not time-limited or whatever), JTAG cpu debugging plus having a good core library. Cuz I saw nice board modules with Altera chips on them...Article: 121510
On Fri, 06 Jul 2007 01:58:21 -0700, vssumesh <vssumesh_asic@yahoo.com> wrote: >I also arrived in the same solution, though i reduced the number of >sync flops to two like "if (resync1 and not resync2)". My thought was >now we have some fast FFs and this enable signal is going to be used >only at the next +ve edge of 100MHz, so by that time we get a valid >signal in the "enable_1MHz". Will this assumption work? The extra FF provides protection against metastable events on "resync1". If your fast clock were, let's say, 20MHz then I definitely would not bother with the extra FF. The question is: how likely is it for a setup/hold violation on "resync1" to induce enough metastability to push its settling time out to about 9ns? A third FF is much cheaper than the time it takes me to look up, and calculate, the math :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 121511
I'm developing an embedded web server into a XupV2pro board with a VirtexII-pro fpga. While all my code was in the bram memory all works fine, the problem was that the application grew and grew until a moment when the EDK says that my bram was full. Now I need relocate some parts of my application (code, data or both) to fit in external DDR RAM, the problem is that I try to do this visually with the EDK's option 'generate linker script', putting section .text and .data outside bram into DDR. I recompile the project and all is right but when y download it to the fpga it doesn't work. I go back, remove some files of my project, generate a new linker script where all sections were in bram, compile, download and it run fine. I would like you help me to understand the 'linker script' and how to generate one for my purpose. Thanks in advance.Article: 121512
On Jul 5, 11:26 pm, austin <aus...@xilinx.com> wrote: > water9...@yahoo.com wrote: > > V4 FPGA has independently RXSIGDET port signal,but V5 not. > > > how to detect the signal on V5 GTP? > > Page 155 > > http://direct.xilinx.com/bvdocs/userguides/ug196.pdf > > You need to configure the "loss of Sync (LOS) state machine for the > standard you wish to use. > > Austin i think it should be RXLOSSOFSYNC[0] representation incoming data. right? thx your help.Article: 121513
Antti wrote: > On Jul 6, 7:44 am, Franz Hollerer <franz.holle...@ims.co.at> wrote: >> Hi, >> >> I started to learn ISE and EDK 9.1i, but I spent much much time to get >> things running because they did not work as described in the manuals. >> >> Now I write this posting in the hope that someone from Xilinx will read >> it and consider it for further software development. >> >> I tracked down the problems to two sloppinesses which never should be >> done in software development: >> >> a) The GUI does not evaluate the return code of programs it calls. >> This leads to situations where the GUI shows 100% complete, 0 errors but >> nothing has been done at all, which makes it very hard to find the real >> cause for subsequent errors. >> >> b) Some command line programs like "simgen" return 0 even if errors >> occurred. Thus makes it impossible for "make" to stop on errors, and >> again, makes it very very hard to find the cause for subsequent errors. >> >> Thus dear Xilinx programmers please note: >> - NEVER ignore the return code of a program. >> - Always return 0 on success and a value between 1 and 255 if an >> error has occured. >> >> If you follow this hint you will save us (your customers) and your >> support department much time, money and nerves. >> >> Is there a Xilinx manager out there who have ever considered how much >> money Xilinx must have wasted by not following this simple ground rules >> in software programming? >> >> Best regards, >> >> Franz Hollerer > > the amount of time Users of Xilin silicon devices spend "fighting" > with Xilinx software is enorm. > So far it really looks that Xilinx isnt listening. Things are not > improving. > Only new bug comes, and old ones re-apperar... Xilinx seems to be listening (or at least to have been listening). Unfortunately, the decision makers are not in touch with the listeners whatsoever :-/ I've had some contacts with Xilinx a few months ago regarding the Xilinx Platform Cable USB and the horrible Windriver they use. I pointed out that there are clean, free and open-source solutions to interface USB devices from userspace that would solve many user issues with Windriver (not even talking about the numerous security holes). People listened, developers didn't act. A piece of the chain is probably broken in the middle. As long as companies will refuse offers such as "I can make your software work better, here's how, and I'm willing to spend time on this to help you for free", we won't get decent softwares. Just my 2 cents. Laurent PinchartArticle: 121514
Hello, I've just started a small project with a Xilinx Virtex 4FX board. In general terms my objective is to read various data over a Gigabit Network, manipulate them, and then transmit them back to the Network. I've been looking at the application notes at Xilinx.com, and some of them appeared to be helpful to give me a quick start. But unfortunately all the projects available are updated for ISE/EDK versions 8.2 and over. My board came with ISE/EDK 7.1, so I couldn't use any of those. Is there a way to get my hands on any of those example applications's previous versions, for my ISE/EDK? Any suggestions/recommendations to a newbie from the FPGA experts? Thank you for your time.Article: 121515
>I tracked down the problems to two sloppinesses which never should be >done in software development: >a) The GUI does not evaluate the return code of programs it calls. >This leads to situations where the GUI shows 100% complete, 0 errors but >nothing has been done at all, which makes it very hard to find the real >cause for subsequent errors. Add a wrapper that will pop up it's own "An error occoured" ..? >b) Some command line programs like "simgen" return 0 even if errors >occurred. Thus makes it impossible for "make" to stop on errors, and >again, makes it very very hard to find the cause for subsequent errors. Maybe one can workaround this as customer by renaming original program and then add a wrapper that will check that the original actually did work? >Thus dear Xilinx programmers please note: >- NEVER ignore the return code of a program. >- Always return 0 on success and a value between 1 and 255 if an > error has occured. This really makes me wonder.Article: 121516
On Jul 6, 5:32 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 06 Jul 2007 01:58:21 -0700, > > vssumesh <vssumesh_a...@yahoo.com> wrote: > >I also arrived in the same solution, though i reduced the number of > >sync flops to two like "if (resync1 and not resync2)". My thought was > >now we have some fast FFs and this enable signal is going to be used > >only at the next +ve edge of 100MHz, so by that time we get a valid > >signal in the "enable_1MHz". Will this assumption work? > > The extra FF provides protection against metastable events on > "resync1". If your fast clock were, let's say, 20MHz then I > definitely would not bother with the extra FF. The question > is: how likely is it for a setup/hold violation on "resync1" > to induce enough metastability to push its settling time out > to about 9ns? A third FF is much cheaper than the time it > takes me to look up, and calculate, the math :-) Actually its worse than that. Since the tools usually work with a PERIOD constraint, how can you be sure that you have anywhere near 9 ns of slack in this path to handle this event? Probably 3 ns is enough for most metastable events, but how do you even know you have 3 ns slack without looking through the placed design afterwards? In the 2 flip-flop case there is a high probability that the path between flops will have a large slack at 100 MHz since there are no intervening LUTs. If you want to go overboard, you can hand place the synchonizing flops to ensure lots of timing slack. Regards, GaborArticle: 121517
I dont think yoy are a newbie and i am not a FPGA expert... Anyway contact your local dealer from whome you bought this board. They might have some evaluation version of the latest ISE. Also if your design is for small FPGA you can use latest xilinx webpack which is freely available at xilinx site. regards Sumesh V SArticle: 121518
On Jul 6, 1:20 am, vssumesh <vssumesh_a...@yahoo.com> wrote: > Thanks Gabor for these valuable replys. First of all, how can i draw > waveform diagrams in this group? I have seen lot of sessions with neat > diagarm, my diagarm was also good when i draw it on the tesxt window > but when in converted to the html page it somehow got distotred. How > can i share my diagrams with you? > > Comming to your second suggestion, that ack from the 100MHz domain to > the 1MHz domain is exactly what i want, but how we can do that? The > flag which indicates that is set on 100MHz clock and rest on 1MHz > clock. Is that possible to use two clocks in a single FF? > The idea was to use one clock and an asynchronous reset. This is why I also suggested that there was a problem concerning multiple events. It could happen that the asynchronous reset masks out a new update. If you want to be sure to handle all updates, but are not worried about responding twice to the same update, you can reverse the process and use an asynchronous set when the update occurs, and synchronous reset on the 1 MHz clock when the update is processed. Still you need to be careful because the set event can come very close to the 1 MHz clock edge. > I am thinking of another process similar to your suggestion that the > flag will be set at 100Mhz, but will also be reset at 100MHz when an > edge happend at the 1MHz signal. But these information that an edge > happend at the 1MHz location is also needed to be synchronised to the > 100MHz domain. That will delay it by two more cycles in the 100MHz > domain. > This is generally the preferred method. Keeping handshake in one clock domain removes the race conditions. However now you need to deal with the possibility of a new update occuring just after an edge of 1 MHz but before the reset signal. Make sure that the 1 MHz process sees the new updates by re-asserting the flag (or not clearing it) if another update has occured within 3 100 MHz cycles prior to the reset signal. > Your first suggestion i could not understand fully. What will happen > if i use only two flops operting at 1MHz clock. Please explian me why > some bits will be differnt from other bits. My two clocks are fully > asynchronus. This is important. Two flops are the approved method of synchronizing a single signal to avoid metastability issues. However this does not deal with data coherency. If your registers are single bits with independent functions, or are known to only change one bit at a time (like Grey code) then the 2-stage synchronizer is all you need. But what if you are transferring binary data like an 8-bit number? Now if in one clock domain the number goes from 01111111 to 10000000 binary, the value has changed by 1 count, but all the bits have changed together (in that domain). This does not mean that the bits will change together as sampled in the other clock domain. Varying path delays can cause some bits to meet the setup to the 1 MHz clock when others don't. Then even though there may be no metastability on any of the sampled bits, you could easily read a value like 00000000 binary if for example the highest bit had a longer path delay than the lower 7. The second synchronizing register would not fix this, only delay the 00000000 value by another 1 us. A much better approach is to use a register clocked by 100 MHz with a clock enable generated like your handshake reset just after the rising edge of 1MHz. This register would be guaranteed to update coherently, but would have nearly 1 us of setup to the next 1 MHz rising edge.Article: 121519
"Gabor" <gabor@alacron.com> wrote in message news:1183725549.431632.71640@n60g2000hse.googlegroups.com... > On Jul 6, 5:32 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > Actually its worse than that. Since the tools usually work with > a PERIOD constraint, how can you be sure that you have anywhere > near 9 ns of slack in this path to handle this event? > Hi Gabor, You know this already, but for the record:- NET "numa_numa" MAXDELAY 1ns; or somesuch. HTH, Syms.Article: 121520
<pbFJKD@ludd.invalid> wrote in message news:468e36f4$0$539$cc7c7865@news.luth.se... > >I tracked down the problems to two sloppinesses which never should be >>done in software development: > >>a) The GUI does not evaluate the return code of programs it calls. >>This leads to situations where the GUI shows 100% complete, 0 errors but >>nothing has been done at all, which makes it very hard to find the real >>cause for subsequent errors. > > Add a wrapper that will pop up it's own "An error occoured" ..? > >>b) Some command line programs like "simgen" return 0 even if errors >>occurred. Thus makes it impossible for "make" to stop on errors, and >>again, makes it very very hard to find the cause for subsequent errors. > > Maybe one can workaround this as customer by renaming original program and > then add a wrapper that will check that the original actually did work? > >>Thus dear Xilinx programmers please note: >>- NEVER ignore the return code of a program. >>- Always return 0 on success and a value between 1 and 255 if an >> error has occured. > > This really makes me wonder. > For what it's worth I switched to Lattice recently (May 2006) because I got fed up with run around on pricing and availability from Al and Xi . Since then Xi have changed distribution in UK so it may be better. I'm using Aldec Active HDL for simulation and some high level schematic entry, ISP Lever for chip specific stuff. My project is not large (LFECP15E about 10% utilisation - we want room to grow !!) but I have had no tools issues at all. Michael Kellett www.mkesc.co.ukArticle: 121521
Hello, I'm testing ML501 board, very nice. On the Xilinx site the documentation of this board has some errors like the constraints file(...also unavailable...). Looking the EDK example design I see errors between UCF file generated for "ml501_bsb_design" and the Schematics(Sheet 3 of 22, for example) http://www.xilinx.com/products/boards/ml501/files/ml501_bsb_design.zip http://direct.xilinx.com/bvdocs/userguides/ml501_20061010_bw.pdf All DDR2 memory pin connected to the FPGA Banks are wrong(they are inverted?) I rebuild from scratch pin-to-pin from the Official schematics all DDR2 LOC pins to implement one working UCF file but I found this incongruence in the EDK UCF file. What UCF file I use with this Board? Reading this simple guide I made a bitstream without problems, and It's working well. http://www.xilinx.com/products/boards/ml501/docs/ml501_bsb_design_creation.pdf In this situation I think the UCF file generated by the EDK flow are ok However I think there's a confusion. I think is a good idea if Xilinx put a general UCF file for her ML501 board with DDR2,ETH,USB, and other constraints to safe lot of time(with a lamp and zoom into schematics....). happy day, Callisto.Article: 121522
>> Thus dear Xilinx programmers please note: >> - NEVER ignore the return code of a program. >> - Always return 0 on success and a value between 1 and 255 if an >> error has occured. > > This really makes me wonder. > why?Article: 121523
On Jul 6, 4:48 am, Marco Albero <periket2...@ya.com> wrote: > I'm developing an embedded web server into a XupV2pro board with a > VirtexII-pro fpga. While all my code was in the bram memory all works fine, > the problem was that the application grew and grew until a moment when the > EDK says that my bram was full. > Now I need relocate some parts of my application (code, data or both) to > fit in external DDR RAM, the problem is that I try to do this visually with > the EDK's option 'generate linker script', putting section .text and .data > outside bram into DDR. I recompile the project and all is right but when y > download it to the fpga it doesn't work. I go back, remove some files of my > project, generate a new linker script where all sections were in bram, > compile, download and it run fine. > I would like you help me to understand the 'linker script' and how to > generate one for my purpose. > > Thanks in advance. The JTAG loader only loads the BRAM's, since they are part of the FPGA. IOW, you have loaded the hardware, but not the software. You can use XMD to load your application into external memory via JTAG, or put a bootloader in BRAM, and have it load your app from somewhere else (typically flash, but you could boot from the network server, serial port, etc.) Alternately, you can use SysACE, and load everything (FPGA configuration & application) from CF. The advantage to the SysACE chip is that you can skip the configuration PROM altogether, and you don't need JTAG tools (it uses a FAT filesystem)Article: 121524
My SATA host controller includes TX/RX OOB Sequence generation
ciruit(it
can generate COMRESET/COMINIT/COMWAKE).
My GTP setting is as following,
a>GTP clock:150M,Gen1 mode,8 GTP;
b>Datawidth:16bit,enable 8B/10B
c>Default OOB detection threshold:000
d>RXLOSSOFSYNC port is set FALSE,it will be regard as signal
detection.
e>TXCOMSTART/TXCOMTYPE=1'b0 is included(they must be included or
only option?).
f>Other all options are default
My verification environment is ,
1>SATA Device BFM<---->Xilinx V5 SATA GTP<----->SATA Host.
first,SATA Host sends COMRESET sequence to GTP.But my SATA Device
BFM is
no respond.
As an example,i replace Xilinx V5 SATA GTP with SATA Host PHY
BFM.SATA
Device BFM and SATA Host controller are same.
2>SATA Device BFM<---->SATA Host PHY BFM<----->SATA Host.
The SATA Device BFM can respond COMINIT sequence after COMRESET .
Ok,I test 8 GTP ports with loopback mode.My Host controller
COMRESET's
sequence is 6 repeat sequences(signle sequence is:4abc 7b4a 4abc 7b4a
4abc
7b4a 4abc 7b4a)
Port0>loopback=3'b001:
my rxdata result is: bcbc 4a4a bc7b 4a4a bc7b 4a4a bc7b 4a4a 4a7b,
bc7b 4a4a bc7b 4a4a bc7b 4a4a bc7b
4a4a 4a7b,
bc7b 4a4a bc7b 4a4a bc7b 4a4a bc7b
4a4a 4a7b,
bc7b 4a4a bc7b 4a4a bc7b 4a4a bc7b
4a4a 4a7b,
bc7b 4a4a bc7b 4a4a bc7b 4a4a bc7b
4a4a 4a7b,
bc7b 4a4a bc7b 4a4a bc7b 4a4a bc7b
4a4a 4a7b,
Port1>loopback=3'b000
SATA Device BFM is no repond.
Port2>loopback=3'b010;
my rxdata result is: ab85 4abc 7b4a 4abc 7b4a 4abc 7b4a 4abc
7b4a,
4abc 7b4a 4abc 7b4a 4abc
7b4a 4abc 7b4a,
4abc 7b4a 4abc 7b4a 4abc
7b4a 4abc 7b4a,
4abc 7b4a 4abc 7b4a 4abc
7b4a 4abc 7b4a,
4abc 7b4a 4abc 7b4a 4abc
7b4a 4abc 7b4a,
4abc 7b4a 4abc 7b4a 4abc
7b4a 4abc 7b4a,
Port4>loopback=3'b100
SATA Device BFM is no repond.
Port5>loopback=3'b100
SATA Device BFM is no repond.
Port6>loopback=3'b110
SATA Device BFM is no repond.
Port7>loopback=3'b000
SATA Device BFM is no repond.
why my SATA device BFM no respond?
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