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On Jul 3, 1:54 pm, "Tim (one of many)" <t...@nooospam.roockyloogic.com> wrote: > Alan Nishioka wrote: > > I have tried changing the mode pins (difficult because they are > > connected directly to V33 and gnd) to no effect. But JTAG should work > > regardless of the mode pin settings, right? > > Yes, JTAG works in all modes. And maybe you have the mode pins set to > salve serial. Or even floating, which means that the default pullups > pull them to slave serial, depending on the HSWAP pin. > > What I was suggesting is that you try programming the part in slave > serial mode. That could show up any one of a host of problems. If slave > serial works and JTAG doesn't... > > Good luck. Thank you all for your ideas. I now have a few more things to try. Alan NishiokaArticle: 121426
On Jul 3, 7:36 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > AugustoEinsfeldt wrote: > > Thanks for all responses. Because the time zone I was unable to reply > > earlier. > > The device will do a lot of slow timings (1 second to 10 minutes), > > read 6 serial interface ADC converters (with 2.5MHz SCLK) and talk to > > a CPLD (used as port expander and watchdog) at 10Mbps data rate. It is > > a 3S200 and may have up to 70% of resources used. > > > I may stick to the pull-down resistor idea because the system MTBF. > > Resistors cause less impact here. > > System has a XPLA3 CPLD and other circuits at 3V3 (that is supplied > > by a TDK's DC-DC converter) and I think the excess of current will > > sink easily. But I will calculate it again. TDK's never answered about > > sink capability of their DC-DC modules and I'd like to avoid using a > > 3V6 zener to do not waste energy in some temperature conditions. > > The signal's rise/fall time are around 50us (worst case). I know it is > > very slow for this device and I will have some extra current in the > > pin's input circuitry but the cycle time of each signal is in the > > range of several minutes. So the impact of slow signal transition may > > not be important for the system. Only 2 to 5 signals of 56 may change > > at same time and since they came from mechanical feedback it is very > > unlikely they will really change precisely together. > > If you are chasing high operational MTBF, I would be wary of feeding > slow edges into a device running a lot of other logic. > I have seen very strange effects, caused by input theshold oscillations > on Digital devices without hysteresis. High series R makes this effect > worse. > [I think Xilinx fpga's may have small Hyst, you'll need to check ] > > > > > The design did use schmitt-trigger devices for the inputs in the past > > but the MTBF did fall because other added circuits and I thought I > > could work out the bounce and slow edges with some sample/timing logic > > in the FPGA. > > > Each of these input signals has a transient suppressor and another > > 100ohm resistor to the input connector. Those are to protect against > > huge ESD strikes and EMC/EMI. > > > Exercising a bit longer in this subject, in case I can sink externally > > (to the FPGA) the excess of current (56mA) and since each clamp diode > > for this device can handle 100mA (according DS099), which leads a good > > current injection handling, the single input resistor (no pull-down) > > could work. I am in the limit of system MTBF and it is why I still > > thinking to avoid any other component... The main question remains: > > would the FPGA's MTBF be reduced because this current flowing in the > > clamp diodes? > > > System cost is not a big issue but I'd like to avoid high reliability > > resistors because availability and lead times. While writing this text > > I am having second thoughts about avoiding these resistors... but your > > opinion would help in the FPGA's MTBF. > > What about 4-Pack resistors ?. That slashes the component count, so > should improve your MTBF. > > Another design approach, would be to hold the IP pins low, most of the > time, and tristate for narrow window, and read the Pin status at the end > of that time. > Result is no significant clamp energy, and faster slews - as you now > effectively sense a CURRENT level, not a voltage level. > [ eg at 1mA and 10pF I get 20ns for 0-2V slew] > > -jg Jim, I had exactly the same thought minutes ago and was going to post it when I saw your message. This sounds a good idea. Important to know there can happen strange effects with low slew rate signals, so this approach seems to solve all issues. Using inout pin and keeping it as output in zero for most of the time can effectively reduce the stress. I would do the signal sampling in the previous input design, anyway, so the solution was already half way. Thanks, -AugustoArticle: 121427
Subject: Unable to use xmd or mb-gdb with microblaze cycle accurate
simulator target
Hello:
I am trying to use gdb and xmd to connect to the cycle-accurate
simulator target on microblaze but have been quite unsuccessful. Here
are the steps followed this far:
1) Compiled code with ‘No optimization’ and ‘-xlmode-executable’
option set in XPS studio
2) Chose ‘Simulation’ under ‘Debug->XMD Debug options’
3) Launched XMD from XPS and not from command line
4) Launched GDB which displayed the source program &
5) Within gdb set these options:
a. Target Settings: break point at ‘main’ and exit and also set
break points else where within the code
b. Connect to target & download
c. ‘Run Method’->’Run’
6) With these options set the ‘Run’ button was hit and the program
stalled at _start
7) Upon ‘continue’ xmd crashes with a windows message that says ‘xmd
encountered a problem…’
So I figured that since xmd is the interface for gdb I’d try stepping
through xmd shell instead. These were the commands tried out manually
in xmd shell.
1) connect mb sim
2) xload xmp system.xmp
3) xload mhs system.mhs
4) xload mss system.mss
5) dow executable.elf
6) bps 0x00000bf8 ? setting software break point
7) con or stp 10 or run ->xmd crashes and windows displays an error
message similar to the previous scenario
The system contains a UART peripheral and from what I understand
simulation of peripherals is not supported. But could that be the
cause of the crash? Shouldn’t it still be possible to step through the
initial set of instructions at least?
Also,I am able to use similar commands to connect and step through the
Virtual Platform target and successfully display things on the virtual
uart terminal – unfortunately trace isn’t supported for microblaze VP.
So in summary here are my queries:
1) What am I missing to successfully use xmd/gdb to connect to the
cycle-accurate simulator target on microblaze? Is a opb_mdm module
required? That isn’t present in my system and even with that I had no
success.
2) Is it possible to obtain a trace/profile information using this
approach? What I need is the number of clock cycles consumed.
Any guidance and tips provided would be very much appreciated since it
would help me pace up my simulation efforts.
Thanks
Prasad Subramanian
Graduate Student
Utah State University
Article: 121428john.m.oyler@gmail.com wrote: > (Note: I realize that some/all of the Xilinx cpld's can do 5v, but I'm > really wanting to play with something heftier.) Rather than opt for a whole slew of buffers and associated real-estate, I opted to use a CPLD almost exclusively for 3.3-5V buffering. It's a trade-off between cost, real-estate and routing... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 121429
On Jul 3, 5:22 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: >Xilinx is much better served at using resources in making there existing > toolset better as they still need to mature, lest they lose market share > in areas that they dominate. Ahhh .... exactly, losing existing market share that is the reason DSP blocks are in FPGA's today.Article: 121430
Totally_Lost wrote: > On Jul 3, 5:22 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: >> Xilinx is much better served at using resources in making there existing >> toolset better as they still need to mature, lest they lose market share >> in areas that they dominate. > > Ahhh .... exactly, losing existing market share that is the reason DSP > blocks are in FPGA's today. Why do people whine so mercilessly when their favorite niche application doesn't have the requisite multi-million dollar investment in tools? Reconfigurable computing is great. It's just not supported natively by general purpose hardware that has a huge, general market. Get over it. Unless you have many millions to spare to develop the technology to get the few reconfigurable computing folks up and running. We'd welcome the addition!Article: 121431
Amontec, Larry wrote: > Amontec, Larry wrote: > >> ON NEXT MONDAY : 17-JUNE-2006 >> >> Amontec will provide the ‘how-to’ program via a XILINX VIRTEX XC4VLX25 >> 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! >> >> On next Monday, your Amontec JTAG key will be close to the speed of a >> Xilinx Platform Cable USB for programming any FPGA and CPLD vendors >> (Altera Xilinx Lattice Cypress ...) >> >> Come back next Monday on http://www.amontec.com ! >> >> Laurent > > > Hi all, > > You may download the Amontec SVF Player from > http://www.amontec.com/jtagkey.shtml > > Already tested for programming Altera Lattice Xilinx FPGA s CPLD s and > FLASH s. > It can be use for programming AVR ATMEGA processors too. > But you may use it as custom JTAG Boundary Scan. > > Infini SCAN LENGTH ! > Infini number of TAP (number of Targets) integrating Header and Trailer > scans. > > The amtsvfplayer.exe comes with c project source. Also, you may edit the > source, customize it and re-compile a new SVF Player for your specific > needs. > > amtsvfplayer.exe -h to get help on usage. > > You may execute SVF Files or SVF Lines. > A SVF Line could be a concatenation of SVF commands. > > You may adapt JTAG Frequency (FREQUENCY) via -frequencyFactor. In this > way you do not need to edit the SVF yourself. When using > -frequencyFactor, the RUNTEST x TCK is automaticaly updated ... > > Linux version ready to be published. > > HAVE FUN WITH JTAG AND SVF ! > ... but you need to have the JTAGkey. > > Regards, > Laurent > http://www.amontec.com > > Ann: via JTAGkey, you have a lot of ARM Debug Solutions too, including > OpenOCD JTAG server, Crossworks, Yagarto ... ! Timing for small devices: Xilinx Coolrunner XCR3128 ERASE / PROGRAM / VERIFY -> JTAG generation from SVF Player SVF used : http://www.amontec.com/chm_appl_test_led_blink_prog_check.svf ... in 601 milliseconds ScreenShot : http://www.amontec.com/jtagkey.shtml Regards, LaurentArticle: 121432
Hi all, I wrote a generate loop to generate a switching logic. I am getting the expected circuit from the synthesizer(synplify). But it's not working in the simulator ( Modelsim ). The code is like this genvar i; generate for(i=0;i<elements;i=i+1) begin:A1 assign source_out[i*8+:8] = (enable[i])?result[address[i*6+:6]*8+: 8]:source_in[i*8+:8]; end endgenerate The requirement is, i have two bus(64 bytes each) and each byte of the output of the block can be from the corresponding position from the source or from anywhere (according to the address) from the result bus.Article: 121433
Jim, I am using two XC95108 which are completely oversized for that task simply because I have two of them on my breadboard. Each of them features the programmable predivider (not in use) and the quadrature circuitry made from two d-flipflops. The outputs lead to an external 74AHC1G86. The fluctuations ( I don't like to call them jitter because they are not stochastic) have dropped from +/-450 ps to abt. +/-50 ps. Regards Ulrich "Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag news:4689f747$1@clear.net.nz... > Ulrich Bangert wrote: > > > Gents, > > > > this is to let you know that departing the two clock signals into two > > separate cplds and xoring them with external single-gate-logic has improved > > the situation a lot. > > Good to hear that :) > > Can you quantify "improved the situation a lot", so readers can know > what the relative jitter levels are ? > > Which/how many single gate devices did you use ? & which CPLDs ? > > > > -jg > > > >Article: 121434
People like yourself do have have problems using FPGA's in old system add-ons. Often modern FPGAs need multiple power rails and simply can't take directly 5V inputs. In response to some of these needs we have developed some products to help. If you want an easy path to using a modern FPGA in an old style computer have a look at our Craignell modules http://www.enterpoint.co.uk/component_replacements/craignell.html. These offer a Xilinx Spartan-3E FPGA module in a DIL standard format. We have made the module power input 5V (normal DIL position) and the I/ O 5V tolerant and pulled up to 5V to drive external CMOS level logics. First batch of these has sold out but we have a second batch in manufacture and likely to be available in about 4 weeks time. We have added a new size in this second batch so we will have DIL28,32,36,40 versions and also coming is the derivative product Drigmorn1 which will be a development board rather than for the obsolete component replacement/easy build markets that are Craignell modules main targets. Pricing on Craignells is from GBP=A335, US$70, 55=80 on one offs and we be offering versions with XC3S100E, XC3S500E and possibly XC3S250E FPGAs. John Adair Enterpoint Ltd. On 3 Jul, 19:21, john.m.oy...@gmail.com wrote: > I've spent several hours browsing the Xilinx site (and not so much > less the Altrera site), and I'm starting to get some idea of what all > the different device families are. > > However, after digging through numerous pdfs, it looks like everything > is 3.3v and under. All of the cool stuff I'd like to try to do > interfaces with old computers, vintage stuff. > > How does one interface to TTL logic? Which devices can be used for > that, and what does it take to safely hook them up to something that > is 5v? > > (Note: I realize that some/all of the Xilinx cpld's can do 5v, but I'm > really wanting to play with something heftier.)Article: 121435
Hi everyone. I have a core to control a I/O peripheral. This core is based on a FIFO to get words from a I/O bus (32 bits). But now, I want to read from the FIFO and copy the words to the BRAM. I know this core runs ok but I need to map the packets from FIFO to the memory so I could access whenever I want. I have though in DMA to implement it. But at the moment I am not sure if this solution is the best. I am using "Create and Import Peripheral Wizard" from Xilinx to add this funtionality to the PowerPC proccessor and access the words by a pointer. Another solution is to implement the DMA manually but I am not any idea. Any suggestion. Regards PabloArticle: 121436
RCIngham wrote: > The multipliers in Altera Stratix FPGAs can be operated in a Q1.15 > fractional binary mode that I have found to be useful in a previous > project. > > If the Xilinx multipliers can be operated in a similar mode it might be > a/the answer to your problem. Thanks for all your answers. 'lamda' is within (-1,1) and transmitted into fpga board from matalab. Before it transmitted to uart, lamda has been changed to Q15 format. I need 'lamda' update correspording to the interative times from 1 to 5. I guess I am wrong here. I cannot direct use the integer * Q15 binary. Coz the 'lamda' is binary and has been enlarged 2*16 whereas interative number is not. I did not know how to figure it out so far. So can I just generate the 5 interative numbers and multiply from matlab and transformed to Q15 format, then transmit to the fpga. (It looks so silly) Also the Q15 updated lamda will mulitply another Q15 parameter. 2 signed prod[15 0] multiply. If I want to keep 32 bits. Is it correct that I just keep prod[30 0] & '0' as my result. I removed the first sign. One more thing, the type in the multiplier is 'signed', why i still can use 'std_logic_vector'. Is it same? And I don't need to convert 'std_logic_vector' to 'signed'.Article: 121437
Does anyone know what it means pinout compatible to UFS / Twister / N-Box / Power Flasher & Other compatible gsm interfaces. Where do I fins this pinout?Article: 121438
<darrick> wrote in message news:468b70a9$1_2@mk-nntp-2.news.uk.tiscali.com... > Does anyone know what it means > > pinout compatible to UFS / Twister / N-Box / Power Flasher & Other > compatible gsm interfaces. > > Where do I fins this pinout? > > Google? pinout ufs twisterArticle: 121439
Can you help me with google. I tried to find out the jtag pins but couldn't. The socket is IDC 16 WAY which is comtatible with UFS / Twister / N-Box / Power Flasher & Other GSM Thanks in advanceArticle: 121440
Perry wrote: > On Jun 26, 2:19 pm, Sebastian Goller <s...@hrz.tu-chemnitz.de> wrote: > >>Perry wrote: >> >>>On Jun 25, 10:01 pm, Sebastian Goller <s...@hrz.tu-chemnitz.de> wrote: >> >>>>I'm currently developing a design for the XUP development board. The >>>>development software is Xilinx EDk 8.2 >>>>The system requires several frequencies. >> >>>>Power PC : 100 MHz >>>>PLB : 50 MHz >> >>>>User IP : 50 MHz, 2.5 MHz >> >>>>The EDK uses DCM_0 to divide the 100 MHz by 2. I use 2 cascaded DCMs to >>>>generate the 2.5 MHz (first divides by 2, second divides by 10). >>>>But when I want to generate the bitstream the following messages and >>>>errors occur: >> >>>>INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not >>>>connected >>>> to an external port in this design. A new port >>>> 'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected >>>>to this >>>> signal. >>>>INFO:NgdBuild:889 - Pad net >> >>>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' >>>> is not connected to an external port in this design. A new port >> >>>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' >>>> has been added and is connected to this signal. >> >>>>Applying constraints in "xup_morpheus5.ucf" to the design... >> >>>>Checking timing specifications ... >>>>INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification >>>> "TS_sys_clk_pin", was traced into DCM instance >>>> "dcm_0/dcm_0/Using_Virtex.DCM_INST". The following new TNM groups >>>>and period >>>> specifications were generated at the DCM output(s): >>>> CLK2X: TS_dcm_0_dcm_0_CLK2X_BUF=PERIOD dcm_0_dcm_0_CLK2X_BUF >>>>TS_sys_clk_pin/2 >>>>HIGH 50% >>>> CLKDV: TS_dcm_0_dcm_0_CLKDV_BUF=PERIOD dcm_0_dcm_0_CLKDV_BUF >>>>TS_sys_clk_pin*2 >>>>HIGH 50% >>>>INFO:XdmHelpers:851 - TNM "dcm_0_dcm_0_CLKDV_BUF", used in period >>>>specification >>>> "TS_dcm_0_dcm_0_CLKDV_BUF", was traced into DCM instance >> >>>>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I >>>> /DCM_INST". The following new TNM groups and period specifications were >>>> generated at the DCM output(s): >>>> CLKDV: >>>>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_ >>>>CLKDV_BUF=PERIOD >>>>board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_CLK >>>>DV_BUF TS_dcm_0_dcm_0_CLKDV_BUF*2 HIGH 50% >>>>INFO:XdmHelpers:851 - TNM >> >>>>"board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I >>>> _CLKDV_BUF", used in period specification >> >>>>"TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbi >>>> t_I_CLKDV_BUF", was traced into DCM instance >> >>>>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_2 >>>> _I/DCM_INST". The following new TNM groups and period specifications >>>>were >>>> generated at the DCM output(s): >>>> CLKDV: >>>>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_ >>>>I_CLKDV_BUF=PERIOD >>>>board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_I_C >>>>LKDV_BUF >>>>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_ >>>>CLKDV_BUF*10 HIGH 50% >> >>>>ERROR:NgdBuild:455 - logical net 'plb_bram_if_cntlr_1_port_BRAM_Clk' has >>>> multiple driver(s): >>>> pin PAD on block >> >>>>plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_port_BR >>>> AM_Clk with type PAD, >>>> pin O on block dcm_0/dcm_0/Using_BUGF_for_CLKDV.CLKDV_BUFG_INST >>>>with type >>>> BUFG >>>>ERROR:NgdBuild:924 - input pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' >>>>is driving non-buffer primitives: >>>> pin C on block reset_block/reset_block/core_cnt_en with type FD, >>>> pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with type FD, >>>> pin C on block reset_block/reset_block/Rstc405resetchip with type FD, >>>> pin C on block reset_block/reset_block/Peripheral_Reset_0 with type FD, >>>> pin C on block reset_block/reset_block/Rstc405resetsys with type FD, >>>> pin C on block reset_block/reset_block/Core_Reset_Req_d3 with type FD, >>>> pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with type FDRE, >>>> pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with type FDRE, >>>> pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with type FDRE, >>>> pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with type FDRE, >>>> pin C on block reset_block/reset_block/SEQ/pr_dec_0 with type FDR, >>>> pin C on block reset_block/reset_block/SEQ/pr_dec_1 with type FDR, >>>> pin C on block reset_block/reset_block/SEQ/chip_dec_0 with type FDR, >>>> pin C on block reset_block/reset_block/SEQ/chip_dec_2 with type FD, >>>> pin C on block reset_block/reset_block/SEQ/pr_dec_2 with type FD, >>>> pin C on block reset_block/reset_block/SEQ/chip_dec_1 with type FDR, >>>> pin C on block reset_block/reset_block/SEQ/bsr_dec_0 with type FDR, >>>> pin C on block reset_block/reset_block/SEQ/bsr_dec_2 with type FD, >>>> pin C on block reset_block/reset_block/SEQ/seq_clr with type FDR, >>>> pin C on block reset_block/reset_block/SEQ/ris_edge with type FDR >> >>>>ERROR:NgdBuild:455 - logical net >> >>>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' >>>> has multiple driver(s): >>>> pin O on block >> >>>>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/ >>>> CLKDV_BUFG_INST with type BUFG, >>>> pin PAD on block >>>>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1 >>>> with type PAD >> >>>>ERROR:NgdBuild:924 - input pad net >> >>>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' >>>> is driving non-buffer primitives: >>>> pin O on block >> >>>>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/ >>>> CLKDV_BUFG_INST with type BUFG >> >>>>Does anybody know this problem. I did not apply any changes to the >>>>PLB_BRAM_IF_CNTL. Do I have to specify the new clock lines in one of the >>>>EDK files? >> >>>>Thanks in advance >>>>Sebastian Goller >> >>>It seems that you have connected more than one nets to the same output >>>or inout port. >> >>I already checked the source code and the edif netlist >>(design_analyzer). Everything is okay. The point that confuses me the >>most is, that the error regarding plb_bram_if_cntlr_1_port_BRAM_Clk >>occurs when I use the DCM_0 in the EDK. If I use the same frequency for >>the PowerPC and the PLB there is no problem at all. >>Same thing with the two cascaded DCMs in the user IP. No signal has more >>than one driver. >>The simulation of the behavioral model and the structural model works fine. >>Is there anything I have to add to the .mhs or the .mpd or to another file? >>I have already tried to modify the .ucf-file. I added the following lines >> >>Net "sys_clk_s" TNM_NET = "sys_clk_s"; >>TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" "TS_sys_clk_pin"/2; >>Net "board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1" >>TNM_NET = "clkdv_dcm1"; >>TIMESPEC "TS_clkdv_dcm1" = PERIOD "clkdv_dcm1" "TS_sys_clk_s"/2; >> >>After restarting NGDBUILD the following error occurs: >> >>INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not >>connected >> to an external port in this design. A new port >> 'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected >>to this >> signal. >>INFO:NgdBuild:889 - Pad net >> >>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' >> is not connected to an external port in this design. A new port >> >>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' >> has been added and is connected to this signal. >> >>Applying constraints in "xup_morpheus5.ucf" to the design... >>INFO:NgdBuild:757 - Line 14 in 'xup_morpheus5.ucf': The constraint for NET >> 'sys_clk_s' is being attached to the equivalent NET >> 'plb_bram_if_cntlr_1_port_BRAM_Clk'. >>ERROR:NgdBuild:756 - Line 16 in 'xup_morpheus5.ucf': Could not find net(s) >> 'board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' in the >>design. >> To suppress this error specify the correct net name or remove the >>constraint. >>ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. >>ERROR:NgdBuild:19 - Errors found while parsing constraint file >> "xup_morpheus5.ucf". >> >>What I do not understand is that NGDBUILD gives me an information about >>the signal >>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1" >>and five seconds later the signal can not be found in the design. > > > You set timing constraint for "board1_unit_0/board1_unit_0/ > USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1", but you didnt specify > a pin for it. Try to set a pin constraint for it. > Thanks for your help. I have found out that I need to remove the IBUFGs of the DCMs generated by CoreGenerator. An IBUFG has to be connected to a pad, which is not the case in my design.So afterArticle: 121441
I have a problem with the RocketIO component. The documentation says that I need a differential clock for the Rocket IO. I am using Xilinx EDK 8.2. The input frequency is 100 MHz. The bus frequency is 50 MHz. So a DCM has been included by the EDK. When I want to use the Rocket IO I have to generate a differenatial clock. The problem is, that I need an IBUFGDS to do that. But an IBUFGDS has to be connected to a pad. Otherwise NGDBUILD will produce an error telling me that signal XYZ is has multiple drivers and is driving non-buffer primitives. . There is no such thing like a BUFGDS. But since the input for the IBUFGDS is the 50 MHz clock from the DCM the IBUFGDS can not be connected to a pad. If I do not use the IBUFGDS I get a synthesis error. So what am I supposed to do in this situation? Thanks in advance Sebastian GollerArticle: 121442
Sebastian, I believe the documentation recommends using a differential clock on the board to supply one of the BREF inputs (which certian of the dedicated clock inputs) if the data rate is to be high e.g. above 2.5 GBps. This would require a differential input buffer, it is also recommended to connect this clock directly to the BREF clock input on the MGT and not use DCM's as they introduce to much jitter. For the user clock I think you are ok using internal clocks which have been generated by a DCM. If you are using data rates lower than 2 Gbps you can use the REFCLK inputs of the MGT these do not have to brough in via a differential input though it is still not recommened to use a DCM to generate REFCLKS due to the jitter introduced. see UG024.pdf from xilinx. >From the sounds of it you need a 100 Mhz clock this will have to be generated externally to the FPGA by either a oscilator in which case a differential input is recommended or a frequency synthesiser (we do this and it works ok) alternatively you could just use the 50 MHz clk Hope this makes sense, I wrote it rather quickly AdArticle: 121443
I believe the documentation recommends using a differential clock on the board to supply one of the BREF inputs (which are specific ones of the dedicated clock inputs) if the data rate is to be high e.g. above 2.5 Gbps. This would require a differential input buffer, it is also recommended to connect this clock directly to the BREF clock input on the MGT and not use DCM's as they introduce to much jitter. To drive REFCLK's as opposed to BREFCLKS I think you can use any clock internal to the FPGA as long as it is driven from a BUFG. Though for REFCLKS it is not recommended to use DCM generated clocks due to jitter on the outputs. You can use the REFCLK inputs to the MGT provided the speed is below 2.5 Gbps UG 024 provides more info For the user clock you are ok using internal clocks which have been generated by a DCM. You do not say if the 100Mhz clock you have divdied down to 50 MHz is for a reference clock (BREF or REF clk) or for the user clock ? You should be ok if the DCM is driving the user clock but may have problems if it is going to be driving the reference clocks. Hope this makes sense, I wrote it rather quickly AdArticle: 121444
subint wrote: > Hi all, > > I wrote a generate loop to generate a switching logic. I am getting > the expected circuit from the synthesizer(synplify). But it's not > working in the simulator ( Modelsim ). > The code is like this > > genvar i; > generate > for(i=0;i<elements;i=i+1) begin:A1 > assign source_out[i*8+:8] = (enable[i])?result[address[i*6+:6]*8+: > 8]:source_in[i*8+:8]; > end > endgenerate > > The requirement is, i have two bus(64 bytes each) and each byte of the > output of the block can be from the corresponding position from the > source or from anywhere (according to the address) from the result bus. In what way is it not working? Is the source_out always one of the two results? Are you certain the enable isn't an "x" value?Article: 121445
I tried the unbuffered jtag programmer, it is partly working. It allows me to go into the device with impact and select various command. For exmaple I can get the device id or checksum, but when I try to erase or program I receive fail. Any ideas? Second point, why is the buffered device use tri state buffers and not just normal buffers without tristate. Third point, is impact able to know when the programmer is buffered or not since it seems the buffered one requires more inputs from lpt?Article: 121446
Sebastian Goller wrote: > I have a problem with the RocketIO component. The documentation says > that I need a differential clock for the Rocket IO. I am using Xilinx > EDK 8.2. The input frequency is 100 MHz. The bus frequency is 50 MHz. So > a DCM has been included by the EDK. > When I want to use the Rocket IO I have to generate a differenatial > clock. The problem is, that I need an IBUFGDS to do that. But an IBUFGDS > has to be connected to a pad. Otherwise NGDBUILD will produce an error > telling me that signal XYZ is has multiple drivers and is driving > non-buffer primitives. . > There is no such thing like a BUFGDS. But since the input for the > IBUFGDS is the 50 MHz clock from the DCM the IBUFGDS can not be > connected to a pad. > If I do not use the IBUFGDS I get a synthesis error. So what am I > supposed to do in this situation? > > Thanks in advance > Sebastian Goller There is a strict jitter specification for the RocketIO input clock. The DCM output will completely violate this tightly spec'ed value. In over-simplified terms, the clock multiplication needs to know where the clock is within an *output* bit period; if the jitter is a large part of a bit period (or more than a bit) how could the the timing be effectively implemented?Article: 121447
Hello everybody, do You know how to change the program of an existing PicoBlaze implementation on a Xilinx Spartan 3E development board? The board uses an USB cable to download the bitstream to the FPGA. I have an existing design including a PicoBlaze processor and would like to change its ROM code without recompiling the complete project. The JTAG loader software only seems to work with the parallel port cable, at least it tells me so. Thanks for Your advice, Markus FrasArticle: 121448
Hi all,
i am designing a system in which we have a bram block,microblaze
processor and other essential component.
i have written a verilog code for bram controller (successfully
compiled)to interface bram block to opb bus.now i have to write a c
code to perform read write operation in bram block.i have written
following code
#include <stdio.h>
#include <mb_interface.h>
#include <xutil.h>
int main(){
printf("Hello this is the start, printing using print\n");
volatile char *pointer = ( volatile char *) 0x10013405;
*pointer = 'c';
char temp = *pointer;
printf("%c %c\n",temp , *pointer);
return 0 ;
}
which is not working
so regarding this i have following question
1-in c ,is it possible to assign address to a pointer according to
us ????
2-is it necessary to use gpio function to read write operation in a
peripheral ??
if you find some conceptual mistake in code then please reply
with regards
Ajay
Article: 121449The EPCS (serial configuration) devices are Altera's "low cost" alternative to the EPC (enhanced config) devices. Not only are the devices considerably less expensive they are also much smaller in size. So, typically, board costs and/or real estate drive which device you would choose. Keep in mind that you don't need to purchase either device to configure your FPGA. You can always buy some flash and have a micorprocessor perform the configuration. On speed: the enhanced devices have the ability to connect to the FPGA via a parallel bus which allows for a faster configuration option; the serial configuration devices are just that, serial data stream only. <jjlindula@hotmail.com> wrote in message news:1183410321.068726.124350@q75g2000hsh.googlegroups.com... > Hello, I'm trying to decide to use an EPC16 or EPCS64 to program the > Stratix II EP2S601020C3 on my board. Can any comment which method is > better/faster? Altera's development kits are using the EPCS64 so I > leaning that direction. > > Thanks, > joe >
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