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Hello John, Are you suggesting that the FPGA board should be the master instead of target? In one of my discussion in other threads, someone suggested that the link layer chip (PCI-to-1394 chip) should be set as master (i.e. to continue asserting grant value). At this point, I'm getting more confuse because I don't see how the other signals such as FRAME# or IRDY# (that is initiator driven signal) will be produce by the link layer chip. Could you help to clear this point?Article: 122351
Gang I created a half dozen example projects using ISE 8.2i and the PicoBlaze on my S3-1600 Dev Board. I'm really comfortable with asm programming so the lack of a C compiler was no big deal. I am running under Windows XP SP2 on a dual cpu P6 @ 1.8GHz and 2GB of RAM. Now I have started using the XPS 8.2i with ISE 8.2i so that I can do some MicroBlaze programming in C. I am creating some very simple hardware systems that consist of the CPU, a uart and some RAM. When I click the button to build the hardware bit stream it is taking 14 minutes to run. When I compile my C code it takes about 45 seconds to compile and then merge the ELF file with the hardware bit stream. This 14 minute hw build time is totally unreasonable. I find myself not willing to experiment with changes to the hardware because the associated build times. Am I doing something wrong? The entire hw and sw system is supposed to be based on MAKE files that only reprocess a file that has changed. The XPS environment depends on the ISE environment to create the hw bitstream. My initial ISE/PicoBlaze experiences were very nice (i.e. synthesis, map, place & route, etc were fast). Is there a way to describe my MicroBlaze design without using the XPS? or am I crazy for thinking this way? Any help would be appreciated. BobArticle: 122352
I am new to use Bottom-Up Incremental Compilation Methodology in Quartus and I have a question about it. I have exported partition from subproject and imported it to top-level design successfully. However, I can import a partition for only one time. In my project, I need to import the same partition for multiple times. Unfortunately, when I insert two blocks into the top-lever design and import the same partition, Quartus II report Error: "Found conflicting placement requirements for Partitions preserving Placement". Maybe, I made mistakes in some settings. Could someone tell me what should I do to solve the problem? P.S. I am using Quartus II 6.0 and Cyclone II EP2C35F672C8, thanks a lot!Article: 122353
Peter Alfke wrote: > > This really irks me...."no real advantages"... > I will not get into a propaganda tirade, but rest assured that there > are significant technical differences between the two competitors. I > am of course biased, and much more familiar with the Xilinx devices > and their special advantages. And -as promised- I will not elaborate > them here. > There are differences, for better or worse, between Obama and Clinton, > between the US and Canada, between BMW and Mercedes, between Apple and > Microsoft, and also between Xilinx and Altera. You may prefer one > brand over the other, but don't call it a toss-up! We worked hard to > make them different. > It is only when you ignore all the interesting and important fine > details that everything looks the same grey mush. > "Once you have seen one lake or one mountain, you have seen then all. > California is just like Ohio with some mountains and beaches thrown > in!" > Nonsense! > Peter Alfke Peter, As a long time Xilinx user and fan, as a convert from Altera (first by need, then by price and familiarity) I see both points. If there's a niche algorithm that makes or breaks the design or if there's a critical path that's impossible to implement in one vendor's devices, then the differences are extreme. The silicon from each vendor has its sincere strong points in certain corners. No one vendor can declare total domination, however, just greater market share. As an engineer tasked with coming up with the best price/performance solution to meet our Quality, Cost, and Deliverable (QCD) requirements, I choose one vendor over another. A design can be implemented in so many ways that a good engineer can come up with a superb implementation in one vendor's silicon that won't pass muster in the other. But turn it around and require the engineer to target the other device and that same implementation will be tweaked to the new silicon and not run so well on the original "vendor of choice" silicon. If any vendor stopped innovating, the market share would dwindle for that manufacturer and the whole industry would suffer; without the competition, the drive to excel is lessened. Because of the continuing innovation, the solutions stay close to the same level of performance with some algorithms or implementations winning hand over fist in one brand of silicon versus the other. QCD targets have to be met. If cost were identical, the quality factors can come into play. If new devices are promised but not delivered, the project's deliverables are in jeopardy. It's all an engineering trade-off. If Xilinx had only free parts with no delivery or software issues to consider, I would only use Xilinx. Any good engineer can produce an average design that meets the quality requirements. It's only the exceptional designs (or the sub-par engineers) that fail in this task. If I had a QCD requirements that made Ohio the "right" choice, I'd hope the experience could be just as fine in the end as the California story. I appreciate your passion. - John_HArticle: 122354
Eddie H wrote: > Does this mean that I do not perform timing simulation and only perform functional simulation? For a synchronous design, yes. > I do have period consntarints on the clocks and I am meeting this constraint. With no constraints, most tools report the Fmax as is. -- Mike TreselerArticle: 122355
bob.zigon@gmail.com wrote: > Gang > > I created a half dozen example projects using ISE 8.2i and the > PicoBlaze on my S3-1600 Dev Board. I'm really comfortable with asm > programming so the lack of a C compiler was no big deal. > I am running under Windows XP SP2 on a dual cpu P6 @ 1.8GHz and 2GB of > RAM. > > Now I have started using the XPS 8.2i with ISE 8.2i so that I can do > some MicroBlaze programming in C. I am creating some very simple > hardware systems that consist of the CPU, a uart and some RAM. When I > click the button to build the hardware bit stream it is taking 14 > minutes to run. > When I compile my C code it takes about 45 seconds to compile and then > merge the ELF file with the hardware bit stream. > > This 14 minute hw build time is totally unreasonable. I find myself > not willing to experiment with changes to the hardware because the > associated build times. > > Am I doing something wrong? The entire hw and sw system is supposed to > be based on MAKE files that only reprocess a file that has changed. > The XPS environment depends on the ISE environment to create the hw > bitstream. My initial ISE/PicoBlaze experiences were very nice (i.e. > synthesis, map, place & route, etc were fast). > > Is there a way to describe my MicroBlaze design without using the XPS? > or am I crazy for thinking > this way? > > Any help would be appreciated. > > Bob > Hi Bob - Could you post the map report (# of luts, # of brams) of the two systems? I suspect the Picoblaze system is vastly smaller. 14 minutes to run through synthesis, map and par seems quite reasonable, actually incredibly fast to me. As far as software changes go, I'd suggest that instead of initializing the bitstream with your ELF, just use XMD to download it. This way it takes only the time it takes for gcc. -SivaArticle: 122356
Peter, I'm not being a wise guy by an stretch. I am seriously inquiring for my own edification. Name some things that Xilinx can do that Altera can't or more specifically, is there an application out there in the world today that can only be solved with a Xilinx part? Would it be a fair statement to say that >90% of the designs out there can be done effectively with either company and the real advantages lie more with: 1. Service 2. Tools 3. Price 4. Delivery 5. Familiarity: meaning that once someone starts with a certain vendor, uses them for a while, and understand the hardware and how to flex it, they're less likely to switch--especially since most of us are put on ridiculous delivery schedules. Again, not trying to raise ire, just humbly asking a question. Best regards, Rob "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1185410018.909333.123160@z24g2000prh.googlegroups.com... > On Jul 25, 2:50 pm, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> > wrote: >> Thank you all for your input. To sum it up: >> >> Altera and Xilinx are indeed the major brands to look at. Lattice has >> some nice stuff, but is smaller and does not support VHDL (at least >> not in the low-end tools). >> >> There are no real advantages of one over the other (maybe there is for >> some specific designs). >> > This really irks me...."no real advantages"... > I will not get into a propaganda tirade, but rest assured that there > are significant technical differences between the two competitors. I > am of course biased, and much more familiar with the Xilinx devices > and their special advantages. And -as promised- I will not elaborate > them here. > There are differences, for better or worse, between Obama and Clinton, > between the US and Canada, between BMW and Mercedes, between Apple and > Microsoft, and also between Xilinx and Altera. You may prefer one > brand over the other, but don't call it a toss-up! We worked hard to > make them different. > It is only when you ignore all the interesting and important fine > details that everything looks the same grey mush. > "Once you have seen one lake or one mountain, you have seen then all. > California is just like Ohio with some mountains and beaches thrown > in!" > Nonsense! > Peter Alfke > > >Article: 122357
On Jul 25, 7:33 pm, "Rob" <robns...@frontiernet.net> wrote: > Peter, > > I'm not being a wise guy by an stretch. I am seriously inquiring for my own > edification. > > Name some things that Xilinx can do that Altera can't or more specifically, > is there an application out there in the world today that can only be solved > with a Xilinx part? Would it be a fair statement to say that >90% of the > designs out there can be done effectively with either company and the real > advantages lie more with: The temptation is there to answer with: FIFO, IDELAY, SRL16, DSP48 efficiency, PPC, etc., but that would just invite an endless series of acrimonious responses. Hell, there are many people who do vote for the party that I despise, and lots of people who seem to prefer the PC over the Mac. Just don't tell me there are no differences in user friendliness and elegance... FPGAs (and operating systems) are not (yet) a commodity, where only price and availability counts. Let's hope it stays that way for a while. Peter AlfkeArticle: 122358
Mike, I am using V5LXT and its GTP. At this point I am doing the simulation of the logic in the FPGA fabric that is feedting the data to the GTP transmitters. When I do the functional simulation, everything looks good but when I do the timing simulation I am not seeing simple logic in the FPGA fabric work. This is why I am intertested in looking at the Fabric logic state machine using timing simulation. The only thing that I can think of is to bring the fabric state machine outside on the FPGA pins. This will force the software to preserve the names. Eddie.Article: 122359
On 2007-07-25, colin <colin_toogood@yahoo.com> wrote: > > Many thanks for this info. I allways feel silly asking this sort of > question but I could only find version 2.0 on the PCISIG website. I haven't tried this with PCI-e, but for PCI I found a complete copy of several versions by googling for the exact title (in quotes) along with filetype:pdf to restrict the results. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 122360
Hello Group Members I am trying to build a simple system consisting of PowerPC405, JTAG, UART, OPB DDR controller, and 16MB External DDR memory on a HiTech PPC board. No on-chip BRAMs. I use EDK 9.1/ISE9.1 versions. If I try to launch XMD from EDK GUI, it prints messages detecting the programming cable and quits without printing any error messages. I tried invoking XMD from cygwin shell and used the command ' connect ppc hw', it detects the JTAG chain, prints the ID code and then quits printing 'ERROR(0):'. I have no idea what might be wrong here. Any help is very much appreciated. Interestingly, If I use only on-chip BRAM and no external memory, i can print messages to UART by downloading code through XMD. Thanks swamyArticle: 122361
On Jul 25, 8:10 pm, Peter Alfke <al...@sbcglobal.net> wrote: > The temptation is there to answer with: > FIFO, IDELAY, SRL16, DSP48 efficiency, PPC, etc., Distributed memory can also be really useful in cases. I'm surprised you didn't mention IO standards/features as it appears to me that that's where L., A. & X. each differs the most. Glad we have choices. TommyArticle: 122362
Hello everyone, I have a placed and routed .ncd file and I'd like to be able to convert it back to a simple netlist. It doesn't contain any "secured" core, so I can freely use all the xilinx tools suite on it. But there is no "ncd2edif" ... I convert it to XDL then somehow parse it ... but in the xdl I have the slice configuration, which means I would have to convert it to a basic element (LUT/MUXF5/...) + interconnections first ... That's gonna be quite painful to do. Does someone has a better idea/tool to do the job ? Thanks, SylvainArticle: 122363
In comp.arch.fpga, Jim Granville <no.spam@designtools.maps.co.nz> wrote: > > Stef wrote: >> Thank you all for your input. To sum it up: >> >> Altera and Xilinx are indeed the major brands to look at. Lattice has >> some nice stuff, but is smaller and does not support VHDL (at least >> not in the low-end tools). > > Are you sure ? > > The web page states this : > [Supported HDL languages include; VHDL, Verilog 1995, Verilog 2001.] > > and they release the Mico8/Mico32 in both Verilog and VHDL. You are right the ispLever tools do include VHDL. I somehow missed that, sorry for the mis-information there. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122364
Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com> writes: > I have a placed and routed .ncd file and I'd like to be able to > convert it back to a simple netlist. You can convert it to a verilog netlist with netgen, here's from one of my older Makefiles: netgen -sim -aka -dir . -ofmt verilog -pcf $(CHIP).pcf -sdf_anno true -sdf_path ../../impl/2vp20/xst-compiled -w $< $@ Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122365
In comp.arch.fpga, Peter Alfke <alfke@sbcglobal.net> wrote: > On Jul 25, 2:50 pm, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> > wrote: >> Thank you all for your input. To sum it up: >> >> Altera and Xilinx are indeed the major brands to look at. Lattice has >> some nice stuff, but is smaller and does not support VHDL (at least >> not in the low-end tools). >> >> There are no real advantages of one over the other (maybe there is for >> some specific designs). >> > This really irks me...."no real advantages"... > I will not get into a propaganda tirade, but rest assured that there > are significant technical differences between the two competitors. I > am of course biased, and much more familiar with the Xilinx devices > and their special advantages. And -as promised- I will not elaborate > them here My wording may be a little unflatering, but I think that it's true for low/medium-end designs. The real differences only show up when you want to get the most out of these devices. Thats why I added the specific designs exeption, there will be designs where it does matter. I started this thread by asking for the differences and got no replies that stated clear diffrences. From that I concluded that there's not much between them, and is this not true for simple(r) designs? > There are differences, for better or worse, between Obama and Clinton, > between the US and Canada, between BMW and Mercedes, between Apple and > Microsoft, and also between Xilinx and Altera. You may prefer one > brand over the other, but don't call it a toss-up! We worked hard to > make them different. I'm an Alfa Romeo adept myself, so BMW or Mercedes have no real differences between them (to me). > It is only when you ignore all the interesting and important fine > details that everything looks the same grey mush. The interesting and important stuff is mostly only required for high- end stuff. I need 10-40Mbps IO, not 3GBs, only a few kB of memory, some state machines that run in the 10-100MHz range, not rocket science. > "Once you have seen one lake or one mountain, you have seen then all. > California is just like Ohio with some mountains and beaches thrown > in!" > Nonsense! Not if you're only looking for a bit of water and some rocks, if you're interested in nice scenery then yes. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122366
Hello, Has anyone succeeded to do module based, dynamic partial reconfiguration in a Virtex4 Device with the ICAP? I am trying to load a Partial Bitstream with the OPB_HWICAP peripheral included in EDK 9.1 using the set_Configuration function. I can read out the status and configuration registers through the ICAP but if I try to reconfigure it seems that nothing happens - neither to the configruation and status registers nor to the FPGA logic - . Altough the set_configuration Function returns Success. Partial Reconfiguration works if I reconfigure the FPGA with Impact externaly. Could someone give me any hints, i can try to get partial reconfiguration with the ICAP working? Thanks in advance FabianArticle: 122367
Amontec, Larry wrote: > Amontec, Larry wrote: > >> Amontec, Larry wrote: >> >>> ON NEXT MONDAY : 17-JUNE-2006 >>> >>> Amontec will provide the ‘how-to’ program via a XILINX VIRTEX XC4VLX25 >>> 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! >>> >>> On next Monday, your Amontec JTAG key will be close to the speed of a >>> Xilinx Platform Cable USB for programming any FPGA and CPLD vendors >>> (Altera Xilinx Lattice Cypress ...) >>> >>> Come back next Monday on http://www.amontec.com ! >>> >>> Laurent >> >> >> >> Hi all, >> >> You may download the Amontec SVF Player from >> http://www.amontec.com/jtagkey.shtml >> >> Already tested for programming Altera Lattice Xilinx FPGA s CPLD s and >> FLASH s. >> It can be use for programming AVR ATMEGA processors too. >> But you may use it as custom JTAG Boundary Scan. >> >> Infini SCAN LENGTH ! >> Infini number of TAP (number of Targets) integrating Header and >> Trailer scans. >> >> The amtsvfplayer.exe comes with c project source. Also, you may edit >> the source, customize it and re-compile a new SVF Player for your >> specific needs. >> >> amtsvfplayer.exe -h to get help on usage. >> >> You may execute SVF Files or SVF Lines. >> A SVF Line could be a concatenation of SVF commands. >> >> You may adapt JTAG Frequency (FREQUENCY) via -frequencyFactor. In this >> way you do not need to edit the SVF yourself. When using >> -frequencyFactor, the RUNTEST x TCK is automaticaly updated ... >> >> Linux version ready to be published. >> >> HAVE FUN WITH JTAG AND SVF ! >> ... but you need to have the JTAGkey. >> >> Regards, >> Laurent >> http://www.amontec.com >> >> Ann: via JTAGkey, you have a lot of ARM Debug Solutions too, including >> OpenOCD JTAG server, Crossworks, Yagarto ... ! > > > Timing for small devices: > > Xilinx Coolrunner XCR3128 ERASE / PROGRAM / VERIFY -> > JTAG generation from SVF Player > SVF used : > http://www.amontec.com/chm_appl_test_led_blink_prog_check.svf > ... in 601 milliseconds > > ScreenShot : > http://www.amontec.com/jtagkey.shtml > > Regards, > Laurent We have tested with an big Altera EPC2S 16.9Mbits bitstream (SVF file) and the Amontec JTAG download it after a 4.4 seconds ! Laurent http://www.amontec.comArticle: 122368
> I've asked purchasing to get some indication qoutes of the low-end > devices, eval kits and tools from both. The Xilinx distributor got > back the next day, still waiting for Altera. :-( I would also try to evaluate the technical support that you'll receive. The FAE support I get from EBV here in the UK for Altera devices is second to none. Nial.Article: 122369
Stef wrote: > In comp.arch.fpga, > Jim Granville <no.spam@designtools.maps.co.nz> wrote: >> Stef wrote: >>> Thank you all for your input. To sum it up: >>> >>> Altera and Xilinx are indeed the major brands to look at. Lattice has >>> some nice stuff, but is smaller and does not support VHDL (at least >>> not in the low-end tools). >> Are you sure ? >> >> The web page states this : >> [Supported HDL languages include; VHDL, Verilog 1995, Verilog 2001.] >> >> and they release the Mico8/Mico32 in both Verilog and VHDL. > > You are right the ispLever tools do include VHDL. > I somehow missed that, sorry for the mis-information there. > Heard that with ispLever 7.0 they now also support mixed VHDL/Verilog design which Altera is doing it for years now (o; Can someone confirm on this? cheers rick From removethisthenleavejea@replacewithcompanyname.co.uk Thu Jul 26 04:11:41 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!news2.euro.net!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!despina.uk.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1185363521.107673.240850@x35g2000prf.googlegroups.com> <1185388542.212656.229920@o61g2000hsh.googlegroups.com> <1185414134.839241.218590@z24g2000prh.googlegroups.com> Subject: Re: PC104+ communication with FPGA using Xilinx IPCore Date: Thu, 26 Jul 2007 12:11:41 +0100 Lines: 33 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 2739008e1732c40028dab13e0e13e830623ba502353332a92c21316146a88181 NNTP-Posting-Date: Thu, 26 Jul 2007 12:12:01 +0100 Message-Id: <1185448321.73541.0@despina.uk.clara.net> Xref: prodigy.net comp.arch.fpga:134252 You will need something in your system that configures the PCI registers of each device. If you are using a motherboard host then usually that will do this configuration. Bus mastering, or initiator, function depends on whether your device supports the mode or not. Sometimes devices are slave (target) only which then then needs another device to do reading and writing of the target device. Signals like Frame# can be input, output, or both depending on the modes supported by any given device. If your 1394 chip supports initiator mode then it should be able to drive lines appropriately. The chip will still need it's PCI config registers set up by the overall master of the system. Hope that is clearer. John Adair Enterpoint Ltd. www.eneterpoint.co.uk "awa" <ameliaw.azman@gmail.com> wrote in message news:1185414134.839241.218590@z24g2000prh.googlegroups.com... > Hello John, > > Are you suggesting that the FPGA board should be the master instead of > target? In one of my discussion in other threads, someone suggested > that the link layer chip (PCI-to-1394 chip) should be set as master > (i.e. to continue asserting grant value). At this point, I'm getting > more confuse because I don't see how the other signals such as FRAME# > or IRDY# (that is initiator driven signal) will be produce by the link > layer chip. Could you help to clear this point? > > > From removethisthenleavejea@replacewithcompanyname.co.uk Thu Jul 26 04:15:44 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!ecngs!feeder2.ecngs.de!newsfeed.freenet.de!news2.euro.net!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!despina.uk.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <m3ps2haad5.fsf@donnybrook.brouhaha.com> <f85kha$cns$1@aioe.org> <m3k5sph24u.fsf@donnybrook.brouhaha.com> <1185389564.006825.47890@57g2000hsv.googlegroups.com> <46a79e6e$0$539$cc7c7865@news.luth.se> Subject: Re: tiny Spartan 3 module? Date: Thu, 26 Jul 2007 12:15:44 +0100 Lines: 26 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 300933100e2027920382160a6e94e38c26d51000332359427373218146a88272 NNTP-Posting-Date: Thu, 26 Jul 2007 12:16:02 +0100 Message-Id: <1185448562.73553.0@despina.uk.clara.net> Xref: prodigy.net comp.arch.fpga:134251 At the moment our shop will let you buy an item even if not in stock so we have held off putting them there. Once it is listed we don't tend to remove from the listing and just show zero stock. We are looking at ways to improve this and even to possibly to show expected delivery but it's not there yet. John Adair Enterpoint Ltd. www.enterpoint.co.uk <pbFJKD@ludd.invalid> wrote in message news:46a79e6e$0$539$cc7c7865@news.luth.se... > John Adair <g1@enterpoint.co.uk> wrote: >>Eric > >>The shop will show these modules when the new batch comes in shortly >>and we have stock built and tested. The first batch were sold out >>before we could put it up on the shop. The shop website is undergoing >>a major overhaul currently and a few things will be tidyed up. > > Could you not just list everything, and simple put a note "out of stock" > instead ..?, otherwise one is lead to think that you simple just don't > have it at all. > >Article: 122370
In comp.arch.fpga, Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: >> I've asked purchasing to get some indication qoutes of the low-end >> devices, eval kits and tools from both. The Xilinx distributor got >> back the next day, still waiting for Altera. :-( Just for the record: That delay was some miscommunication. > I would also try to evaluate the technical support that you'll > receive. If possible, yes. But evaluating support is not the easiest job. ;-) > The FAE support I get from EBV here in the UK for Altera devices > is second to none. I've already talked to an Altera FAE and he seemded OK. The real test is ofcourse supporting real design problems/questions. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122371
Hi all I am trying to program the Vertex 4 FPGA (XC4VFX100) in the slave serial mode using a PIC. I am facing a problem while doing the programming. when I am sending the first configuration bit on the din pin of the FPGA , the prog_b & the init_b pins which were otherwise high are going low. can anybody suggest me about the problem and any solution for this. thanks & regards archanaArticle: 122372
On Jul 25, 10:19 pm, Siva Velusamy <siva.velus...@xilinx.com> wrote:
> bob.zi...@gmail.com wrote:
> > Gang
>
> > I created a half dozen example projects using ISE 8.2i and the
> > PicoBlaze on my S3-1600 Dev Board. I'm really comfortable with asm
> > programming so the lack of a C compiler was no big deal.
> > I am running under Windows XP SP2 on a dual cpu P6 @ 1.8GHz and 2GB of
> > RAM.
>
> > Now I have started using the XPS 8.2i with ISE 8.2i so that I can do
> > some MicroBlaze programming in C. I am creating some very simple
> > hardware systems that consist of the CPU, a uart and some RAM. When I
> > click the button to build the hardware bit stream it is taking 14
> > minutes to run.
> > When I compile my C code it takes about 45 seconds to compile and then
> > merge the ELF file with the hardware bit stream.
>
> > This 14 minute hw build time is totally unreasonable. I find myself
> > not willing to experiment with changes to the hardware because the
> > associated build times.
>
> > Am I doing something wrong? The entire hw and sw system is supposed to
> > be based on MAKE files that only reprocess a file that has changed.
> > The XPS environment depends on the ISE environment to create the hw
> > bitstream. My initial ISE/PicoBlaze experiences were very nice (i.e.
> > synthesis, map, place & route, etc were fast).
>
> > Is there a way to describe my MicroBlaze design without using the XPS?
> > or am I crazy for thinking
> > this way?
>
> > Any help would be appreciated.
>
> > Bob
>
> Hi Bob -
>
> Could you post the map report (# of luts, # of brams) of the two
> systems? I suspect the Picoblaze system is vastly smaller. 14 minutes to
> run through synthesis, map and par seems quite reasonable, actually
> incredibly fast to me.
>
> As far as software changes go, I'd suggest that instead of initializing
> the bitstream with your ELF, just use XMD to download it. This way it
> takes only the time it takes for gcc.
>
> -Siva
Another way I save a LOT of time is by not using EDK (the gui that
is :).
Using a X/Cygwin shell and make you can perform all the operations
that EDK can but without the overhead of a large Eclipse-based gui
running in the background. I do not have data to backup it running
faster, but at least it feels that way to me.
To use the command line only, some of the commands you will want to
learn are:
"xps -nw system.xmp" - This will launch EDK in command line mode. From
here some important commands are:
"save make" - this will update (if necessary) the make files
which are generated based upon the content of of your .mhs and .mss
files.
"make -f system.make netlist" - This will perform synthesis on your
EDK project.
"make -f system.make download" - This will generate the bitstream that
can be downloaded with iMPACT, as well as perform the download to your
board. You will need to ensure that etc/download.cmd in your project
directory contains the proper commands to download to your board if
you wish to use this method. This step will also perform synthesis if
the netlist does not exist.
"make -f system.make program" - This will compile all software for
your system. If the system libraries need to be generated/built this
will occur also.
If you don't set your application to initialize BRAM, then you can
save time by just having to download the software as you are debugging
it. Re-downloading the bitstream takes only a few seconds compared to
re-initializing BRAM and then downloading. If your software does not
harm the state of hardware (i.e. you can re-run the software with the
same expected results over and over again), then all you will need to
do is download your software w/ XMD:
1) "xmd"
2) "connect mb <whatever method you're using. I recommend the MDM>"
3) "download <elf file>"
HTH,
Mike
Article: 122373On Jul 25, 7:35 pm, PFC <li...@peufeu.com> wrote: > On Wed, 25 Jul 2007 21:35:39 +0200, John Oyler <john.m.oy...@gmail.com> > wrote: > > > I don't know that my fpga is capable (spartan 3e 100k), but I thought > > I might like to try to do ethernet first. I remember finding a > > tutorial weeks ago but forgot to bookmark it, where the instructions > > had you hook up two io pins directly to an ethernet cable, and you > > could hardcode an IP address into the chip and ping it. Does anyone > > know of any like this, or even of the one I speak? (Might even have > > been verilog, I forget). > > Tutorial is there. > http://www.fpga4fun.com/10BASE-T0.html > > > Also, at the risk of sounding stupid, can an fpga hook up directly to > > ethernet? > > 10 Mbps, maybe, if you violate most of the ethernet spec ;) > You'll most likely get a toy system, though. > > > Supposing it is clocked at the right speed, the only > > consideration is the voltage of utp/ethernet, right? What other sort > > of hardware would I need to make all that work? Is it anything I can > > salvage off an old nic? > > If you just want to play and learn stuff, you could try putting in an > Ethernet PHY. You won't be able to use anything from an old LAN board as > those all use highly integrated PCI chipsets (unless very, very old). > Or you could download the Ethernet MAC core at OpenCores.org and have a > look. > > If you just want to send a few packets for messaging, though, and not > high throughput data, an ethernet enabled microcontroller is a much better > bet. > > I have an Ethernet + FPGA module in the works ; I have selected a > complete and easy to use MAC+PHY chip from SMSC, the LAN9117. Thank you, that's the url I was looking for... I would have settled for another tutorial similar to it. As for it being a toy system, that's fine. It will just be on my development board here, something to learn with. Eventually, I'd like to do a nice ethernet implementation suitable for an old 8-bit expansion bus. But that's for later. Thanks agian, JohnArticle: 122374
On Jul 26, 1:42 am, swamy_digital <swam...@gmail.com> wrote: > Hello Group Members > > I am trying to build a simple system consisting of PowerPC405, JTAG, > UART, OPB DDR controller, and 16MB External DDR memory on a HiTech PPC > board. No on-chip BRAMs. I use EDK 9.1/ISE9.1 versions. > > If I try to launch XMD from EDK GUI, it prints messages detecting the > programming cable and quits without printing any error messages. > > I tried invoking XMD from cygwin shell and used the command ' connect > ppc hw', it detects the JTAG chain, prints the ID code and then quits > printing 'ERROR(0):'. I have no idea what might be wrong here. > > Any help is very much appreciated. > > Interestingly, If I use only on-chip BRAM and no external memory, i > can print messages to UART by downloading code through XMD. > > Thanks > swamy I had an issue where I could not download w/ 9.1 but could w/ no problems under 8.2. It seemed that the xmd.ini file was (or wasn't) setting up some addresses properly. You may want to check the contents of your xmd.ini file (if it exists) and make sure that everything makes sense. It sounds like the xmd.ini file probably has some addressing setup to access the BRAM from your other project and since you don't have BRAM in the current project its becoming unhappy when it tries to setup/access something. -- Mike
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