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Messages from 122575

Article: 122575
Subject: regarding RTOS in NIOS II
From: sriman <srimankk@gmail.com>
Date: Tue, 31 Jul 2007 17:57:20 -0000
Links: << >>  << T >>  << A >>
hi everyone

    i am trying to use RTOS in NIOS processor. After going through its
documentation i found that UC/OS2 and UClinux are the two versions
avaliable. I am interfacing my design to a Ethernet. i am using a DE2
board. i found that UClinux has got native TCP/IP protocols that wil
help in easy interfacing of the WLAN module which i am using.
  But the problem what i am facing is i dont have a license in linux
version software. i have it for windows. also according what i read in
documentations UClinux can be used only in Linux platform.
  So what shall i do now. Is programming in US/OS2 the only
alternative. or can i do somethin so that i can program the uclinux in
linux and migrate it onto a windows sytem and use it in my design


Article: 122576
Subject: Re: ASIC Digital Design Blog
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 31 Jul 2007 11:17:12 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 7:19 am, Nir Dahan <write2...@googlemail.com> wrote:
> Hi All,
>
> Please allow me to shamelessly plug my blog. It is relatively new (2-3
> months old) and just passed the 5000 views mark.
> I am blogging about a lot of topics that might interest people here.
>
> visit me at:http://asicdigitaldesign.wordpress.com
>
> Thanks,
>
> Nir

Hi Nir,
It is excellently written in your blog. I like it very much.

Thank you for sharing your experiences with us.

Weng


Article: 122577
Subject: Re: DDR Simulation Model
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 31 Jul 2007 11:30:00 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 6:34 am, s...@hrz.tu-chemnitz.de wrote:
> During my work with the XUP development board another problem occured
> when I tried to use the on-board DDR-SDRAM. A data stream is written
> into the RAM using the PLB bus and burst mode (16 x 64 bit). When I
> read the data from the RAM using the Power PC after some time an error
> occurs. It looks like one 64 bit word has not been written into the
> RAM (or it has been overwritten - I am not sure about this).
> When I use the Block RAM of the Virtex-II Pro instead everything is
> fine. I do not change anything but the address. Same protocol is used
> for both RAMs.
>
> My problem is that I do not have a simulation model for the DDR RAM.
> It is a Kingston KVR266X64C25/256. All I can do during simulation is
> to look what the PLB DDR controller is writing to the output pins. And
> the simulation does not show any wrong behavior at this point. I can
> not perform any read accesses since there is no RAM model atttached.
> So currently for tests the only way is to use the real board but here
> I can not see, what is happening.
> Does anybody know, where I can get a simulation model for this RAM? I
> have searched the Kingston page. I have sent them an E-Mail (still
> waiting for response). I have tried Google but I could not find
> anything. Same here.
> Thanks in advance
>
> Sebastian Goller

Hi S,
When you write data into Block RAM of Xilinx FPGA, you provide address
and data in the same clock. When reading, first clock is to provide
address, then reading its data from data bus on second clock due to
one clock delay of Block RAM.

DDR RAM is totally different from Block RAM of Xilinx. It has some
defined bus activities to get data written or read. You cannot
directly read or write by PowerPC. There must be some logic between
them to access approprite data.

You must read its manual carefully and understand its read and write
rules that is at least 20 full pages long.

Weng



Article: 122578
Subject: Re: Looking for PLD with embedded memory
From: Eric Smith <eric@brouhaha.com>
Date: Tue, 31 Jul 2007 11:43:23 -0700
Links: << >>  << T >>  << A >>
Philipp Klaus Krause <pkk@spth.de> writes:
> I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated
> memory that can be used as ROM and ~64Kb of integrated memory that can
> be used as EEPROM.

You're going to be looking for a long time.

You can get that much RAM, but not in a part with 5V tolerant I/O.

You can get built-in flash memory, but not EEPROM.

I suspect that you just need to use a 3.3V part with appropriate level
shifters or QuickSwitch parts (or equivalent) to get your 5V tolerance
(or possibly just series resistors), and a separate EEPROM chip.

Article: 122579
Subject: Re: Upgrading from EDK 8.1 to EDK 9.1i
From: Eric Smith <eric@brouhaha.com>
Date: Tue, 31 Jul 2007 11:46:06 -0700
Links: << >>  << T >>  << A >>
bob.zigon@gmail.com writes:
> I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a
> copy of the the EDK 8.1 and uses ISE 8.1 Webpack.
[...]
> 2. Do I have to purchase the 9.1 EDK?

Not if you're still in the one year support period for your purchase
of the EDK 8.1 in the development kit.

Article: 122580
Subject: Re: ASIC Digital Design Blog
From: Nir Dahan <write2nir@googlemail.com>
Date: Tue, 31 Jul 2007 12:17:23 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 8:17 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Jul 31, 7:19 am, Nir Dahan <write2...@googlemail.com> wrote:
>
> > Hi All,
>
> > Please allow me to shamelessly plug my blog. It is relatively new (2-3
> > months old) and just passed the 5000 views mark.
> > I am blogging about a lot of topics that might interest people here.
>
> > visit me at:http://asicdigitaldesign.wordpress.com
>
> > Thanks,
>
> > Nir
>
> Hi Nir,
> It is excellently written in your blog. I like it very much.
>
> Thank you for sharing your experiences with us.
>
> Weng

Weng,

thanks for the kind words, if you have any ideas/suggestions/complains
feel free to email me.
I also keep a list of interview questions and puzzles which are
related to our craft. There is always at least one puzzle or challenge
which is open.

check it out

Nir


Article: 122581
Subject: Re: Looking for PLD with embedded memory
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 01 Aug 2007 07:38:09 +1200
Links: << >>  << T >>  << A >>
Philipp Klaus Krause wrote:
> Jim Granville schrieb:
> 
>>>The device doesn't have to be fast, 8 Mhz for a simple design would be
>>>OK. I need about 40 I/O.
>>
>>What does this connect to ? - ie where does this ROM code go ?
>>Is there a processor in the system, reading this, or something else ?
> 
> 
> It goes into a Z80-based system from the 80s. The system has a cartridge
> port, where D0...D7 (data), A0...A14 (addres bus, A15 missing), E8...EE
> (chip enable). Back in the 80s a cartridge would contain one to four 64
> KBit EPROMS containing a program. Each enable line would be used as a
> chip enable.
> I've written a few programs for the system. So far each did fit into
> 32KB, so I used a 256 KBit EPROM together with a 74LS21 (to connect the
> four chip enable lines to the EPROM's output and chip enable) for my
> cartridges.
> Now I'd like to write a program that uses more ROM and I'd like to be
> able to save some data. I think dividing the address space into lower
> 24KB (directly mapped as before) middle 4KB (bank-switched), upper 4KB
> (to locate some control registers to switch the middle 4KB and control
> the IC line to the EEPROM) would make sense.

Have you looked at FLASH rather than EPROM ?
Then you might be able to dispense with the EEPROM.
If you use a small CPLD (XC9536, or ATF1502ASL ) you will
be able to do all the chip select/banking/mapping you need,
as well as get a phantom write path for the Flash.

-jg



Article: 122582
Subject: Re: verilog parser question about `defines
From: raphfrk <raphfrk@netscape.net>
Date: Tue, 31 Jul 2007 12:41:05 -0700
Links: << >>  << T >>  << A >>
On Jul 26, 2:41 pm, Gabor <ga...@alacron.com> wrote:
> You can also add macros in the GUI under synthesis options
> (Advanced) "Verilog Macros".  Use the same format for
> definitions.  Use a vertical bar to separate multiple entries.

Thanks


Article: 122583
Subject: Xilinx Webpack 9.2 and Windows 2000 Pro?
From: "Ioiod" <aks@tht.com>
Date: Wed, 01 Aug 2007 04:14:59 GMT
Links: << >>  << T >>  << A >>
On Xilinx's website, Webpack product-description no longer lists
Windows 2000 as a supported O/S.  I'm currently using Webpack 9.1i.03 on
a Windows 2000 machiine.

Will I have problems if I try to upgrade to Webpack 9.2? 



Article: 122584
Subject: Re: Best CPU platform(s) for FPGA synthesis
From: "Ioiod" <aks@tht.com>
Date: Wed, 01 Aug 2007 04:29:06 GMT
Links: << >>  << T >>  << A >>

<sharp@cadence.com> wrote in message 
news:1185490882.415577.205710@b79g2000hse.googlegroups.com...
> On Jul 26, 6:19 pm, jjohn...@cs.ucf.edu wrote:
>> Is Quartus (and the others) more efficient in any one particular
>> environment? I prefer Linux, but the OS is now secondary to pure
>> runtime performance (unless it is a major contributor). Can any of
>> them make use of more than 2GB or RAM? More than 4GB?
>
> 64-bit Linux can make use of more than 4GB of RAM.  But don't use 64-
> bit executables unless your design is too big for 32-bit tools,
> because they will run slower on the same machine.

Interesting -- on an AMD Athlon X2/5200+ running RHEL Linux 4 update 4 
x86_64,
just about all Synopsys Design Compiler jobs run FASTER in 64-bit mode than
32-bit mode, between 5-10% faster.  THe penalty is slightly larger 
RAM-footprint,
just as you noted.  The X2/5200+ is spec'd the same as an Opteron 1218 
(2.6GHz,
2x1MB L2 cache..)

This trend was pretty much consistent across all our Linux EDA-tools.

On Solaris SPARC, 64-bit mode was definitely slower than 32-bit mode, by 
about
10-20%.  For the life of me, I can't understand why the AMD would run 64-bit
mode faster than its 32-bit mode -- but for every other machine 
architecture,
64-bit mode is almost always slower.

I forgot to re-run my 32bit vs 64-bit benchmark on Intel Core2 Duo machines.
FOr 64-bit, the Intel E6850 (4MB L2 cache, 3.0GHz) ran anywhere
from 50-60% faster than the AMD X2/5200+.  Don't worry, no production 
machines
were overclocked (for obvious official, sign/off reasons.)  It was just a 
admin's
corner cubicle experiment.

> Most of these tools are not multi-threaded, so the only way you will
> get a speedup is if you have multiple jobs at the same time.  Event-
> driven simulation in particular is not amenable to multi-threading,
> despite much wishful thinking for the last few decades.

When I ran two separate (unrelated) jobs simultaneously on the AMD and Intel
machines, the AMD machine handled dual-tasking much better.  AMD only
dropped 5-7%, for each job.  The E6600 fared a lot worse -- anywhere from
10-30% performance drop.  (Though not as bad as the Pentium/3 and
Pentium/4 based Xeons.)

I'm wondering if the E6600's unified 4MB L2-cache thrashes badly in 
dual-tasking.
Or maybe the better way to look at it, in single-tasking the 4MB L2-cache is
4X more than the AMD Opteron's 1MB cache per CPU-core.



Article: 122585
Subject: Re: Best CPU platform(s) for FPGA synthesis
From: "Ioiod" <aks@tht.com>
Date: Wed, 01 Aug 2007 04:30:16 GMT
Links: << >>  << T >>  << A >>

"Eric Smith" <eric@brouhaha.com> wrote in message 
news:m33az9ztja.fsf@donnybrook.brouhaha.com...
> sharp@cadence.com writes:
>> 64-bit Linux can make use of more than 4GB of RAM.  But don't use 64-
>> bit executables unless your design is too big for 32-bit tools,
>> because they will run slower on the same machine.
>
> Although that might be true for some specific cases, in general on Linux
> native 64-bit executables tend to run faster than 32-bit executables.
> But I haven't benchmarked 32-bit vs. 64-bit FPGA tools.

I think that should be qualified to say 64-bit x86_64 Linux binaries run 
faster than
the same binaries compiled for 32-bit x86 Linux.

For other CPU-architectures (MIPs, SPARC, PowerPC, etc.), the opposite is
generally true. 



Article: 122586
Subject: Altera Cyclone II and Cyclone III "distributed" RAM?
From: "Ioiod" <aks@tht.com>
Date: Wed, 01 Aug 2007 04:37:13 GMT
Links: << >>  << T >>  << A >>
I looked on Altera's website, but I could not find any description on how
distributed (LUT-based) RAM works on the CYclone II/III family.

FOr the Stratix III, I see Altera called this feature "M-LAB."  Am I
missing something obvious?  Or do the Cyclone family simply not
supported distributed RAM? 



Article: 122587
Subject: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
From: Ben Twijnstra <ben.twijnstra@gmail.com>
Date: Wed, 01 Aug 2007 07:31:56 +0200
Links: << >>  << T >>  << A >>
Ioiod wrote:

> I looked on Altera's website, but I could not find any description on how
> distributed (LUT-based) RAM works on the CYclone II/III family.
> 
> FOr the Stratix III, I see Altera called this feature "M-LAB."  Am I
> missing something obvious?  Or do the Cyclone family simply not
> supported distributed RAM?

Nope, Altera doesn't support distributed RAM in the Cyclone series. Then
again, the Cyclone III has a _lot_ of block RAM.

Best regards,


Ben


Article: 122588
Subject: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Tue, 31 Jul 2007 22:35:09 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 9:37 pm, "Ioiod" <a...@tht.com> wrote:
> I looked on Altera's website, but I could not find any description on how
> distributed (LUT-based) RAM works on the CYclone II/III family.

LUT-based RAM is a Xilinx specific thing that I'm sure is heavily
protected.

Cyclone I and II only have M4K as hard blocks, though you can use it
as two one-port memories. For tiny RAMs making them out of LEs.
Cyclone III is the same except the blocks are twice as big (M9K).

> FOr the Stratix III, I see Altera called this feature "M-LAB."

MLAB are one of three different kinds of hard memory blocks. They are
not LUT RAM.

> Am I
> missing something obvious?  Or do the Cyclone family simply not
> supported distributed RAM?

They do not support Xilinx style LUT RAM, no.

I'm not saying that LUT RAM aren't useful, but they do not come for
free and it's all about the tradeoffs.

Not speaking for or associated with Altera.

Tommy


Article: 122589
Subject: Re: Xilinx/ModelSim bug ? Clocking headache ...
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Wed, 01 Aug 2007 09:41:54 +0200
Links: << >>  << T >>  << A >>
> It's a standard source of unexpected behaviour in zero-delay 
> VHDL models, and one of the very few reasons why I sometimes
> prefer Verilog for behavioural modelling - you can do zero-delay
> combinational signal assignment in Verilog.

I wish that too now ...

> I don't understand what's going on in your Xilinx models.  I
> can't believe they put out code that doesn't work with
> zero delays. 

But they did ...

Here's a test case : http://pastebin.com/m71704926
And the simulation output :
 http://www.246tnt.com/files/bram_write.png
 http://www.246tnt.com/files/bram_read.png

Basically cnt, cnt_d1, cnt_d2 and cnt_d3 are connected to the 
BRAM Data In. And they are assignement one of another :

cnt_d1 <= cnt;
cnt_d2 <= cnt_d1;
cnt_d3 <= cnt_d3;

So when we write at address 1DC0 the value 12121212 with wren = 1100,
we expect it to store 12120000 ... but when you look at the read
result (the output register is active so there's 2 clock delay),
we get ... 13120000 ... 



> You can be fairly sure it will work correctly 
> when all the non-zero (post place-and-route) delays are 
> backannotated into it.

Yes sure that will work. And all their models have a 
100 ps delay output btw .. so that post synthesis simulation
work OK.


> If you're desperate, introduce a tiny non-zero delay in all
> input signals except the clock, by copying them with a delay:
> 
>   port_signal <= input_signal after 1 ns;
> 
> But that sucks, doesn't it?

Yes that sucks _big_time_



    Sylvain

Article: 122590
Subject: Re: ASIC Digital Design Blog
From: michel.talon@gmail.com
Date: Wed, 01 Aug 2007 00:55:08 -0700
Links: << >>  << T >>  << A >>
Hi,

I read all your post, and I found a lot of interesting tricks!

thank you very much for this blog, I hope you will continue to update
it.

Best regards, Michel.


On 31 juil, 16:19, Nir Dahan <write2...@googlemail.com> wrote:
> Hi All,
>
> Please allow me to shamelessly plug my blog. It is relatively new (2-3
> months old) and just passed the 5000 views mark.
> I am blogging about a lot of topics that might interest people here.
>
> visit me at:http://asicdigitaldesign.wordpress.com
>
> Thanks,
>
> Nir



Article: 122591
Subject: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
From: Dolphin <Karel.Deprez@gemidis.be>
Date: Wed, 01 Aug 2007 01:12:38 -0700
Links: << >>  << T >>  << A >>
Hello,

We have implemented a variable phase shift in a spartan 3E device. The
phase shift can be set with a register. Normally the PSDONE signal
should go high when a phase shift is performed. This happens but takes
a long time (several minutes). The datasheet says :

"The phase adjustment might require as many as 100 CLKIN
cycles plus 3 PSCLK cycles to take effect, at which point the
DCM's PSDONE output goes High for one PSCLK cycle.
This pulse indicates that the PS unit completed"

However it seems that our design is much slower...
The DCM that does the phase shift gets its clock from another DCM.
Could it be that there is too much jitter on this clock?

Anybody had a similar problem?

Thanks and best regards,
Karel Deprez


Article: 122592
Subject: Re: DDR Simulation Model
From: Sebastian Goller <sego@hrz.tu-chemnitz.de>
Date: Wed, 01 Aug 2007 01:18:16 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 4:54 pm, "B. Joshua Rosen"
<bjro...@polybusPleaseDontSpamMe.com> wrote:
> On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote:
> > During my work with the XUP development board another problem occured
> > when I tried to use the on-board DDR-SDRAM. A data stream is written
> > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read
> > the data from the RAM using the Power PC after some time an error
> > occurs. It looks like one 64 bit word has not been written into the RAM
> > (or it has been overwritten - I am not sure about this). When I use the
> > Block RAM of the Virtex-II Pro instead everything is fine. I do not
> > change anything but the address. Same protocol is used for both RAMs.
>
> > My problem is that I do not have a simulation model for the DDR RAM. It
> > is a Kingston KVR266X64C25/256. All I can do during simulation is to
> > look what the PLB DDR controller is writing to the output pins. And the
> > simulation does not show any wrong behavior at this point. I can not
> > perform any read accesses since there is no RAM model atttached. So
> > currently for tests the only way is to use the real board but here I can
> > not see, what is happening.
> > Does anybody know, where I can get a simulation model for this RAM? I
> > have searched the Kingston page. I have sent them an E-Mail (still
> > waiting for response). I have tried Google but I could not find
> > anything. Same here.
> > Thanks in advance
>
> > Sebastian Goller
>
> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's
> website.

Thanks for your answer. I have taken a look at http://www.micron.com
(Design Support etc.) The problem is that I can not find a module that
has the specifications of the RAM I use in my design.
The KVR2666X64C25//256 has the following specs (according to the data
sheet):

- 256MB 32M x 64-Bit
- DDR266
- CL2.5
- 184-Pin DIMM

There is no module on Micron's site that has these specs. Every DDR266-
Module has a CL2.0. I can only choose between pin count 66 and 66-
ball. A depth of 256 MB is not available for DDR266.
I have looked at my design. There are 106 pins used for the interface
between the PLB DDR controller and the RAM module. So a pin count of
66 does not seem useful to me.
I am sorry if ask very stupid questions, but it is the first time I
use DDR SDRAM.


Article: 122593
Subject: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
From: "HT-Lab" <hans64@ht-lab.com>
Date: Wed, 01 Aug 2007 08:24:10 GMT
Links: << >>  << T >>  << A >>

"Ioiod" <aks@tht.com> wrote in message 
news:7NTri.12212$eY.8991@newssvr13.news.prodigy.net...
> On Xilinx's website, Webpack product-description no longer lists
> Windows 2000 as a supported O/S.  I'm currently using Webpack 9.1i.03 on
> a Windows 2000 machiine.
>
> Will I have problems if I try to upgrade to Webpack 9.2?

Not sure if it helps but the full ISE 9.2.01i seems to be running fine on my 
win2k machine. I also checked the supported OS of ISE92 and indeed win2k is 
no longer listed :-(

Hans
www.ht-lab.com


> 



Article: 122594
Subject: Re: DDR Simulation Model
From: Sebastian Goller <sego@hrz.tu-chemnitz.de>
Date: Wed, 01 Aug 2007 01:29:13 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 8:30 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Jul 31, 6:34 am, s...@hrz.tu-chemnitz.de wrote:
>
>
>
> > During my work with the XUP development board another problem occured
> > when I tried to use the on-board DDR-SDRAM. A data stream is written
> > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I
> > read the data from the RAM using the Power PC after some time an error
> > occurs. It looks like one 64 bit word has not been written into the
> > RAM (or it has been overwritten - I am not sure about this).
> > When I use the Block RAM of the Virtex-II Pro instead everything is
> > fine. I do not change anything but the address. Same protocol is used
> > for both RAMs.
>
> > My problem is that I do not have a simulation model for the DDR RAM.
> > It is a Kingston KVR266X64C25/256. All I can do during simulation is
> > to look what the PLB DDR controller is writing to the output pins. And
> > the simulation does not show any wrong behavior at this point. I can
> > not perform any read accesses since there is no RAM model atttached.
> > So currently for tests the only way is to use the real board but here
> > I can not see, what is happening.
> > Does anybody know, where I can get a simulation model for this RAM? I
> > have searched the Kingston page. I have sent them an E-Mail (still
> > waiting for response). I have tried Google but I could not find
> > anything. Same here.
> > Thanks in advance
>
> > Sebastian Goller
>
> Hi S,
> When you write data into Block RAM of Xilinx FPGA, you provide address
> and data in the same clock. When reading, first clock is to provide
> address, then reading its data from data bus on second clock due to
> one clock delay of Block RAM.
>
> DDR RAM is totally different from Block RAM of Xilinx. It has some
> defined bus activities to get data written or read. You cannot
> directly read or write by PowerPC. There must be some logic between
> them to access approprite data.
>
> You must read its manual carefully and understand its read and write
> rules that is at least 20 full pages long.
>
> Weng

Hi Tianxiang,

thanks for your answer. There is a DDR controller in my design. All
components are connected via PLB bus. So everything I have to do is to
use the PLB protocol. The controller will handle the rest.
What I do not understand is that some data is written and read
correctly. There is only one 64 bit word which is missing. The PowerPC
starts reading at the base address of the DDR RAM (0x00000000). I use
a simple pointer PMEM and assign the value in PMEM to another
variable. After the data has been read from the RAM PMEM is increased
by 4 (32 bit data width). This works until PMEM is 1152. Then the
error occurs. After this error everthing looks fine again.


Article: 122595
Subject: Re: DDR Simulation Model
From: Sebastian Goller <sego@hrz.tu-chemnitz.de>
Date: Wed, 01 Aug 2007 02:35:12 -0700
Links: << >>  << T >>  << A >>
On Jul 31, 4:54 pm, "B. Joshua Rosen"
<bjro...@polybusPleaseDontSpamMe.com> wrote:
> On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote:
> > During my work with the XUP development board another problem occured
> > when I tried to use the on-board DDR-SDRAM. A data stream is written
> > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read
> > the data from the RAM using the Power PC after some time an error
> > occurs. It looks like one 64 bit word has not been written into the RAM
> > (or it has been overwritten - I am not sure about this). When I use the
> > Block RAM of the Virtex-II Pro instead everything is fine. I do not
> > change anything but the address. Same protocol is used for both RAMs.
>
> > My problem is that I do not have a simulation model for the DDR RAM. It
> > is a Kingston KVR266X64C25/256. All I can do during simulation is to
> > look what the PLB DDR controller is writing to the output pins. And the
> > simulation does not show any wrong behavior at this point. I can not
> > perform any read accesses since there is no RAM model atttached. So
> > currently for tests the only way is to use the real board but here I can
> > not see, what is happening.
> > Does anybody know, where I can get a simulation model for this RAM? I
> > have searched the Kingston page. I have sent them an E-Mail (still
> > waiting for response). I have tried Google but I could not find
> > anything. Same here.
> > Thanks in advance
>
> > Sebastian Goller
>
> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's
> website.

I have taken a look at the RAM Module. There is some more information
on the RAM chips:

0516      1-1
MT         46V32M8
TG         -5B G

What does this mean and how can I use it to find the correct
simulation model?



Article: 122596
Subject: Fatal Error ISE 9.1
From: martin.leibetseder@ge.com
Date: Wed, 01 Aug 2007 02:54:57 -0700
Links: << >>  << T >>  << A >>
hi,

i get this message when i run "map".

Using target part "5vlx30ff324-3".
Mapping design into LUTs...
Running directed packing...
Constraining slice packing based on guide NCD.
Running delay-based LUT packing...
FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of
library
   <C:/Program Files/Xilinx_ISE_9_1i/xilinx/bin/nt/
libPlXil_DesCheck.dll> failed
   due to an unknown reason.   Process will terminate. For more
information on
   this error, please consult the Answers Database or open a WebCase
with this
   project attached at http://www.xilinx.com/support.

Process "Map" failed


Could somebody help me?


Article: 122597
Subject: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
From: acher@in.tum.de (Georg Acher)
Date: Wed, 1 Aug 2007 10:11:42 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dolphin <Karel.Deprez@gemidis.be> writes:
>Hello,
>
>We have implemented a variable phase shift in a spartan 3E device. The
>phase shift can be set with a register. Normally the PSDONE signal
>should go high when a phase shift is performed. This happens but takes
>a long time (several minutes). The datasheet says :
>
>"The phase adjustment might require as many as 100 CLKIN
>cycles plus 3 PSCLK cycles to take effect, at which point the
>DCM's PSDONE output goes High for one PSCLK cycle.
>This pulse indicates that the PS unit completed"
>
>However it seems that our design is much slower...
>The DCM that does the phase shift gets its clock from another DCM.
>Could it be that there is too much jitter on this clock?
>
>Anybody had a similar problem?

Are you on the phase shift limits? Then it takes almost forever, and 3E has no
status pin for the limit detection... 
-- 
         Georg Acher, acher@in.tum.de
         http://www.lrr.in.tum.de/~acher
         "Oh no, not again !" The bowl of petunias

Article: 122598
Subject: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
From: Dolphin <Karel.Deprez@gemidis.be>
Date: Wed, 01 Aug 2007 03:34:34 -0700
Links: << >>  << T >>  << A >>
On 1 aug, 12:11, ac...@in.tum.de (Georg Acher) wrote:
> Dolphin <Karel.Dep...@gemidis.be> writes:
> >Hello,
>
> >We have implemented a variable phase shift in a spartan 3E device. The
> >phase shift can be set with a register. Normally the PSDONE signal
> >should go high when a phase shift is performed. This happens but takes
> >a long time (several minutes). The datasheet says :
>
> >"The phase adjustment might require as many as 100 CLKIN
> >cycles plus 3 PSCLK cycles to take effect, at which point the
> >DCM's PSDONE output goes High for one PSCLK cycle.
> >This pulse indicates that the PS unit completed"
>
> >However it seems that our design is much slower...
> >The DCM that does the phase shift gets its clock from another DCM.
> >Could it be that there is too much jitter on this clock?
>
> >Anybody had a similar problem?
>
> Are you on the phase shift limits? Then it takes almost forever, and 3E has no
> status pin for the limit detection...
> --
>          Georg Acher, ac...@in.tum.de
>          http://www.lrr.in.tum.de/~acher
>          "Oh no, not again !" The bowl of petunias

Hello Georg,
The input clock is 115MHz (=8.7ns). This allows for a maximum of
20*(8.7-3) = 114steps. We are only doing 100 steps...

Thanks for the information,
Karel


Article: 122599
Subject: Re: DDR Simulation Model
From: PFC <lists@peufeu.com>
Date: Wed, 01 Aug 2007 13:15:32 +0200
Links: << >>  << T >>  << A >>


> Thanks for your answer. I have taken a look at http://www.micron.com
> (Design Support etc.) The problem is that I can not find a module that
> has the specifications of the RAM I use in my design.
> The KVR2666X64C25//256 has the following specs (according to the data
> sheet):
>
> - 256MB 32M x 64-Bit
> - DDR266
> - CL2.5
> - 184-Pin DIMM

	Well :

	TYpe KVR266X64C25 in Google
	Get the spec sheet (first link)
	Count chips on module (result : 16 chips)
	So, it has 16x 32Mx4-bit chips making 32Mx64 bits

	Then, either get a module and look at what chips it actually uses, or :
	Go to Micron's site and search 32Mx4-bit, CL2.5 modules

	MT46V32M4P-75
	MT46V32M4TG-75

	Hint : those are DDR266B, not DDR266

> There is no module on Micron's site that has these specs. Every DDR266-

	That's because you got a Kingston module ;) not Micron

> Module has a CL2.0. I can only choose between pin count 66 and 66-
> ball. A depth of 256 MB is not available for DDR266.
> I have looked at my design. There are 106 pins used for the interface
> between the PLB DDR controller and the RAM module. So a pin count of
> 66 does not seem useful to me.

	That's because there are 16 chips on your Kingston, not 1.
	If you check the pinout of the 184-pin DDR module you'll notice that  
there are something like 106 useful pins, the rest is power supply and  
ground...

> I am sorry if ask very stupid questions, but it is the first time I
> use DDR SDRAM.

	Are you routing the PCB ?




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