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On 30 Jul., 16:19, austin <aus...@xilinx.com> wrote: > Antti, > > Again,I need to apologize for the website problems over the weekend. > > Please be patient. > > Austin eh, ok no problem - usually my search skills give me access anyway, so I actually was able to land on the target page I was looking for, and the empty page was back online within hours from my the time of my frustration. But yes, making the corporate "web front" 99.9% online and accessible without caveats should be a task on the desk of some at X ;) AnttiArticle: 122526
I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with it.(http:// www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=50). The problem i am facing is on the data sheet 20 pins are assigned to each sensor. i am a newibe to vlsi design. i am unable to distinguish the usage of al the pins. only understood a few. can anyone help me out by tellin whats the real functionalities of those pins i am attaching the pin descriptions with this post Pin Numbers Name Direction Description 1 DATA1[0] Output Sensor 1 Data Bit 0 2 DATA1[1] Output Sensor 1 Data Bit 1 3 DATA1[4] Output Sensor 1 Data Bit 4 4 DATA1[3] Output Sensor 1 Data Bit 3 5 DATA1[5] Output Sensor 1 Data Bit 5 6 DATA1[2] Output Sensor 1 Data Bit 2 7 DATA1[6] Output Sensor 1 Data Bit 6 8 DATA1[7] Output Sensor 1 Data Bit 7 9 DATA1[8] Output Sensor 1 Data Bit 8 10 DATA1[9] Output Sensor 1 Data Bit 9 11 NC N/A Not Connect 12 GND N/A Ground 13 PIXCLK1 Output Sensor 1 Pixel Clock 14 MCLK1 Input Sensor 1 Master Clock 15 LVAL1 Output Sensor 1 Line Valid 16 FVAL1 Output Sensor 1 Frame Valid 17 SCLK1 input Sensor 1 I2C Clock 18 SDATA1 I/O Sensor 1 I2C Data 19 N/C N/A Not Connect 20 N/C N/A Not ConnectArticle: 122527
I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with it.(http:// www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=50). The problem i am facing is on the data sheet 20 pins are assigned to each sensor. i am a newibe to vlsi design. i am unable to distinguish the usage of al the pins. only understood a few. can anyone help me out by tellin whats the real functionalities of those pins i am attaching the pin descriptions with this post Pin Numbers Name Direction Description 1 DATA1[0] Output Sensor 1 Data Bit 0 2 DATA1[1] Output Sensor 1 Data Bit 1 3 DATA1[4] Output Sensor 1 Data Bit 4 4 DATA1[3] Output Sensor 1 Data Bit 3 5 DATA1[5] Output Sensor 1 Data Bit 5 6 DATA1[2] Output Sensor 1 Data Bit 2 7 DATA1[6] Output Sensor 1 Data Bit 6 8 DATA1[7] Output Sensor 1 Data Bit 7 9 DATA1[8] Output Sensor 1 Data Bit 8 10 DATA1[9] Output Sensor 1 Data Bit 9 11 NC N/A Not Connect 12 GND N/A Ground 13 PIXCLK1 Output Sensor 1 Pixel Clock 14 MCLK1 Input Sensor 1 Master Clock 15 LVAL1 Output Sensor 1 Line Valid 16 FVAL1 Output Sensor 1 Frame Valid 17 SCLK1 input Sensor 1 I2C Clock 18 SDATA1 I/O Sensor 1 I2C Data 19 N/C N/A Not Connect 20 N/C N/A Not ConnectArticle: 122528
MM, I am asking the experts here. Will post their reply soon, AustinArticle: 122529
Philipp Klaus Krause <pkk@spth.de> writes: > "CAVEAT: Synthesis in the devel trunk is broken, Just to clear up any confusion here, I am not using the devel trunk. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 122530
"sriman" <srimankk@gmail.com> wrote in message news:1185809060.100078.285710@d30g2000prg.googlegroups.com... > I am tring to design a video acquisition system. I am usimg the DE1 > borad and the compactable TRB_DC2 camera module with it.(http:// > www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No =50). > The problem i am facing is on the data sheet 20 pins are assigned to > each sensor. i am a newibe to vlsi design. i am unable to distinguish > the usage of al the pins. only understood a few. can anyone help me > out by tellin whats the real functionalities of those pins > > i am attaching the pin descriptions with this post > > Pin Numbers Name Direction Description > 1 DATA1[0] Output Sensor 1 Data Bit 0 > 2 DATA1[1] Output Sensor 1 Data Bit 1 > 3 DATA1[4] Output Sensor 1 Data Bit 4 > 4 DATA1[3] Output Sensor 1 Data Bit 3 > 5 DATA1[5] Output Sensor 1 Data Bit 5 > 6 DATA1[2] Output Sensor 1 Data Bit 2 > 7 DATA1[6] Output Sensor 1 Data Bit 6 > 8 DATA1[7] Output Sensor 1 Data Bit 7 > 9 DATA1[8] Output Sensor 1 Data Bit 8 > 10 DATA1[9] Output Sensor 1 Data Bit 9 Parallel port. You get the sampled pixels (or color components) here. Usually pumped by the rising edge of the pixel clock. > 11 NC N/A Not Connect > 12 GND N/A Ground Let me think.... :) > 13 PIXCLK1 Output Sensor 1 Pixel Clock Pixel clock (time to read data) > 14 MCLK1 Input Sensor 1 Master Clock The heart of the sensor. You provide this signal. No MCLK, no life. > 15 LVAL1 Output Sensor 1 Line Valid Generally, triggers the start and the end of a sampled row When asserted, data at the parallel port is valid in sync with the pixel clock. > 16 FVAL1 Output Sensor 1 Frame Valid Generally, triggers the start and the end of a whole frame > 17 SCLK1 input Sensor 1 I2C Clock > 18 SDATA1 I/O Sensor 1 I2C Data Use them to control the sensor settings by writing to (and reading from) the internal sensor registers.Article: 122531
Antti, The people responsible are being challenged as we speak: the website isn't just used by customers. It is used by those of us in the IC Design group, by the verification and characterization teams, by the FAE's, and by the support organization. In effect, any "down" time becomes visible, and affects everyone. I am also pretty good with a web browser, and sometimes cached pages, or re-postings of documents appear elsewhere. But I don't appreciate digging for documents! AustinArticle: 122532
Brad Smallridge wrote:
> Hello Mike,
> No. The reset wasn't the problem.
> Here is the code:
A bram requires a control for write enable.
-- Mike Treseler
Article: 122533"austin" <austin@xilinx.com> wrote in message news:f8l09j$mti1@cnn.xilinx.com... > MM, > > I am asking the experts here. Will post their reply soon, Thanks Austin... /MikhailArticle: 122534
MM, The expert did not understand your question. Perhaps you could supply me with more details while he asks me to ask you some questions? One comment I received was that we thought it took a minimum of four DSPs to do what you want, and that was confusing to us (as we saw three in your post?). Austin MM wrote: > "austin" <austin@xilinx.com> wrote in message > news:f8l09j$mti1@cnn.xilinx.com... >> MM, >> >> I am asking the experts here. Will post their reply soon, > > Thanks Austin... > > /Mikhail > >Article: 122535
MM, Here it is: "If he wants to use RLOC_RANGE he has to create a set (using U_SET for example) and place the RLOC_RANGE attribute on a single member of the set, not on all of them as he is doing now with a wildcard. A simpler alternative would be to use independent LOC constraints on the three DSP48s.: I hope this helps. Austin austin wrote: > MM, > > The expert did not understand your question. > > Perhaps you could supply me with more details while he asks me to ask > you some questions? > > One comment I received was that we thought it took a minimum of four > DSPs to do what you want, and that was confusing to us (as we saw three > in your post?). > > Austin > > MM wrote: >> "austin" <austin@xilinx.com> wrote in message >> news:f8l09j$mti1@cnn.xilinx.com... >>> MM, >>> >>> I am asking the experts here. Will post their reply soon, >> Thanks Austin... >> >> /Mikhail >> >>Article: 122536
"austin" <austin@xilinx.com> wrote in message news:f8l8dm$mjv2@cnn.xilinx.com... > MM, > > "If he wants to use RLOC_RANGE he has to create a set (using U_SET for > example) and place the RLOC_RANGE attribute on a single member of the > set, not on all of them as he is doing now with a wildcard. > > A simpler alternative would be to use independent LOC constraints on the > three DSP48s.: Thanks again Austin. Obviously I wasn't using the RLOC_RANGE correctly... I have now put independent RLOCs on each of the DSP48s. I still think however that there has to be an easier (and less restrictive in terms of relative component order) way to tell the tools to place things close together. I believe the COMPRESS attribute is supposed to do just that but according to the docs it doesn't work for DSP48s. /MikhailArticle: 122537
Gabor wrote: > On Jul 28, 8:17 pm, Neil Steiner <neil.stei...@vt.edu> wrote: >> I'm working with a custom verilog core that accepts a small number of >> parameters, and I'm having a hard time pushing them through XST properly >> under EDK 8.1. >> >> For example, I include the following line in my .mpd file: >> >> PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10, >> MIN_SIZE=2, BUS=SDCR >> >> But XST happily reports: >> >> C_DCR_BASEADDR = 32'b00000000000000000000000001000000 >> >> Does anybody know how to ensure that my C_DCR_BASEADDR parameter is not >> initialized to something wider than 10 bits? > > > Did you try > > C_DCR_BASEADDR=10'b0001000000 I tried that just now, but platgen doesn't seem very happy with it. More specifically, it doesn't seem to recognize 10'b0001000000 as a number. > Normally verilog assumes integer (32-bit) type for unspecified > bit-widths. On the other hand are you sure that this matters? > If you assigned the parameter to a 10-bit vector as in > > wire [9:0] addr; > assign addr = C_DCR_BASEADDR; > > you'd just get the 10 LSB's of the parameter anyway. The little that I do know is that the hardware was responding as if the parameter had been zero. But based on your comments, I'll go ahead and dig just a bit more, because there might possibly be some User Cluelessness involved. ;)Article: 122538
On Jul 30, 8:47 pm, "devices" <me@home> wrote: > "sriman" <srima...@gmail.com> wrote in message > > news:1185809060.100078.285710@d30g2000prg.googlegroups.com...> I am tring to design a video acquisition system. I am usimg the DE1 > > borad and the compactable TRB_DC2 camera module with it.(http:// > > www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryN... > =50). > > > > > > > The problem i am facing is on the data sheet 20 pins are assigned to > > each sensor. i am a newibe to vlsi design. i am unable to distinguish > > the usage of al the pins. only understood a few. can anyone help me > > out by tellin whats the real functionalities of those pins > > > i am attaching the pin descriptions with this post > > > Pin Numbers Name Direction Description > > 1 DATA1[0] Output Sensor 1 Data Bit 0 > > 2 DATA1[1] Output Sensor 1 Data Bit 1 > > 3 DATA1[4] Output Sensor 1 Data Bit 4 > > 4 DATA1[3] Output Sensor 1 Data Bit 3 > > 5 DATA1[5] Output Sensor 1 Data Bit 5 > > 6 DATA1[2] Output Sensor 1 Data Bit 2 > > 7 DATA1[6] Output Sensor 1 Data Bit 6 > > 8 DATA1[7] Output Sensor 1 Data Bit 7 > > 9 DATA1[8] Output Sensor 1 Data Bit 8 > > 10 DATA1[9] Output Sensor 1 Data Bit 9 > > Parallel port. You get the sampled pixels (or color components) > here. Usually pumped by the rising edge of the pixel clock. > > > 11 NC N/A Not Connect > > 12 GND N/A Ground > > Let me think.... :) > > > 13 PIXCLK1 Output Sensor 1 Pixel Clock > > Pixel clock (time to read data) > > > 14 MCLK1 Input Sensor 1 Master Clock > > The heart of the sensor. You provide this signal. > No MCLK, no life. > > > 15 LVAL1 Output Sensor 1 Line Valid > > Generally, triggers the start and the end of a sampled row > When asserted, data at the parallel port is valid in sync with > the pixel clock. > > > 16 FVAL1 Output Sensor 1 Frame Valid > > Generally, triggers the start and the end of a whole frame > > > 17 SCLK1 input Sensor 1 I2C Clock > > 18 SDATA1 I/O Sensor 1 I2C Data > > Use them to control the sensor settings by writing to > (and reading from) the internal sensor registers.- Hide quoted text - > > - Show quoted text - what should me clk signal. can i use the same clock which i am using for the board.Article: 122539
On Jul 30, 6:11 am, "X.Y." <Xieyu1...@gmail.com> wrote: > On Jul 28, 6:34 am, Subroto Datta <sda...@altera.com> wrote: > > > > > > > On Jul 27, 1:25 am, "X.Y." <Xieyu1...@gmail.com> wrote: > > > > On Jul 27, 5:37 am, Subroto Datta <sda...@altera.com> wrote: > > > > > Hi X.Y, > > > > > The Incremental Compilation flow currently does not allow the > > > > imported .qxp to be "stamped" onto different instances. This is > > > > coming. One workaround is to have a different HDL file and name for > > > > each instance. Admittedly, this is not ideal but in many cases is an > > > > easy solution. (If you're making changes on the top-level file, it's > > > > painful to repeat in multiple files. But if the changes are in the > > > > HDL files beneath that entity, then it all works smoothly after the > > > > initial set-up.) > > > > > One flow Iused often, mainly because it works and is easy, is the > > > > pseudo-bottom up flow. This basically involves putting partitions on > > > > the hierarchies that are in the same level as the one/s you are > > > > interested in and set them to Empty(so they have no logic, but nothing > > > > gets removed). I then work on the partitions I want with quick > > > > compiles. Then, when I get what I want, I set that partition to post- > > > > fit and either set the other partitions to Source or delete them > > > > altogether(making everything else one big partition). It's quick and > > > > easy without creating sub-projects, making sure their layout fits into > > > > the top-level, etc. Also, in Q7.1 you can export a .qxp from sub > > > > partitions, so you can always save off your results. This works with > > > > multiple instances of the same thing, since they now have different > > > > instances(and locations). > > > > > What end goal are you using Incremental Compilation flow for? Are you > > > > trying to reduce compile times, are you trying to preserve > > > > performance, or something else? > > > > > - Subroto Datta > > > > Altera Corp. > > > > Thanks for your reply! My end goal is trying to preserve performance. > > > In our project, I use one Cyclone II FPGA to process four groups of > > > image signal which comes from four cameras. The processing algorithms > > > of the four groups of image signal are all the same. As a result, I > > > plan to build a subproject implementing the processing of one of the > > > four signals and export it as a partition. Then, I build a top level > > > project and import it four times. Certainly, I will do four different > > > pin assignments for the four partitions. > > > It appears that LogicLock can do it also, am I right?- Hide quoted text - > > > > - Show quoted text - > > > I would recommend against using LogicLock for preserving > > performance(which is done through back-annotation of location > > assignments). LogicLock is excellent for floorplanning, but can have > > issues with these back-annotated assignments. That portion of the > > LogicLock flow is really meant to be replaced by the Incremental > > Compilation flow. > > > One thing I want to make sure of, does your design not meet timing > > when run flat? Also, is it large portions of your design or just a > > small sub-section that continually fails timing? I'm assuming it > > doesn't meet timing when put together, and it's not just a single > > block, as the strategy for these flows can be slightly different. > > > Do your four equal blocks connect to each other? Is there some > > central, common logic? Do they connect to pins? The problem I've > > seen with what you're trying to do is a good placement of a single > > block isn't good everywhere. For example, let's say you put them into > > the four quadrants of the device. In the lower-level you optimize one > > for the top-left corner, so the connections it makes to pins are all > > placed along the top-and-left side, and the connections you make to > > internal logic are on the bottom and right sides. Now, if you try to > > keep that placement but move it to an instantiation on the bottom- > > right, your pin and logic connections are reversed, and if these paths > > are critical at all, they can fail timing. > > > Just to go over the pseudo-bottom up flow again, take your top-level > > design and: > > > 1) Put a partition on all four instances, and any thing else you want > > to put a partition on. > > > 2) Floorplan the partitions(most likely into quadrants) (This is can > > be optional) > > > 3) Set three of the four to empty and let the fitter work on the > > fourth one(say top-left region.) > > > 4) Set the top-left region to Post-Fit and set a second partition to > > Source(or Post-Synthesis) and fit it > > > 5) Repeat onto the third and fourth partition > > > 6) If any of them still doesn't make timing, you can back and refit > > that one while leaving the rest post-fit. > > > The nice thing about this flow is each region is aware of pin > > locations, as well as any logic that is not set to empty. So if there > > is some central block of logic, it can optimize placement to connect > > to that. If the pin assignments have a different layour for all four > > instances, the fitter can optimize for that. > > > Hope this helps, > > Subroto Datta > > Altera Corp.- Hide quoted text - > > > - Show quoted text - > > Hi, Subroto, > > Thanks for your reply, I have tried the pseudo-bottom up flow you > recommend. It works well! Once I fit a partition, I can find its > Floorplan Region in Timing Closure Floorplan. At last, there are four > regions for the four partitions. > > There are some answers for your questions as flow, > 1, My design doesn't meet timing when run flat. > 2, In my design, the four equal blocks connect to each other. > 3, There is some central, common logic and they connect to pins. > > And Besides, there are some questions I want to ask you: > 1, What do you mean by "The problem I've seen with what you're trying > to do is a good placement of a single block isn't good everywhere." > 2, Actually, in your method, we need to put all the design partitions > in a single Quartus project. The different thing is the compiling flow > you told me. It is not a real bottom up flow (because it involves sub > projects), so you call it pseudo- bottom up flow, am I right? > 3, You have ever said " Also, in Q7.1 you can export a .qxp from sub > partitions, so you can always save off your results. This works with > multiple instances of the same thing, since they now have different > instances (and locations). " in your first letter. Do you mean, we > can import one sub partition multiple times in Q7.1, however, not in > Q6.0? > > Best regards. > > Yours sincerely, > X. Y.- Hide quoted text - > > - Show quoted text - 1. One problem is that the memory/DSP is not always uniform in the FPGA. For example, if you have an MRAM in the top of one instance, it may no longer be at the top of another instance and it would require a completely different fit. But issues can also be more subtle. For example, since they all talk to each other, the instance in the top- left quadrant will want to place logic in its bottom-right corner to talk to the other quadrant that is diagonal from it. If you tried to have identical placement for the entity in the bottom right quadrant, it would now have logic in its lower-left corner that has to go across the entire quadrant to get to its destination, and could fail timing. 2) Correct. This flow doesn't require any sub-projects to be created, which is why I call is pseudo-bottom up. 3) No, you still can't import a sub-partition multiple times(at least you can't import it and keep the placement). But in this flow you can export a .qxp for the top-left instance, one for the bottom-left, one for the bottom-right and one for the top-right. So now you've got four .qxp files representing the four quadrant instances(and with different/better placement for each one.) Does the instance meet timing when run by itself? If not, how far off is it? Hope this helps, Subroto Datta Altera Corp.Article: 122540
MM, You are welcome. Your comments about the placement are noted. There is a lot of work going on in just this area (of best placement, easiest way to control..etc.). AustinArticle: 122541
"sriman" <srimankk@gmail.com> wrote in message news:1185824874.432611.242170@j4g2000prf.googlegroups.com... > On Jul 30, 8:47 pm, "devices" <me@home> wrote: > > "sriman" <srima...@gmail.com> wrote in message > > > > news:1185809060.100078.285710@d30g2000prg.googlegroups.com...> I am tring to design a video acquisition system. I am usimg the DE1 > > > borad and the compactable TRB_DC2 camera module with it.(http:// > > > > www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryN... > > =50). > > > > > > > > > > > > > The problem i am facing is on the data sheet 20 pins are assigned to > > > each sensor. i am a newibe to vlsi design. i am unable to distinguish > > > the usage of al the pins. only understood a few. can anyone help me > > > out by tellin whats the real functionalities of those pins > > > > > i am attaching the pin descriptions with this post > > > > > Pin Numbers Name Direction Description > > > 1 DATA1[0] Output Sensor 1 Data Bit 0 > > > 2 DATA1[1] Output Sensor 1 Data Bit 1 > > > 3 DATA1[4] Output Sensor 1 Data Bit 4 > > > 4 DATA1[3] Output Sensor 1 Data Bit 3 > > > 5 DATA1[5] Output Sensor 1 Data Bit 5 > > > 6 DATA1[2] Output Sensor 1 Data Bit 2 > > > 7 DATA1[6] Output Sensor 1 Data Bit 6 > > > 8 DATA1[7] Output Sensor 1 Data Bit 7 > > > 9 DATA1[8] Output Sensor 1 Data Bit 8 > > > 10 DATA1[9] Output Sensor 1 Data Bit 9 > > > > Parallel port. You get the sampled pixels (or color components) > > here. Usually pumped by the rising edge of the pixel clock. > > > > > 11 NC N/A Not Connect > > > 12 GND N/A Ground > > > > Let me think.... :) > > > > > 13 PIXCLK1 Output Sensor 1 Pixel Clock > > > > Pixel clock (time to read data) > > > > > 14 MCLK1 Input Sensor 1 Master Clock > > > > The heart of the sensor. You provide this signal. > > No MCLK, no life. > > > > > 15 LVAL1 Output Sensor 1 Line Valid > > > > Generally, triggers the start and the end of a sampled row > > When asserted, data at the parallel port is valid in sync with > > the pixel clock. > > > > > 16 FVAL1 Output Sensor 1 Frame Valid > > > > Generally, triggers the start and the end of a whole frame > > > > > 17 SCLK1 input Sensor 1 I2C Clock > > > 18 SDATA1 I/O Sensor 1 I2C Data > > > > Use them to control the sensor settings by writing to > > (and reading from) the internal sensor registers.- Hide quoted text - > > > > - Show quoted text - > > what should me clk signal. can i use the same clock which i am using > for the board. > I don't have that board so i cannot tell you much. The board has three clocks, but i don't know either if you can use them as independent clock sources or if there is any other constraint in their usage. I actually remember that the DE1 board comes with sample code and it's likely that there's a camera reference design. You might start by taking a look.Article: 122542
Yeah, you'll need the IDELAYCTRL. Page 311 of the V5 user guide.Article: 122543
On Jul 31, 4:00 am, Subroto Datta <sda...@altera.com> wrote: > On Jul 30, 6:11 am, "X.Y." <Xieyu1...@gmail.com> wrote: > > > > > > > On Jul 28, 6:34 am, Subroto Datta <sda...@altera.com> wrote: > > > > On Jul 27, 1:25 am, "X.Y." <Xieyu1...@gmail.com> wrote: > > > > > On Jul 27, 5:37 am, Subroto Datta <sda...@altera.com> wrote: > > > > > > Hi X.Y, > > > > > > The Incremental Compilation flow currently does not allow the > > > > > imported .qxp to be "stamped" onto different instances. This is > > > > > coming. One workaround is to have a different HDL file and name for > > > > > each instance. Admittedly, this is not ideal but in many cases is an > > > > > easy solution. (If you're making changes on the top-level file, it's > > > > > painful to repeat in multiple files. But if the changes are in the > > > > > HDL files beneath that entity, then it all works smoothly after the > > > > > initial set-up.) > > > > > > One flow Iused often, mainly because it works and is easy, is the > > > > > pseudo-bottom up flow. This basically involves putting partitions on > > > > > the hierarchies that are in the same level as the one/s you are > > > > > interested in and set them to Empty(so they have no logic, but nothing > > > > > gets removed). I then work on the partitions I want with quick > > > > > compiles. Then, when I get what I want, I set that partition to post- > > > > > fit and either set the other partitions to Source or delete them > > > > > altogether(making everything else one big partition). It's quick and > > > > > easy without creating sub-projects, making sure their layout fits into > > > > > the top-level, etc. Also, in Q7.1 you can export a .qxp from sub > > > > > partitions, so you can always save off your results. This works with > > > > > multiple instances of the same thing, since they now have different > > > > > instances(and locations). > > > > > > What end goal are you using Incremental Compilation flow for? Are you > > > > > trying to reduce compile times, are you trying to preserve > > > > > performance, or something else? > > > > > > - Subroto Datta > > > > > Altera Corp. > > > > > Thanks for your reply! My end goal is trying to preserve performance. > > > > In our project, I use one Cyclone II FPGA to process four groups of > > > > image signal which comes from four cameras. The processing algorithms > > > > of the four groups of image signal are all the same. As a result, I > > > > plan to build a subproject implementing the processing of one of the > > > > four signals and export it as a partition. Then, I build a top level > > > > project and import it four times. Certainly, I will do four different > > > > pin assignments for the four partitions. > > > > It appears that LogicLock can do it also, am I right?- Hide quoted text - > > > > > - Show quoted text - > > > > I would recommend against using LogicLock for preserving > > > performance(which is done through back-annotation of location > > > assignments). LogicLock is excellent for floorplanning, but can have > > > issues with these back-annotated assignments. That portion of the > > > LogicLock flow is really meant to be replaced by the Incremental > > > Compilation flow. > > > > One thing I want to make sure of, does your design not meet timing > > > when run flat? Also, is it large portions of your design or just a > > > small sub-section that continually fails timing? I'm assuming it > > > doesn't meet timing when put together, and it's not just a single > > > block, as the strategy for these flows can be slightly different. > > > > Do your four equal blocks connect to each other? Is there some > > > central, common logic? Do they connect to pins? The problem I've > > > seen with what you're trying to do is a good placement of a single > > > block isn't good everywhere. For example, let's say you put them into > > > the four quadrants of the device. In the lower-level you optimize one > > > for the top-left corner, so the connections it makes to pins are all > > > placed along the top-and-left side, and the connections you make to > > > internal logic are on the bottom and right sides. Now, if you try to > > > keep that placement but move it to an instantiation on the bottom- > > > right, your pin and logic connections are reversed, and if these paths > > > are critical at all, they can fail timing. > > > > Just to go over the pseudo-bottom up flow again, take your top-level > > > design and: > > > > 1) Put a partition on all four instances, and any thing else you want > > > to put a partition on. > > > > 2) Floorplan the partitions(most likely into quadrants) (This is can > > > be optional) > > > > 3) Set three of the four to empty and let the fitter work on the > > > fourth one(say top-left region.) > > > > 4) Set the top-left region to Post-Fit and set a second partition to > > > Source(or Post-Synthesis) and fit it > > > > 5) Repeat onto the third and fourth partition > > > > 6) If any of them still doesn't make timing, you can back and refit > > > that one while leaving the rest post-fit. > > > > The nice thing about this flow is each region is aware of pin > > > locations, as well as any logic that is not set to empty. So if there > > > is some central block of logic, it can optimize placement to connect > > > to that. If the pin assignments have a different layour for all four > > > instances, the fitter can optimize for that. > > > > Hope this helps, > > > Subroto Datta > > > Altera Corp.- Hide quoted text - > > > > - Show quoted text - > > > Hi, Subroto, > > > Thanks for your reply, I have tried the pseudo-bottom up flow you > > recommend. It works well! Once I fit a partition, I can find its > > Floorplan Region in Timing Closure Floorplan. At last, there are four > > regions for the four partitions. > > > There are some answers for your questions as flow, > > 1, My design doesn't meet timing when run flat. > > 2, In my design, the four equal blocks connect to each other. > > 3, There is some central, common logic and they connect to pins. > > > And Besides, there are some questions I want to ask you: > > 1, What do you mean by "The problem I've seen with what you're trying > > to do is a good placement of a single block isn't good everywhere." > > 2, Actually, in your method, we need to put all the design partitions > > in a single Quartus project. The different thing is the compiling flow > > you told me. It is not a real bottom up flow (because it involves sub > > projects), so you call it pseudo- bottom up flow, am I right? > > 3, You have ever said " Also, in Q7.1 you can export a .qxp from sub > > partitions, so you can always save off your results. This works with > > multiple instances of the same thing, since they now have different > > instances (and locations). " in your first letter. Do you mean, we > > can import one sub partition multiple times in Q7.1, however, not in > > Q6.0? > > > Best regards. > > > Yours sincerely, > > X. Y.- Hide quoted text - > > > - Show quoted text - > > 1. One problem is that the memory/DSP is not always uniform in the > FPGA. For example, if you have an MRAM in the top of one instance, it > may no longer be at the top of another instance and it would require a > completely different fit. But issues can also be more subtle. For > example, since they all talk to each other, the instance in the top- > left quadrant will want to place logic in its bottom-right corner to > talk to the other quadrant that is diagonal from it. If you tried to > have identical placement for the entity in the bottom right quadrant, > it would now have logic in its lower-left corner that has to go across > the entire quadrant to get to its destination, and could fail timing. > > 2) Correct. This flow doesn't require any sub-projects to be > created, which is why I call is pseudo-bottom up. > > 3) No, you still can't import a sub-partition multiple times(at least > you can't import it and keep the placement). But in this flow you can > export a .qxp for the top-left instance, one for the bottom-left, one > for the bottom-right and one for the top-right. So now you've got > four .qxp files representing the four quadrant instances(and with > different/better placement for each one.) > > Does the instance meet timing when run by itself? If not, how far off > is it? > > Hope this helps, > Subroto Datta > Altera Corp.- Hide quoted text - > > - Show quoted text - Hi, Subroto, Thanks for your help. The instance meets timing when run by itself. However, I meet a new problem when I try to optimize my design (I mean the instance). In my old instance, I use the same clock when image capture (storage), image display, and image processing. This clock, which is named "pclk", has a frequency of 24MHz. It is slow. The frequency of image capture and display cannot be changed because of the requirement of other device. So I want to increase the frequency of image processing. It involves SRAM reading, writing, and data processing. I use a PLL to acquire a clock of 72MHz. This is the problem. SRAM will also be read when image capture, and written when display. That means the clock, the address bus and data bus will be switched between the state of image capture/display and image process. Actually, I use two blocks: one for image capture/display and another for image process. And I use BUS MUX to switch address bus and data bus. Meanwhile, I use LPM MUX to switch the two clock of different frequency. Unfortunately, the instance does not meet timing. In Timing Analyzer Summary, it reports, Clock setup: 'pclk' has a slack of -4.152ns and Clock hold: 'pclk' has a slack of -4.216ns. Could you be kind enough to tell me how to solve this problem? Best Regards, Yours sincerely, X.Y.Article: 122544
Gang I'm looking for 2 examples that use the MicroBlaze FSL bus. The first example would do something like creating a component that adds to numbers together and returns them from the custom ip. The example would explain the steps you need to take thru the XPS (and the ISE) to make this run. The host C program would write the 2 operands to the fifo and read the resulting sum. In the second example, a host C program would write 3 coefficients and 2 pointers into the SDRAM into the fifo. The custom ip would effectively multiply and accumulate the coefficients against the input buffer. It would write the sum back out to the output buffer. I've looked at FSL_V20.pdf as well as xapp529. Xilinx really needs to do a better job of creating step by step examples for an important feature like the FSL. BobArticle: 122545
On 31 Jul., 06:08, bob.zi...@gmail.com wrote: > Gang > > I'm looking for 2 examples that use the MicroBlaze FSL bus. > > The first example would do something like creating a component that > adds to numbers together and returns them from the custom ip. > The example would explain the steps you need to take thru the XPS > (and the ISE) to make this run. The host C program would write the > 2 operands to the fifo and read the resulting sum. > > In the second example, a host C program would write 3 coefficients and > 2 pointers into the SDRAM into the fifo. The custom ip would > effectively > multiply and accumulate the coefficients against the input buffer. > It would write the sum back out to the output buffer. > > I've looked at FSL_V20.pdf as well as xapp529. Xilinx really needs to > do a better > job of creating step by step examples for an important feature like > the FSL. > > Bob Dear Bob, regarding your request: example 1: please run EDK 9.1 ip wizard for FSL, it creates the IP, library and test application exactly as you described. Add the ip, add the main C application, compile download and you see your FSL adder IP working, exactly as you described. THIS DOES EXIST already, your example 1 *IS* provided by Xilinx for you to be used. example 2: I did not understand what you want to do with SDRAM pointer. I guess this is the reason why Xilinx has not prepared this example for you. (means there is something you need todo yourself too) AnttiArticle: 122546
Dear All,
This is Jegadeesh from Trioz Technologies India Pvt Ltd.
We are currently working on a project under FlexRay to develop a
demonstration module to our customer.
At present we are in a design stage of the software based on the
hardware that we finished designing already.
we have planned to demonstrate the Flexray communication using PIC
controller interfacing with the Fujitsu's Flexray Stand Alone
Controller (MB88121B) by SPI(Serial Peripheral Interface). Further,
Stand Alone Controller is interfaced with the Austria Micro system's
Flexray Driver (AS8221).
We need to know some clarifications regarding Hardware Design of
AS8221 with MB88121B and channel Transmission / Reception.
The Flexray Standalone Controller has 2 channels A and B respectively.
Is it possible to Transmit Flexray Frames in a channel (Ex: CH A) and
Receive it via another channel (Ex: CH B) by using a two Transceivers
and one Flexray Controller?
Please reply back to me with solutions and suggesstions for our
clarifications at the earliest.
Thanks and Regards,
Jegadeesh.R
Article: 122547I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated memory that can be used as ROM and ~64Kb of integrated memory that can be used as EEPROM. Initially I considered using a parallel EPROM, serial EEPROM together with lots of TTL, but soon I realized that the EPROM, EEPROM together with a 22V10 GAL and a 74573 register would be a simpler solution. A few days ago I noticed how cheap CPLDs are today and that one, together with a 3.3V voltage regulator could replace the GAL and register. Now I ask myself if there is some PLD that could replace the EEPROM or EPROM, too. PhilippArticle: 122548
Philipp Klaus Krause schrieb: > I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated > memory that can be used as ROM and ~64Kb of integrated memory that can > be used as EEPROM. > > Initially I considered using a parallel EPROM, serial EEPROM together > with lots of TTL, but soon I realized that the EPROM, EEPROM together > with a 22V10 GAL and a 74573 register would be a simpler solution. > A few days ago I noticed how cheap CPLDs are today and that one, > together with a 3.3V voltage regulator could replace the GAL and register. > > Now I ask myself if there is some PLD that could replace the EEPROM or > EPROM, too. > > Philipp The device doesn't have to be fast, 8 Mhz for a simple design would be OK. I need about 40 I/O. PhilippArticle: 122549
I'm looking to update a couple of products from VIIPro to V5 devices. Is there some very rough comparison of the relative logic capabilities of the 2 FPGA ranges somewhere? The redefining of the logic slices and the subsequent adaptation of the capacity figures in the literature have made it harder to compare. So, for example, is the LX30T approximately equivalent to a VP4 or is it as big as a VP20? This is obviously just in terms of the logic capacity and not involving the extra features on V5s. TIA, Rog.
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