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Messages from 120600

Article: 120600
Subject: Re: EDK 9.1 + Virtex 5 Hard MAC
From: Eric Smith <eric@brouhaha.com>
Date: 11 Jun 2007 12:34:47 -0700
Links: << >>  << T >>  << A >>
Jorge <jorge.wpi@gmail.com> writes:
> I figured out how
> to create a simple Microblaze system which uses the opb_ethernet IP
> core, but I would like to switch to the hard MAC on the virtex5 fpga.
> EDK does not have a wrapper for this in it's IP core list, so I used
> the Xilinx Core Generator to generate it.  The problem I am having is
> importing the core into EDK. 

Is there much difference between the V4 and V5 TEMACs?  If not,
it might be easier to take the hard_temac RTL supplied for the V4 
and convert it to use the V5.


Article: 120601
Subject: Re: Unexpected resources utilization
From: eryksson@gmail.com
Date: Mon, 11 Jun 2007 19:46:09 -0000
Links: << >>  << T >>  << A >>
On Jun 11, 12:07 pm, mk <kal*@dspia.*comdelete> wrote:
> On Mon, 11 Jun 2007 16:01:24 -0000, eryks...@gmail.com wrote:
> >I am programing a 8-channel digitizing board based on xc3s400 and I
> >ran into the following situation:
>
> >Here are peaces of code that I think might make it easier to
> >understand:
>
> >COMPONENT ADC_Channel
> >    Port ( CLK : in  STD_LOGIC;
> >              FX_CLK : in STD_LOGIC;
> >           S1WE : in  STD_LOGIC;
> >           S2WE : in  STD_LOGIC;
> >           S1Found : out  STD_LOGIC;
> >           S2Found : out  STD_LOGIC;
> >           ADC_Raw : in  STD_LOGIC_VECTOR (14 downto 0);
> >           CurSample : out  STD_LOGIC_VECTOR (15 downto 0);
> >           FX_IOBUS : inout  STD_LOGIC_VECTOR (7 downto 0);
> >           FX_ADDR : in  STD_LOGIC_VECTOR (15 downto 0);
> >              FX_MemSelect: in STD_LOGIC);
> >END COMPONENT;
>
> Is it possible that the logic which generates SxFound in the
> ADC_Channel is being trimmed when it's not being used and when you
> actually use it, it's using too many resources?

Thank you for such a prompt reply. I was aware that the Xilinx
software terminates logic but I never knew to what extant.
But I don't think that this is the problem because I did the
following.

The SxFound in the ADC_Channel component is generated by:

	process (CLK)
	begin
		if CLK = '0' and CLK'Event then
			if (FilterOutputSx > 50) then
				SxFound <= '1';
			else
				SxFound <= '0';
			end if;
		end if;
	end process;

And I made sure that FilterOutputSx is used (in the ADC_Channel):

	process(CurSelect)
	begin
         case CurSelect is
            when "00" => CurSample <= DI16;
            when "01" => CurSample <= FilterOutputS2(22 downto 7);
            when "10" => CurSample <= FilterOutputS1(22)&FilterOutputS1(15 downto 1);
            when others => CurSample <= "0000000000000000";
         end case;
	end process;
Where CurSample is routed all the way to an external DAC (confirmed
with a scope).

Then I compiled everything twice. Once with the portion:
--S1FoundProc: PROCESS(CLKIN)
--begin
--	if CLKIN = '0' and CLKIN'Event then
--		if (S1Found /="00000000") then
--			S1FoundB <= '1';
--		else
--			S1FoundB <= '0';
--		end if;
--	end if;
--end process;

of the Top Module code commented out and once not commented out.

I don't know why the Synthesize part reported utilization of around
95-97% in both cases, when the actual implementation is much less:

Here are the results (after Place & Route):

Logic Utilization	                                 Utilization without
S1FoundProc	Utilization with S1FoundProc
Number of Slice Flip Flops
17%	                                   27%
Number of 4 input LUTs
23%	                                   35%
Logic Distribution
Number of occupied Slices
51%	                                  74%
    Number of Slices containing only related logic
100%	                                  100%
    Number of Slices containing unrelated logic
0%	                                      0%
Total Number of 4 input LUTs
38%	                                  53%


Any idea why for example there is 10% increase in FF usage?
Any other ideas?

Thank you once again,
Have a good day,
Eryk


Article: 120602
Subject: Re: EDK Sim: BRAM won't init
From: motty <mottoblatto@yahoo.com>
Date: Mon, 11 Jun 2007 12:50:13 -0700
Links: << >>  << T >>  << A >>
I found a workaround.  It seems that the system_init.v file differs
between the 8.2 and 9.1 tools.  There is an extra hierarchical
component in the 9.1 generated file's defparam statements.  I can
deleted that from every line and the RAMs init fine and all is well
and good.  It even gets rid of a 'possible defparam loop' warning in
ModelSim.

Now, why did that file change from the old tools?  Who knows, right?
Is no one simulating EDK projects with 9.1 tools?  I can't believe
that.  Is my project screwed up such that this problem results?  I
have a webcase open and have given detailed explanation of the problem
and my workaround.  But I just spent a full day doing this.  Yay!  I
am back to where I was before upgrading to the 9.1 tools!!!  I didn't
want to do it, but I needed some updated IP wizard.



Article: 120603
Subject: Help with T-VPACK
From: Ji Soon Kim <jisoon.kim@gmail.com>
Date: Mon, 11 Jun 2007 20:12:12 -0000
Links: << >>  << T >>  << A >>
Hello,

I need help with using T-VPACK. I have been having trouble getting T-
VPACk to accept the blif files I've been writing or generating from
verilog files using the steps found on this board.

I was wondering if anybody has either have a verilog file that has
worked for T-VPACK after converting or a BLIF that worked on T-VPACK
(apart from the ones included as an example in VPR&T-VPACK package).

Thank you in advance,

Jisoon Kim


Article: 120604
Subject: Optical RocketIO
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 11 Jun 2007 21:53:40 +0100
Links: << >>  << T >>  << A >>
I've been using a certain make of fibre-optic transceiver to provide optical 
RIO connectivity at the full 3.125Gbps rate. The manufacturer has dropped 
the parts I've been using and I'm now looking for an alternative.

Has anyone else used optical links and if so, what transceiver did you use?

TIA.

Roger. 



Article: 120605
Subject: Re: How to put part of program data into local ram, the rest into external memroy?
From: "Vasanth Asokan" <vasanth@xilinx.com>
Date: Mon, 11 Jun 2007 14:05:57 -0700
Links: << >>  << T >>  << A >>

"Yao Sics" <yao.sics@gmail.com> wrote in message 
news:1181549547.218570.72500@r19g2000prf.googlegroups.com...
> Hi guys,
>
> I have a question regarding how to use linker script to place specific
> data in the specific memory.
> Lets make long story short. Assume I have four arrays: a[100], b[100],
> c[1000], d[1000] in the main.c. I wanna put the first two array
> a[100], b[100] into local memory, DSOCM, while the others into the
> external DDR. How can I do this by linker script? Any input would be
> greatly appreciated!
>
> I just found a webpage briefly touches this issue from xilinx answer
> database. See the solution2,
> It says"Another method is to keep any variables whose locations you
> want to control in a separate file (this example will use
> "special.c")." I just wondered how can I keep those variables in a
> separate file .c?
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13810
>

I did not understand which part of the above answer record your difficulty 
is with. Unless your data structures are an integral part of your main.c it 
should be fairly easy to move them to another file. Assigning an entire .o 
file or a section from a .o file to memory then becomes easy in the linker 
script. The linker script construct is described in the answer record as 
well as the GNU linker manual.

> Thanks in advance,
>
> Yao
>

Apart from the method in the answer record above, you can use section 
attributes on your data structures to assign them to specific sections. For 
example,

int a[100] __attribute__((section(".mydatasection")));

Then in your linker script, create a new section assignment and assign it to 
the memory you want. You can do the same thing for functions. For example,

 .bramdata:{
*(.mydatasection)
}> BRAM

Refer to the GNU GCC docs on section attributes and the GNU linker script 
docs on section assignment to memory.

- Vasanth 



Article: 120606
Subject: Re: adaptive filter FPGA
From: Spiros Lakkos <slakkos@hotmail.com>
Date: Mon, 11 Jun 2007 22:31:01 GMT
Links: << >>  << T >>  << A >>
cutemonster wrote:

> 
> I have to sample x and y because it doesn't work like raster signal.  It's
> voltage varies in time. There is another signal input called Unblank(TTL). 
> It turn on and off of XY signal.  
> 

You are talking here about a hardware Vector to Raster Converter.

There is a nice FPGA based Vector to Raster converter
in the Asteroids Deluxe video-game recreation made by
the fellows of FPGA-ARCADE at :

http://home.freeuk.com/fpgaarcade/ast_main.htm

and by Eric Crabill of FPGA-GAMES at :

http://www.fpga-games.com/astdlx.htm


For a general hardware implementation you can also
check the US States Patent and Trademark Office

http://patft.uspto.gov/netahtml/PTO/srchnum.htm

for Patent Nrs 5969699 and 6496160.



The above references might give you an idea of the kind
of digital filters used during this conversion process.




--==============================================
--               Spiros Lakkos
--  http://cybernetic-engineering.blogspot.com/
--==============================================

Article: 120607
Subject: Re: synthesis - design compiler or synplify pro?
From: Andy <jonesandy@comcast.net>
Date: Mon, 11 Jun 2007 15:51:42 -0700
Links: << >>  << T >>  << A >>
On Jun 11, 12:31 pm, Wei Wang <camww...@gmail.com> wrote:
> On Jun 11, 12:46 pm, Jon Beniston <j...@beniston.com> wrote:
>
> > > I'm trying to think hard how design compiler and synplify pro differ
> > > with each other from a user's point of view, for example, synthesizing
> > > for xilinx virtex fpga. Any inputs would be grateful.
>
> > Synplify Pro will give you better results.
>
> > Cheers,
> > Jon
>
> any review articles comparing those two products? pointers to those
> articles would be greatly appreciated.

Synplify Pro only works for FPGAs

Synopsys DC only works for ASICS.

What's to compare? Synplify Pro has better language coverage for VHDL,
but other than that, it all boils down to the features of the target
implementation, and not so much about the tool.

Back when Synopsys FPGA Compiler II was around we compared it to
Synplify Pro, targeting Xilinx FPGAs, and SP won hands down in QOR,
run time, ease of use, language (vhdl) coverage, virtually everything,
including cost. I don't recall a single category that FC2 beat SP.
There were a handful of corner cases where FC2 gave  a better (faster/
smaller) implementation than SP, but there were many more for which
the SP implementation was better than FC2.

Andy


Article: 120608
Subject: Re: Optical RocketIO
From: johnp <johnp3+nospam@probo.com>
Date: Mon, 11 Jun 2007 16:17:13 -0700
Links: << >>  << T >>  << A >>
Roger -

I've recently used an Agilent HFBR-5921L running at 1.0625 GHz

John Providenza

On Jun 11, 1:53 pm, "Roger" <enquir...@rwconcepts.co.uk> wrote:
> I've been using a certain make of fibre-optic transceiver to provide optical
> RIO connectivity at the full 3.125Gbps rate. The manufacturer has dropped
> the parts I've been using and I'm now looking for an alternative.
>
> Has anyone else used optical links and if so, what transceiver did you use?
>
> TIA.
>
> Roger.



Article: 120609
Subject: Re: How to put part of program data into local ram, the rest into external memroy?
From: Yao Sics <yao.sics@gmail.com>
Date: Mon, 11 Jun 2007 21:28:23 -0700
Links: << >>  << T >>  << A >>
On Jun 12, 5:05 am, "Vasanth Asokan" <vasa...@xilinx.com> wrote:
> "Yao Sics" <yao.s...@gmail.com> wrote in message
>
> news:1181549547.218570.72500@r19g2000prf.googlegroups.com...
>
>
>
>
>
> > Hi guys,
>
> > I have a question regarding how to use linker script to place specific
> > data in the specific memory.
> > Lets make long story short. Assume I have four arrays: a[100], b[100],
> > c[1000], d[1000] in the main.c. I wanna put the first two array
> > a[100], b[100] into local memory, DSOCM, while the others into the
> > external DDR. How can I do this by linker script? Any input would be
> > greatly appreciated!
>
> > I just found a webpage briefly touches this issue from xilinx answer
> > database. See the solution2,
> > It says"Another method is to keep any variables whose locations you
> > want to control in a separate file (this example will use
> > "special.c")." I just wondered how can I keep those variables in a
> > separate file .c?
>
> >http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry...
>
> I did not understand which part of the above answer record your difficulty
> is with. Unless your data structures are an integral part of your main.c it
> should be fairly easy to move them to another file. Assigning an entire .o
> file or a section from a .o file to memory then becomes easy in the linker
> script. The linker script construct is described in the answer record as
> well as the GNU linker manual.
>
> > Thanks in advance,
>
> > Yao
>
> Apart from the method in the answer record above, you can use section
> attributes on your data structures to assign them to specific sections. For
> example,
>
> int a[100] __attribute__((section(".mydatasection")));
>
> Then in your linker script, create a new section assignment and assign it to
> the memory you want. You can do the same thing for functions. For example,
>
>  .bramdata:{
> *(.mydatasection)
>
> }> BRAM
>
> Refer to the GNU GCC docs on section attributes and the GNU linker script
> docs on section assignment to memory.
>
> - Vasanth- Hide quoted text -
>
> - Show quoted text -


Hi Vasanth,

Thank you very much for your input.

I will give it a try for the __attribute__((section())) approach.
Another quick question regarding this __attribute__. Is it only legal
to be used on global variables?

Cheers,

Yao


Article: 120610
Subject: Power consumption problem
From: Amine.Miled@gmail.com
Date: Mon, 11 Jun 2007 22:33:22 -0700
Links: << >>  << T >>  << A >>
Hi,

when i implemented my architecture using ACTEL AFS600 (Fusion family)
i noticed that over 16MHz there is a gap in consumption, in fact when
i was changing my frequency from 1 kHz to 16 Mhz the power consumption
is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
and the power consumption jump directly to 30 mW,
anyone has any reason to explain this gap?

my speed grade is -2,


Regards,
A.


Article: 120611
Subject: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
From: "sjulhes" <t@aol.fr>
Date: Tue, 12 Jun 2007 07:43:44 +0200
Links: << >>  << T >>  << A >>
Yes It works fine, I've used it several times, just dispatch things in the 
linker script.
But be we have a problem, when we reset the firmware, heap gets full and 
heap initialization get false as the heap pointer reaches memory upper 
limit. For now we can't get the to reset the heap pointer, so if you have a 
solution please let me know !



"Pablo" <pbantunez@gmail.com> a écrit dans le message de news: 
1181575038.650482.31310@q66g2000hsg.googlegroups.com...
> Hi, I have a program which needs to allocate high memory with calloc,
> but I want to load the app on the BRAM, so I wish to configure linker
> script so heap resides on the SDRAM. Is it possible?. Does anyone try
> to do this?
> 



Article: 120612
Subject: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
From: Pablo <pbantunez@gmail.com>
Date: Tue, 12 Jun 2007 07:46:11 -0000
Links: << >>  << T >>  << A >>
On Jun 12, 7:43 am, "sjulhes" <t...@aol.fr> wrote:
> Yes It works fine, I've used it several times, just dispatch things in the
> linker script.
> But be we have a problem, when we reset the firmware, heap gets full and
> heap initialization get false as the heap pointer reaches memory upper
> limit. For now we can't get the to reset the heap pointer, so if you have a
> solution please let me know !
>
> "Pablo" <pbantu...@gmail.com> a =E9crit dans le message de news:
> 1181575038.650482.31...@q66g2000hsg.googlegroups.com...
>
> > Hi, I have a program which needs to allocate high memory with calloc,
> > but I want to load the app on the BRAM, so I wish to configure linker
> > script so heap resides on the SDRAM. Is it possible?. Does anyone try
> > to do this?

How do you configure the linker script?. Only stack and heap for the
sdram and the rest of the parameters to the bram?

Thanks


Article: 120613
Subject: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
From: Pablo <pbantunez@gmail.com>
Date: Tue, 12 Jun 2007 00:59:33 -0700
Links: << >>  << T >>  << A >>
On 12 jun, 07:43, "sjulhes" <t...@aol.fr> wrote:
> Yes It works fine, I've used it several times, just dispatch things in the
> linker script.
> But be we have a problem, when we reset the firmware, heap gets full and
> heap initialization get false as the heap pointer reaches memory upper
> limit. For now we can't get the to reset the heap pointer, so if you have a
> solution please let me know !
>
> "Pablo" <pbantu...@gmail.com> a =E9crit dans le message de news:
> 1181575038.650482.31...@q66g2000hsg.googlegroups.com...
>
> > Hi, I have a program which needs to allocate high memory with calloc,
> > but I want to load the app on the BRAM, so I wish to configure linker
> > script so heap resides on the SDRAM. Is it possible?. Does anyone try
> > to do this?

If I configure Heap and Stack for SDRAM in linker script, the program
doesn't run.


Article: 120614
Subject: Re: Power consumption problem
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Tue, 12 Jun 2007 20:05:45 +1200
Links: << >>  << T >>  << A >>
Amine.Miled@gmail.com wrote:
> Hi,
> 
> when i implemented my architecture using ACTEL AFS600 (Fusion family)
> i noticed that over 16MHz there is a gap in consumption, in fact when
> i was changing my frequency from 1 kHz to 16 Mhz the power consumption
> is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
> and the power consumption jump directly to 30 mW,
> anyone has any reason to explain this gap?
> 
> my speed grade is -2,

Is it operating normally over that threshold ?
Normally, such a current discontinuity, also infers
an operational discontinuity.

Does the slope continue at just under 0.5mW/Mhz above that threshold ?

I'd test again with some simpler code, that you know has a very high Fmax.

-jg


Article: 120615
Subject: UK shop - FPGA boards + chips.
From: NickNitro <NickHolby@googlemail.com>
Date: Tue, 12 Jun 2007 01:33:10 -0700
Links: << >>  << T >>  << A >>
Hi,

Is there a UK site where I can get FPGA boards (particularly aimed at
Spartan3 series) and the FPGAs?

Thanks,
Nick.


Article: 120616
Subject: Re: UK shop - FPGA boards + chips.
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Tue, 12 Jun 2007 10:38:53 +0200
Links: << >>  << T >>  << A >>
NickNitro wrote:
> Hi,
> 
> Is there a UK site where I can get FPGA boards (particularly aimed at
> Spartan3 series) and the FPGAs?
> 
> Thanks,
> Nick.
> 


enterpoint.co.uk

Article: 120617
Subject: Apart from IEEE, is there some another journals for publishing an FPGA article?
From: Pablo <pbantunez@gmail.com>
Date: Tue, 12 Jun 2007 03:38:18 -0700
Links: << >>  << T >>  << A >>
Hi, I would like to know if someone could recommend me some journal
for publishing my article about FPGA.


Article: 120618
Subject: Re: Topics and Ideas for BS Project
From: Evan Lavelle <nospam@nospam.com>
Date: Tue, 12 Jun 2007 12:00:51 +0100
Links: << >>  << T >>  << A >>
[it's very hard to follow your posts - you need to attribute your
quotations]

On 8 Jun 2007 10:59:32 GMT, Colin Paul Gloster
<Colin_Paul_Gloster@ACM.org> wrote:

>If one thread/process is running and all other threads/processes are
>not running, then they are not running concurrently. They are not
>running, actually.

that's how (most) computers work. That's also exactly how the standard
Unix process model works, but no-one claims that it's not a
"concurrent" OS. Anyway, the issue of how threads and processes are
handled is not related to any user-level notion of concurrency
provided by an HDL; SystemC, VHDL, and Verilog all provide user-level
concurrency, whatever hardware or OS they run on.

>     
>     "Or are you saying that you can't implement SystemC on concurrent
>     hardware/multi-threaded processors/whatever?"
>
>I am not saying that. However, I am not aware of a SystemC(R)
>implementation (aside from synthesizers of course) which actually
>exploits concurrent hardware (e.g. a multiprocessor workstation).

I'm not either, but that doesn't mean that it hasn't been done, or is
not possible. Are you aware of any VHDL or Verilog implementations
which exploit 'concurrent hardware'? Yes, I'm sure there are trivial
examples of multi-threaded simulators, but are you aware of any
simulators which assign processes to threads? I'm not. You can't do
this unless you're absolutely sure that the processes don't interact
(take another look at the rest of note 4.2.1.2: that's what it's
trying to say). Besides, it would generally be pointless; any
realistic simulation runs a vast number of "simultaneous" "concurrent"
processes, and you need special-purpose hardware to make any sense of
that.

If I can just repeat what I said, or tried to say, im my last post,
the issue of underlying concurrency support is just not relevant. HDL
simulation semantics are defined in such a way that everything happens
*sequentially*, in such a way that *models*, or simulates,
"concurrency". This is true of any HDL that I know about. If you're
really smart, you can try to take advantage of 'parallel' hardware to
run multiple processes simultaneously, but it's difficult.

>If
>you check one of the forums on SystemC.org you can notice people who
>were not pleased that their OSCI simulators would use just one
>operating system process.

I've been following these forums for years, and I don't recall any
specific discussions on this. 

 
>     BTW, what is SystemC(R)? 'SystemC' is an OSCI trademark, in the same
>     way that 'Verilog' is a Cadence trademark."
>
>Terms and/or conditions similar to what were imposed on me can be
>found on
>WWW.SystemC.org/account/register.php
>, such as:
>[...snipped]
>ASCII does not have a registered trademark character, so "(R)" can
>suffice instead.

You would use (TM) in normal usage. But my point was that the word
"Verilog" is also trademarked. I'm sure that we could have a Verilog
discussion without continuously referring to "Verilog(R)" or
Verilog(TM)". Everybody else calls it "SystemC".

Evan  

Article: 120619
Subject: Re: Affordable pcie card ?
From: "Manfred Kraus" <nobody@nowhere.not>
Date: Tue, 12 Jun 2007 14:06:16 +0200
Links: << >>  << T >>  << A >>
>If PCIe isn't really a part of the project but just an interface, you
>may be better of putting a board together with a PLX bridge chip and
>an FPGA.

If this would be an option for you, look at
www.cesys.com . The PCIeS4BASE has
a PLX bridge chip, 512 MB SO-DIMM
and a Virtex-4 for 1.249 Euro.

-Manfred Kraus, CESYS GmbH





Article: 120620
Subject: Re: Apart from IEEE, is there some another journals for publishing an FPGA article?
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 12 Jun 2007 12:17:25 GMT
Links: << >>  << T >>  << A >>
Pablo <pbantunez@gmail.com> posted:
     "Hi, I would like to know if someone could recommend me some journal
     for publishing my article about FPGA."

If you search for
FPGA
on
HTTP://Portal.ACM.org
you can find such journals.

Article: 120621
Subject: Re: UK shop - FPGA boards + chips.
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 12 Jun 2007 13:35:10 +0100
Links: << >>  << T >>  << A >>
Here is a direct link to our boards 
http://www.enterpoint.co.uk/boardproducts.html. You will find links to our 
shop website off most of the individual product pages. Have a look at our 
newsletter signup page for current special offers 
http://www.enterpoint.co.uk/signup.html.

John Adair
Enterpoint Ltd.

"Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote in 
message news:466e5baa$0$13850$ba620e4c@news.skynet.be...
> NickNitro wrote:
>> Hi,
>>
>> Is there a UK site where I can get FPGA boards (particularly aimed at
>> Spartan3 series) and the FPGAs?
>>
>> Thanks,
>> Nick.
>>
>
>
> enterpoint.co.uk 



Article: 120622
Subject: Re: LVPECL output skew
From: Mavrick <>
Date: Tue, 12 Jun 2007 07:26:34 -0700
Links: << >>  << T >>  << A >>
Brian,

Thanks for the tip. We can do the voltage translation using external resistors but that affects the signal integrity and attenuates the signal.

In my application, I need to interface the FPGA LVDS output to CML that is normally powered at 3.3V. The CML part of interest supports differtnial swing of 400mV to 1200mV. Thus the single ended range is 200 to 600mv and the desired common mode voltage range is vcc-100mv to vcc-300mv where vcc = 3.3V. Also the output can not exceed vcc +0.5V.

I wish that the FPGA provided the ability to vary the output common mode voltage. This can help solve the electrical issuses.

Mavrick

Article: 120623
Subject: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
From: "sjulhes" <t@aol.fr>
Date: Tue, 12 Jun 2007 16:30:56 +0200
Links: << >>  << T >>  << A >>
Just start with the heap in the sdram, experiment with a little firmware for 
test.


"Pablo" <pbantunez@gmail.com> a écrit dans le message de news: 
1181635173.201211.44120@a26g2000pre.googlegroups.com...
On 12 jun, 07:43, "sjulhes" <t...@aol.fr> wrote:
> Yes It works fine, I've used it several times, just dispatch things in the
> linker script.
> But be we have a problem, when we reset the firmware, heap gets full and
> heap initialization get false as the heap pointer reaches memory upper
> limit. For now we can't get the to reset the heap pointer, so if you have 
> a
> solution please let me know !
>
> "Pablo" <pbantu...@gmail.com> a écrit dans le message de news:
> 1181575038.650482.31...@q66g2000hsg.googlegroups.com...
>
> > Hi, I have a program which needs to allocate high memory with calloc,
> > but I want to load the app on the BRAM, so I wish to configure linker
> > script so heap resides on the SDRAM. Is it possible?. Does anyone try
> > to do this?

If I configure Heap and Stack for SDRAM in linker script, the program
doesn't run.



Article: 120624
Subject: Re: EDK Simulation Problem
From: "sjulhes" <t@aol.fr>
Date: Tue, 12 Jun 2007 16:32:54 +0200
Links: << >>  << T >>  << A >>
I have the same problem, but I just can't have it working !!
EDK keeps saying there is no lib information on the Compxlib library resluts 
directory.

Do you have another clue ???

"motty" <mottoblatto@yahoo.com> a écrit dans le message de news: 
1181344353.375246.112470@p77g2000hsh.googlegroups.com...
> Thanks Mike,
>
> I got it working.  I used the EDK to start the compilation process and
> it put those extra files....modelsim.ini, _info, etc. that weren't in
> there before.  Compilation errored out, but I went the manual route
> and it works now.
> 





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