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On Jun 13, 10:18 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 13 Jun 2007 13:27:39 -0000, > > ZR1TECH <ZR1T...@gmail.com> wrote: > >Can I do this all in a FPGA? > > >I would like to sync to an incoming pulse (its actually going to be a > >register write) that I will receive at approx 100hz, and generate a > >8Khz output clock. > > Yes, definitely. Getting *really* good results may be quite > tricky, though. > > > > >This will be a recovered sync from a master device, but the devices > >are SW based so there will be a fair amount of jitter (~+/- 500us) .. > >but this jitter is expected to be bounded > >and stable (not slipping in time) over a long period. > > >Is it possible to use a local 50Mhz oscillator and create and up/down > >counter based on the 100hz signal, then slightly adjust the 8Khz clock > >rate based on this? > > For sure. The interesting question is, what are you > really trying to achieve? Are you trying to ensure that yuo > get as nearly as possible 80 output pulses between each > pair of 100Hz register writes? Or are you trying to get > an essentially constant frequency that is, over very long > periods, locked to the long-term average of the 100Hz? > > What I'm getting at is that anything that responds promptly > to changes in the 100Hz input will obviously cause jitter > on the 100 Hz to propagate to the output. Likewise, > anything that smooths the 8kHz output so that it has > minimal jitter, and its frequency changes slowly and > smoothly, will of course fail to respond to rapid > changes in the 100Hz signal's behaviour. You need to > know something about the statistics of the reference > signal, and the desired behaviour of the output. > > Having said all that, the frequencies you describe are > so slow that you have LOTS of time to do any calculations > that might be needed; so you can do quite sophisticated > filtering with a small amount of hardware (or even with > software in an embedded CPU of some kind). > > I did something loosely similar when I wanted to know the > exact position of a rotating flywheel, but could see only > a single index pulse per revolution. In that case I was > able to make use of the known physics of the rotating > object, and the known behaviour of the index pulse > sensor, to make things work better. Some interesting > juggling was necessary to get the thing into lock > quickly at startup time - it's often a good idea to > have two operating modes, "acquiring lock" and > "holding lock". And then you have to be VERY careful > about what happens as you transition from one mode > to the other. By the way: that example was recovering > a roughly 5kHz pulse train from a roughly 30Hz signal, > and I did it all in a little PIC microcontroller! And > no, you can't have the code; it was so long ago that > I have certainly lost it all! > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, Thanks much for the info! I am in fact trying to get an 8K clock locked to the long-term average of the 100Hz.. The system has one timed master (M) this master generates sync packets to another system at a rate of 100hz, when the slave (S) recovers these packets the hardware is updated via a register write to the FPGA. Jitter is introduced via SW trasmit (though very little), network (most of the jitter, as well as a possible packet loss every so often), as well as the SW receiver.. this jitter will be bounded, but its there :) so a clock based on the master that does not slip significantly over time (wander is ok.. just no long term slipping) is what I am after.... Lock time can be in the order of minutes, and quick changes are not what I am looking for.. Im just starting on it so I obviously have alot more homework to do :) thanks much! any info or advice is greatly appreciated! -BillArticle: 120676
ON NEXT MONDAY : 17-JUNE-2006 Amontec will provide the ‘how-to’ program via a XILINX VIRTEX XC4VLX25 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! On next Monday, your Amontec JTAG key will be close to the speed of a Xilinx Platform Cable USB for programming any FPGA and CPLD vendors (Altera Xilinx Lattice Cypress ...) Come back next Monday on http://www.amontec.com ! LaurentArticle: 120677
Is it possible to post a picture a diagram on here?Article: 120678
J.Ram, You have selected to do a verify in iMPACT after configuration. This is why iMPACT is looking for the .msk file. You have two options here. Either deselect the verify operation or have Bitgen create the mask file for you when you generate the bitstream. Look to the Bitgen documentation on using the -m switch for this: http://toolbox.xilinx.com/docsan/xilinx9/books/docs/dev/dev.pdf -David "J.Ram" <jrgodara@gmail.com> wrote in message news:1181732731.232269.185750@d30g2000prg.googlegroups.com... >I have generated a .bit file and try to program xc2v3000 FPGA but > through impact gives a message that checking done pin.............done > pin do not high , program terminated. > so i verify operation in impact and impact gives a error message that > top_design.msk does not exist . > my qustion is where .msk file will be generated and is it really > needed during programming FPGAs. > i checked all other probable error possibilities , so please give > comment. >Article: 120679
In news:qgts635ef1r6kvl1vk0oqdmpmomseugodp@4ax.com timestamped Tue, 12
Jun 2007 12:00:51 +0100, Evan Lavelle <nospam@nospam.com> posted:
"[..]
On 8 Jun 2007 10:59:32 GMT, Colin Paul Gloster
<Colin_Paul_Gloster@ACM.org> wrote:
>If one thread/process is running and all other threads/processes are
>not running, then they are not running concurrently. They are not
>running, actually.
that's how (most) computers work. That's also exactly how the standard
Unix process model works,"
Hi,
By invoking top with
top -i
(to more closely (though unfortunately still not perfectly) show only
active tasks)
and after invocation pressing 1 to remove the imaginary single CPU
load with loads for real CPUs, it is possible to check that tasks can
run literally concurrently (i.e. simultaneously
i.e. contemporaneously) as shown in some examples below...
Running NCSim with Verilog on a machine with four x86_64 cores (AMD Opterons)...
"top - 15:26:15 up 56 days, 20:29, 10 users, load average: 0.27, 0.14, 0.05
Tasks: 190 total, 3 running, 187 sleeping, 0 stopped, 0 zombie
Cpu0 : 52.2% us, 8.6% sy, 0.0% ni, 37.5% id, 0.7% wa, 0.0% hi, 1.0% si
Cpu1 : 93.4% us, 2.0% sy, 0.0% ni, 0.3% id, 4.3% wa, 0.0% hi, 0.0% si
Cpu2 : 72.1% us, 0.3% sy, 0.0% ni, 27.6% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu3 : 0.3% us, 0.0% sy, 0.0% ni, 99.7% id, 0.0% wa, 0.0% hi, 0.0% si
Mem: 8108556k total, 4594596k used, 3513960k free, 143932k buffers
Swap: 0k total, 0k used, 0k free, 3576148k cached
PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
3367 gloster 25 0 32128 16m 5440 R 99.5 0.2 0:06.16 ncsim
3300 petri 19 0 248m 159m 22m R 95.2 2.0 0:06.31 design_vision_e
31390 gloster 16 0 9620 1240 868 R 0.3 0.0 0:24.25 top"
Running NCSim with VHDL on a machine with four x86_64 cores (AMD Opterons)...
"top - 12:54:51 up 56 days, 17:57, 10 users, load average: 0.18, 0.08, 0.02
Tasks: 185 total, 2 running, 183 sleeping, 0 stopped, 0 zombie
Cpu0 : 1.7% us, 0.0% sy, 0.0% ni, 98.3% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu1 : 88.4% us, 0.0% sy, 0.0% ni, 11.6% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu2 : 0.0% us, 0.0% sy, 0.0% ni, 100.0% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu3 : 0.3% us, 0.0% sy, 0.0% ni, 99.7% id, 0.0% wa, 0.0% hi, 0.0% si
Mem: 8108556k total, 4263752k used, 3844804k free, 143896k buffers
Swap: 0k total, 0k used, 0k free, 3408576k cached
PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
31372 gloster 19 0 24916 10m 4700 R 88.3 0.1 0:02.71 ncsim
31390 gloster 16 0 9620 1212 864 R 0.7 0.0 0:00.10 top"
Running NCSim with VHDL on a machine with four Intel Xeon cores...
"top - 13:02:02 up 56 days, 17:31, 4 users, load average: 0.39, 0.14, 0.15
Tasks: 128 total, 2 running, 126 sleeping, 0 stopped, 0 zombie
Cpu0 : 0.7% us, 0.0% sy, 0.0% ni, 99.3% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu1 : 100.0% us, 0.0% sy, 0.0% ni, 0.0% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu2 : 0.3% us, 0.0% sy, 0.0% ni, 99.7% id, 0.0% wa, 0.0% hi, 0.0% si
Cpu3 : 0.0% us, 0.0% sy, 0.0% ni, 100.0% id, 0.0% wa, 0.0% hi, 0.0% si
Mem: 1034188k total, 650436k used, 383752k free, 18696k buffers
Swap: 2031608k total, 72320k used, 1959288k free, 328948k cached
PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
24994 gloster 25 0 24924 10m 4700 R 99.9 1.0 0:13.74 ncsim
24681 gloster 16 0 2152 1148 884 R 0.3 0.1 0:02.25 top"
In news:qgts635ef1r6kvl1vk0oqdmpmomseugodp@4ax.com timestamped Tue, 12
Jun 2007 12:00:51 +0100, Evan Lavelle <nospam@nospam.com> posted:
"[..]; SystemC, VHDL, and Verilog all provide user-level
concurrency, whatever hardware or OS they run on.
[..]
[..] If I can just repeat what I said, or tried to say, im my last post,
the issue of underlying concurrency support is just not relevant. HDL
simulation semantics are defined in such a way that everything happens
*sequentially*, in such a way that *models*, or simulates,
"concurrency". This is true of any HDL that I know about."
Once again I point out to you that providing the user with only one
conceptually running task and forcing the user to manually switch the
simulation from one task to another -- which is exactly what is forced
upon the user by SystemC(R) cooperative multitasking -- is not
user-level concurrency (though an optimizer might be able to find a
way to replace the source code with concurrent parts). This is unlike
the user-level perception of VHDL with processes whose interleaving is
a job for the simulator. It is true that inside a VHDL process one can
have sequential code, but the relationship between one VHDL process
and another VHDL process can be one of concurrency at the user-level,
which is not a SystemC(R) possibility at the user-level because
nothing in the SystemC(R) standard involves user-level concurrency.
"[..]
>[..] However, I am not aware of a SystemC(R)
>implementation (aside from synthesizers of course) which actually
>exploits concurrent hardware (e.g. a multiprocessor workstation).
I'm not either, but that doesn't mean that it hasn't been done, or is
not possible."
I had already admitted this in news:f4bcqk$lon$1@newsserver.cilea.it .
" Are you aware of any VHDL or Verilog implementations
which exploit 'concurrent hardware'? Yes, I'm sure there are trivial
examples of multi-threaded simulators, but are you aware of any
simulators which assign processes to threads? I'm not."
No, I am not aware of any industrial simulators which do this. In the
Cadence NCSim examples above, not much of the available processing
power was exploited.
"[..] Besides, it would generally be pointless; any
realistic simulation runs a vast number of "simultaneous" "concurrent"
processes, and you need special-purpose hardware to make any sense of
that."
Quite a lot of people write software which runs on multiprocessor
computers with a task which runs on one processor at the same
time as other tasks of the same software's run on other processors,
with some of these tasks interacting.
"[..] If you're
really smart, you can try to take advantage of 'parallel' hardware to
run multiple processes simultaneously, but it's difficult."
True.
">If
>you check one of the forums on SystemC.org you can notice people who
>were not pleased that their OSCI simulators would use just one
>operating system process.
I've been following these forums for years, and I don't recall any
specific discussions on this."
Some examples (N.B. to other people, a password is required for all of
these webpages)...
From
WWW.SystemC.org/forum/forum.php?thread_id=3757&forum_id=15
:"[..]
By: Larry Whitley
Subject: sc model thread <-> system thread[ Reply ]
Date: 2006-08-21
[..]
I'll set the console into raw mode and use getchar() to wait for and
receive characters typed at the console. If I do this in a systemc
thread (a pthread) the model appears to stop executing while
getchar() waits for the next key to be hit. Thus the need for an
external system thread.
[..]
By: Vincent Viteau
Subject: RE: sc model thread <-> system thread[ Reply ]
Date: 2006-08-22
Hi Larry, If I understood right, I would have done something
similar. This was not about a console but graphical display. So I had
my SystemC model and a part of it was a graphical monitor and
capture. These last 2 elements were X windows supposed to interact
with the user. First I just did everything from SystemC but my problem
was that SystemC engine only executes in pure sequence and suspends
non active threads. This was not good: 1. to refresh the X windows
when necessary, 2. to properly capture all the user actions.
To address this, I used pthread threads. [..]
[..]"
From
WWW.SystemC.org/forum/forum.php?thread_id=3959&forum_id=15
:"[..]
By: Paco Blasco
Subject: Running SystemC on multiprocessor computer[ Reply ]
Date: 2006-12-15
Hi all: I'm developing some SystemC complex simulation, and I've
noticed that SystemC only use one processor becouse it appears to be
a monothread application. Pthreads/Fibers or QuickThreads maintain
only on thread (or fiber ) active each time. Is it possible to use
the full performace of a quad processor computer? Are the "control"
data of the kernel of systemc thread-safe? I want to modify the
"crunch" method of sc_simcontext to provide a concurrent method and
thread execution.
[..]"
In news:qgts635ef1r6kvl1vk0oqdmpmomseugodp@4ax.com timestamped Tue, 12
Jun 2007 12:00:51 +0100, Evan Lavelle <nospam@nospam.com> posted:
"[..]
You would use (TM) in normal usage. But my point was that the word
"Verilog" is also trademarked. I'm sure that we could have a Verilog
discussion without continuously referring to "Verilog(R)" or
Verilog(TM)"."
Whether or not "Verilog" is trademarked is irrelevant. The OSCI
expressly forbade in a license to me particular ways of using
"SystemC". I have noticed that you have an account of SystemC.org. How
did you get this account without consenting to the terms I mentioned?
"Everybody else calls it "SystemC"."
Not everybody else has agreed to abide by the OSCI's rules. People who
do not have a SystemC.org account nor a copy of anything from the OSCI
are not obliged to comply with the OSCI's rules.
Regards,
Colin Paul Gloster
Article: 120680Maxascent, It is unclear on what you mean by powering the "configuration block" to 3.3V. You can power Vcco_0 (aka Vcco_config) to 3.3V. Be sure to read the V4 Configuration UG (see pg 15) on the requirements for all the dedicated configuration input pins and other requirements based on your configuration mode. http://direct.xilinx.com/bvdocs/userguides/ug071.pdf -David "maxascent" <maxascent@yahoo.co.uk> wrote in message news:vKednZYqqrRLZPLb4p2dnAA@giganews.com... > > Hi > > Could someone just confirm for me that I can connect the config block to > 3.3V in a Virtex 4 device. I have checked the data sheet and it seems to > indicate this. I just want to check as I have been using Virtex 2 Pro > devices which need to be 2.5V. > > JonArticle: 120681
"ZR1TECH" <ZR1TECH@gmail.com> wrote in message news:1181746373.904760.157640@d30g2000prg.googlegroups.com... > Is it possible to post a picture a diagram on here? > > **** ** ******* /**/** /** **/////** /**//** /** ** //** /** //** /**/** /** /** //**/**/** /** /** //****//** ** /** //*** //******* // /// /////// :-)HTH, Syms.Article: 120682
ZR1TECH wrote:
> Is it possible to post a picture a diagram on here?
Maybe a pointer to a diagram.
http://www.altera.com/products/ip/ampp/commstack/images/m-com-dpll_fig1.gif
-- Mike Treseler
Article: 120683I am not entiry sure what the little protection chip does with 2 outputs, hence the bodge... Seems to work though. If anyone knows whats in it I would be most interested! /Mike "Mark McDougall" <markm@vl.com.au> wrote in message news:467002e8$0$22457$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > MikeJ wrote: > >> Pleased to announce the release of Frogger and Scramble (with source >> code) at www.fpgaarcade.com. > > Cool! You also have the Scramble protection I see - that had me beat... > I'm guessing that since the equations are now public, then there's no > reason why MAMEDEV can't be given that information to replace the dodgy > hack that's in the Scramble driver atm? > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 >Article: 120684
This is not the first time I ask for this problem, but at the moment I go on trying to solve this problem. I have a custom board with a Micron memory. The company has said to me that I should use a xilinx core but I have to modify this because they said that their memories use internal loopback. I have tried to modify these signals but this doesn't work. Finally I have decide to implement the core neccesary for this but I don't know how could I integrate this with xps, since I need to use XMD for PowerPC debug. So, I need some recommendation about how to create a core for my DDR Sdram and integrate in my PowerPC model (in XPS) so I could use XMD for download the application in this memory. RegardsArticle: 120685
"Pablo" <pbantunez@gmail.com> wrote in message news:1181755261.328091.228890@i38g2000prf.googlegroups.com... > > I have a custom board with a Micron memory. The company has said to me > that I should use a xilinx core but I have to modify this because they > said that their memories use internal loopback. I have tried to modify > these signals but this doesn't work. > If I understand your question correctly, take a look at the reference design at the link below. It shows how to close the feedback loop internally. I guess, depending on the hardware, you might need to introduce some delay in this path... http://www.digilentinc.com/Data/Products/FX12/FX_12_BIST_Clean.zip > Finally I have decide to implement the core neccesary for this but I > don't know how could I integrate this with xps, since I need to use > XMD for PowerPC debug. > > So, I need some recommendation about how to create a core for my DDR > Sdram and integrate in my PowerPC model (in XPS) so I could use XMD > for download the application in this memory. XMD has nothing to do with the core. What exactly are you going to implement? Integrating a peripheral into XPS isn't that difficult. Copy the PLB_DDR core from the %Xilinx_EDK\hw\XilinxProcessorIPLib\pcores\ directory into your projects pcores directory and edit the source files however you want. Restart XPS or rescan project repositories, XPS will pick up the local version of the core instead of the one in the EDK tree. /MikhailArticle: 120686
rickman wrote: > On Jun 12, 1:52 pm, Antti <Antti.Luk...@googlemail.com> wrote: > >>Xilinx does use digikey, so they also have NO MINIMUM order. >> >>I see no difference here, BOTH ARE BAD in that sense that the latest >>and greatest silicon is NOT AVAILABLE. >> >>not from Xilinx online, not from Lattice online. >> >>Lattice could do an example here, and OFFER IMMEDIATE 1 OFF XP2 >>example ONLINE orders >> >>I bet most people would instanlty order. >> >>just 1 per customer, GIFT PACKAGED XP2 sample. One click order, no >>questions, just PAY and get it. >> >>but eh, one can always dream... I do >> >>well, while dreaming that Xilinx/Lattice would improve their online >>store to include ES silicon, guess what I am designed in? Actel PA3, >>gee the QFN132 package is real nice one, glad to see XP2 includes this >>package as well. To Lattice, I would have preferred XP over PA3, but >>there was no tiny package available. Xilinx, same words: S3AN in >>QFN132 would win many designs over MAX2,machXO,PA3,XP2... but S3AN >>only has big ugly packages :( > > > The reason that engineering samples are not available through online > ordering is because this is a critical phase for a manufacturer and > they want two things; one is to know who the customers are so they can > learn as much as possible about the customer and application > (including the sales potential, which is crucial and gets reported up > the food chain) and to be able to provide support, sometimes in a > proactive way. With new parts, FPGA makers prefer to give out early > engineering samples to the companies with larger potential and more > experience. The support a company can offer has a finite limit, so > they want to make sure their biggest customers are successful first, > then they can go after the smaller buyers. > > You have to consider the vendor's position and give them a little > slack on early sampling. If they don't meet their goals in this early > stage, it can doom a product that may never catch up! > That can backfire, big time. Many vendors think that only large companies matter and fail to see that it's often the little guys like us consultant who really call the shots. Meaning their (big) client's engineers trust their decision and stick with it. I've had sales guys literally beg me to reconsider but in pretty much all cases it was too late. When the work is done a consultant cannot saddle a client with more NRE just because a vendor shows remorse about not having supported what they thought was "only a little guy". A lot of companies, including nearly all European semi mfgs, don't even know what they have missed out on so far. Never will. -- Regards, Joerg http://www.analogconsultants.comArticle: 120687
On Jun 11, 11:51 pm, Andy <jonesa...@comcast.net> wrote: > On Jun 11, 12:31 pm, Wei Wang <camww...@gmail.com> wrote: > > > On Jun 11, 12:46 pm, Jon Beniston <j...@beniston.com> wrote: > > > > > I'm trying to think hard how design compiler and synplify pro differ > > > > with each other from a user's point of view, for example, synthesizing > > > > for xilinx virtex fpga. Any inputs would be grateful. > > > > Synplify Pro will give you better results. > > > > Cheers, > > > Jon > > > any review articles comparing those two products? pointers to those > > articles would be greatly appreciated. > > Synplify Pro only works for FPGAs > > Synopsys DC only works for ASICS. > > What's to compare? Synplify Pro has better language coverage for VHDL, > but other than that, it all boils down to the features of the target > implementation, and not so much about the tool. > > Back when Synopsys FPGA Compiler II was around we compared it to > Synplify Pro, targeting Xilinx FPGAs, and SP won hands down in QOR, > run time, ease of use, language (vhdl) coverage, virtually everything, > including cost. I don't recall a single category that FC2 beat SP. > There were a handful of corner cases where FC2 gave a better (faster/ > smaller) implementation than SP, but there were many more for which > the SP implementation was better than FC2. > > Andy Thanks for your inputs, Andy. From your comments, it looks like I am using the right tool, I've recently found a problem (not quite sure whether it is a "feature" ) with Synplify Pro. The latest version of Synplify Pro [8.8.0.4] overconstraints the timing of the design and the 8.4 version had the problem of confusing itself with DIFFM/DIFFS and IOB, the idea of comparing those two tools was to find a backup when one tool fails I can still try the other one.Article: 120688
I'm afraid that you are, and I'm trying to be polite here, completely wrong. SystemC does not operate the way that you think it does, and neither do VHDL nor Verilog. All three define simulation semantics in what is fundamentally exactly the same way. Some simple Googling might convince you. Look up any thread that discusses an endless loop which hangs up a Verilog or VHDL simulator. How is this even possible with your world view? 2 minutes on Google found a simple explanation of how event-driven simulation works, from Janick Bergeron. This is exactly what I've said several times in this thread, but you may find it more believable from Janick; see http://groups.google.co.uk/group/comp.lang.vhdl/browse_frm/thread/3941f0c5edac84fa/ae8567e741594acb?lnk=st&q=endless+loop+group%3Acomp.lang.vhdl&rnum=6&hl=en#ae8567e741594acb I quote: >Because simulators must emulate things that occur in parallel on a >single thread machine, they must perform something similar to >timesharing on the workstation you probably use. Each process gets the >simulation engine (CPU) and runs until it explicitely suspends itself >via a wait statement. Because all processes are run in a sequential >fashion (since there is only 1 CPU), time must not advance between >evaluation. If signals are assigned in zero-time, time must not >advance for the next cycle either. > >Because simulators are not timeshared and assume that every process >will cooperate and release the engine eventually, you might get stuck >if a process fails to execute a wait statement. It is to prevent this >common mistake and give an indication as to what is going wrong that >some simulators have a delta cycle limit that cause a *break* when >that limit is reached, not a time advance. This really is pretty basic. Janick wrote this 12 years ago, so the details of single-processor/single-thread have changed, but the basics are exactly correct. I'm happy to discuss this with you if you have a specific objection, or can demonstrate that the SystemC kernel does not also behave in this way (and it most emphatically *does*), but it really isn't helpful to add lots of irrelevant extras when replying to posts. EvanArticle: 120689
>On Jun 10, 2:38 pm, "cutemonster" <ckh...@hotmail.com> wrote: >> >So you want to display a stroke signal on monitor? >> >Why you need to sample the X? Is it time dimension? Is it a constant >> >ramping, or ramping with retrace, or random? >> >> I have to sample x and y because it doesn't work like raster signal. It's >> voltage varies in time. There is another signal input called Unblank(TTL). >> It turn on and off of XY signal. > >Have you tried to lock the sampling clocks to the unblank? > > No, I don't understand how to lock it with sampling clock. Can you please explain? thanksArticle: 120690
On Jun 13, 3:09 pm, "cutemonster" <ckh...@hotmail.com> wrote: > >On Jun 10, 2:38 pm, "cutemonster" <ckh...@hotmail.com> wrote: > >> >So you want to display a stroke signal on monitor? > >> >Why you need to sample the X? Is it time dimension? Is it a constant > >> >ramping, or ramping with retrace, or random? > > >> I have to sample x and y because it doesn't work like raster signal. > It's > >> voltage varies in time. There is another signal input called > Unblank(TTL). > >> It turn on and off of XY signal. > > >Have you tried to lock the sampling clocks to the unblank? > > No, I don't understand how to lock it with sampling clock. Can you please > explain? > > thanks Locking the clock to the unblank meaning that their phase relation is fixed. For some reason I can't escape from the time dimension :) If you just sample for 1 frame then probably you don't need to do locking. Do you sample just 1 image then display it continuously on the raster? If you capture it as live video or multiple frames, then how can you tell which pixels belong to frame n, which belong to frames n+1, n +2,... Regards,Article: 120691
Hello, I was wondering if anyone is using Incremental Compilation in Quartus 7.1 and if so, could you comment on it. Is it worth the time using IC or is doing Full Compilation better. In my current design I'm only using about 6% of the logic, does IC make sense in this case? If anyone has some opinions on IC please share them. thanks, joeArticle: 120692
Hi everybody, i' trying to realize a custom OPB peripheral using EDK. In my design I need a register in which one bit should be written by software and by the peripheral itself. Ok... I'll try to explain it better. I would like to set a bit of one register from software to tell the peripheral to start to work. When it has finished, i'd like that the peripheral sets to ' 0 ' the same bit in order to communicate that the work is done. In this way setting again the bit to ' 1 ' the peripheral will start to workagain, and so on. The problem is: when I syntethize the peripheral I got the error: Multi-source in Unit <user_logic> on signal <slv_reg3(0)> I think it's due to the fact that the bit is written by the bus (via software) and by the peripheral... How can i fix this problem? It seems that the SW register of the OPB peripherals in EDK can't be written by the peripheral itself (this means that it's useless to try to read that register from software).... How can I get information from software about the peripheral if the register can't be written by the periperal? I'm quite new to this stuff and I hope my problem is clear (despite of my poor english) Thanks a lot, A.Article: 120693
jjlindula@hotmail.com wrote:
> Hello, I was wondering if anyone is using Incremental Compilation in
> Quartus 7.1 and if so, could you comment on it. Is it worth the time
> using IC or is doing Full Compilation better.
I don't mind letting my computer do extra work
as long as it doesn't take too long.
So far, it doesn't take too long,
so I keep it simple.
-- Mike Treseler
Article: 1206949.1 SP3 on XP. I can open my project from the "File" dialog, but if I try double-clicking the ISE file I get: "The project ... you are attempting to open does not have write permissions and therefore cannot be opened in Project Navigator. This could have occured if the project was attempted to be opened in an earlier version of ISE software. In order to open the project, you must either change the permissions of the project file or make a writable copy of the project file." Unfortunately the eroor message doesn't tell me how to do either of these things, and I can't find anything on this in the help.Article: 120695
Pete, I can double click on my .ise file and can launch the GUI. A couple of things that you may want to check out. Look at the properties of the .ise file and verify that Read-only is not selected. Also verify that the file type associated with the .ise file is Xilinx ISE Project. Let me know how it goes. -David "Pete Fraser" <pfraser@covad.net> wrote in message news:1370uhsmqceu619@news.supernews.com... > 9.1 SP3 on XP. > > I can open my project from the "File" dialog, > but if I try double-clicking the ISE file I get: > > "The project ... you are attempting to open does > not have write permissions and therefore cannot > be opened in Project Navigator. > > This could have occured if the project was > attempted to be opened in an earlier version > of ISE software. > > In order to open the project, you must either > change the permissions of the project file or > make a writable copy of the project file." > > Unfortunately the eroor message doesn't tell > me how to do either of these things, and I can't > find anything on this in the help. >Article: 120696
"davide" <davide@xilinx.com> wrote in message news:f4pvvu$arf2@cnn.xilinx.com... > Pete, > > I can double click on my .ise file and can launch the GUI. A couple of > things that you may want to check out. Look at the properties of the .ise > file and verify that Read-only is not selected. I checked that. Assuming you're talking about the Windows properties, that was OK. > Also verify that the file type associated with the .ise file is Xilinx ISE > Project. Let me know how it goes. It may be that ProjNav still has a problem with long paths or spaces in directory names. I moved the folder from the desktop, and it seems OK now. ThanksArticle: 120697
On Jun 13, 5:12 pm, Andrea05 <c...@email.it> wrote: > I would like to set a bit of one register from software to tell the > peripheral to start to work. When it has finished, i'd like that the > peripheral sets to ' 0 ' the same bit in order to communicate that the > work is done. In this way setting again the bit to ' 1 ' the > peripheral will start to workagain, and so on. > > The problem is: when I syntethize the peripheral I got the error: > > Multi-source in Unit <user_logic> on signal <slv_reg3(0)> Two simple choices: 1) Implement the by by instantiating the vendor's flip flop with clear. Processor drives data and enable, peripheral drives clear. 2) Describe the desired behaviour of a register: At clock transition if processor is writing, set to 1. Else if peripheral is done, set to 0. Otherwise, do nothing... That's assuming you are willing to follow a rule in software of never writing the bit without first checking to make sure its cleared. And assuming your peripheral can't clear it until at least a few clocks after it's been set. And assuming your processor and peripheral share a clock; if any of these aren't true, it's a little more complicated.Article: 120698
I've done this exact thing in a couple IP cores. All that follows
assumes that you are using the Create and Import Peripheral Wizard's
template modules. I use the verilog stub logic (user_logic.v) so if
you use VHDL, you will have to figure out the coding differences.
The first assumption that I made was that the software would set the
bit and then wait until that bit is cleared before doing anything else
(usually a while loop). The IP core gets triggered by the register
bit being set to a 1. The core goes off and does its thing. When it
is done, and the trigger bit needs to be cleared, I assert a signal
(from the IP core) high for several clock cycles. An additional 'else
if' statement is added to the slave register implementation in the
user_logic module such that, at the assertion of the aforementioned
signal, the register is written with whatever you want to put in
there. In this case, you just want to clear a bit so you can set that
to 0, or just set the whole thing to 0 if you don't care about the
other bits. If you have set up the software correctly it will 'see'
that the bit is cleared and go on and do its thing. If you are
immediately writing the trigger bit to a 1 after it is cleared, you'll
have to be sure that your IP is done 'pushing' data into the register
before the OPB tries to write to it. If simple guesswork fails,
simulation can help figure out the timing.
I have done this when the OPB clock and the IP clock are the same and
when they are different. If they are different, you just have to sync
the IP signal into the OPB clock domain before you use it to push data
into the slave register. The following is a snippet of code for the
slave register (common clocks):
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
end
else if (push_frame_count_out_i == 1) ----> this is the
signal from the IP that stays high for a few clocks (I think 4)
begin
slv_reg0 <= {16'b0, frame_count_out_i}; -----> we clear
the 1st bit (15 more bits of 0 don't matter) and put a count in the
register. The software can get the
end
count when it sees the 1st bit is cleared.
else ---------> the rest of the register code follows this,
unaltered from the template.
Hope this helps. It is a pretty easy and usable way to do what you
are trying to do.
Article: 120699
Sorry. Formatting screwed up : )
Here's the code without comments.
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
end
else if (push_frame_count_out_i == 1)
begin
slv_reg0 <= {16'b0, frame_count_out_i};
end
else
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