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Gene S. Berkowitz wrote: > According to the manufacturer (Century Corp, Japan), it stripes the data > across the multiple cards to speed up access (you must install cards in > pairs). My statement stands. You can do all that in a single CPLD... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 120951
Andy is right, I myself had to design my custom board (three years ago) while playing with real time image processing. If you want an efficient solution. Try Hunt engineering board (Hunt- RTG-005), which is a ready to go module and will provide you a high speed USB interface along with camera link. regards MH On Jun 20, 2:07 pm, Marek Kraft <sepher_gr...@o2.pl> wrote: > Hello! > > I have been playing with image processing on FPGA for some time now, > and the results seem interesting (I am working mainly on image > preprocessing and edge/corner detection algorithms). My main research > platform was the S3BOARD from Digilent/Xilinx, but I got to the point, > where RS232, or RS232 <-> USB converters do not offer sufficient speed > (imagine sending a 512x512 image to the board and then waiting for the > results, even in grayscale). Therefore, I'd like to invest some money > in a more advanced evaluation board. For now, the Virtex-4-based Video > Starter Kit seems to be the most reasonable choice for me. Is anyone > here using this kit? The opinions I have found while googling the net > (like the one here:http://www.embeddedrelated.com/usenet/embedded/show/54852-1.php) > are however somewhat disencouraging. I'd like to know if it's hard to > develop my own applications for the daughtercard without having to use > the Matlab/Simulink software (just plain HDL). I also tried to find > some other boards for this task (a solution that is functioning out-of- > the-box would be ideal). The price of boards by Vmetro and > Hitechglobal is an overkill for me. I considered also buying the > XUPV2P board from Digilent design a CameraLink compatible interface > for it, but I fear that V2Pro devices are a bit outdated and Xilinx > will stop supporting this product line. I'd also like to know if it is > better to use dedicated National Semiconductor chips to do the > deserialization, or try to use the IOB/multiple clocks based approach? > Thanks for any suggestions.Article: 120952
Hello John, Thank you for you quick reply! To be specific, my program is related to 3D image reconstruction. The input data is float point numbers in the form of 3D array. I represent it using symbol: g(x1,y1,z1), while the number of x1,y1,z1 are quite large. The output data is another 3D float point array. I represent it using symbol: F(x2,y2,z2), similarily the number of x2,y2,z2 are also quite large. The estimated memory usage is 2GB or so, while the calculations required is listed below: integer addition 2442 Giga operations per second float add 814 Giga operations per second float substrac 2424 Giga operations per second float muliply 1610 Giga operations per second float divide 809 Giga operations per second I want these calculations done in one minite, so we can divide the operations by 60. As a matter of fact, if the calculations could be done in 5 minites, it is OK for me. So for minimum requirment, divide the above numbers by 300(=60*5). And your suggestion?Article: 120953
Hello glen: Please refer to my reply to John. There is no problem about the budget. And I prefer to get the whole calculations done in 10 minites as I have said in my reply to John.Article: 120954
I know this topic has been already treated but at the moment I have no solution yet. Is it possible to edit this opencore so you could use internal feedback?.Article: 120955
On Jun 21, 9:27 am, Mark McDougall <m...@vl.com.au> wrote: > Gene S. Berkowitz wrote: > > According to the manufacturer (Century Corp, Japan), it stripes the data > > across the multiple cards to speed up access (you must install cards in > > pairs). > > My statement stands. You can do all that in a single CPLD... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Mark, it depends on your definition of CPLD, if you mean CPLD as Complex PLD, not FPGA then, well it may be still doable, but very unreasonable as the price of CPLDs increases very quickly above 64MC. If you say that an FULL ATA compliant high speed multi SD in parallel optimized interface can be done "cost effectivly" in simple CPLD, then this is something that I would say is not so. OR if you are able to implement it, then I should maybe buy an hat. (so that I can take it off, should I meet you). the PCB as on picture sure is using an overkill of components, but replacing them with and small CPLD is also not possible. However an 3USD FPGA maybe already be able todo the task. AnttiArticle: 120956
On Jun 21, 12:17 pm, Pablo <pbantu...@gmail.com> wrote: > I know this topic has been already treated but at the moment I have no > solution yet. > Is it possible to edit this opencore so you could use internal > feedback?. everything is possible, and the impossible becomes possible - when you do it. AnttiArticle: 120957
On 21 jun, 12:37, Antti <Antti.Luk...@googlemail.com> wrote: > On Jun 21, 12:17 pm, Pablo <pbantu...@gmail.com> wrote: > > > I know this topic has been already treated but at the moment I have no > > solution yet. > > Is it possible to edit this opencore so you could use internal > > feedback?. > > everything is possible, and the impossible becomes possible - when you > do it. > > Antti Just do it!. Of course I am trying to do it, but any help is very grateful at least for someone like me. At the moment I am trying to use this core without any modification, but anything works at the first time. That is the reason why I look for help while I am working with it. Anyway, thanks for the answer. It is a very philosophical phrase.I thinkthat I am going to copy it. Regards PabloArticle: 120958
On a sunny day (Thu, 21 Jun 2007 17:27:08 +1000) it happened Mark McDougall <markm@vl.com.au> wrote in <467a2875$0$22415$5a62ac22@per-qv1-newsreader-01.iinet.net.au>: >Gene S. Berkowitz wrote: > >> According to the manufacturer (Century Corp, Japan), it stripes the data >> across the multiple cards to speed up access (you must install cards in >> pairs). > >My statement stands. You can do all that in a single CPLD... > >Regards, Agreed, was my idea too.Article: 120959
On Jun 21, 1:01 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > On a sunny day (Thu, 21 Jun 2007 17:27:08 +1000) it happened Mark McDougall > <m...@vl.com.au> wrote in > <467a2875$0$22415$5a62a...@per-qv1-newsreader-01.iinet.net.au>: > > >Gene S. Berkowitz wrote: > > >> According to the manufacturer (Century Corp, Japan), it stripes the data > >> across the multiple cards to speed up access (you must install cards in > >> pairs). > > >My statement stands. You can do all that in a single CPLD... > > >Regards, > > Agreed, was my idea too. its of course nice idea :) if the functionality could be easily implemented in small simple PLD, then this CPLD could be sold as competing product to: http://www.zentek.co.jp/product_sd_cg200.htm or? I personally would instantly buy this IP (IDE-SD interface that can fit into CPLD), but it is a little more than "simple PLD" to achive this, so I dont expect this to be available. Antti PS, hm just recalled, I have made a MMC (MMC mode, not SPI) mode IP core that can configure FPGA from MMC card, this IP core does take 21 Macrocells (coolrunner-2), other technologies 22 MC. So I think I know what function takes what resources in CPLD/FPGA. A high performance standard compliant IDE-SD interface is not fittable into CPLD (standard CPLD, not counting the cross-over products like machXO/MAX- II to CPLD's)Article: 120960
On Jun 21, 12:58 pm, Pablo <pbantu...@gmail.com> wrote: > On 21 jun, 12:37, Antti <Antti.Luk...@googlemail.com> wrote: > > > On Jun 21, 12:17 pm, Pablo <pbantu...@gmail.com> wrote: > > > > I know this topic has been already treated but at the moment I have no > > > solution yet. > > > Is it possible to edit this opencore so you could use internal > > > feedback?. > > > everything is possible, and the impossible becomes possible - when you > > do it. > > > Antti > > Just do it!. > > Of course I am trying to do it, but any help is very grateful at least > for someone like me. > > At the moment I am trying to use this core without any modification, > but anything works at the first time. > That is the reason why I look for help while I am working with it. > > Anyway, thanks for the answer. It is a very philosophical phrase.I > thinkthat I am going to copy it. > > Regards > Pablo ;) gee. the thing is that getting some DDR memory IP to working on platform XYZ may require more work then just changing clock feadback. you should not expect some one todo this for you, unless its paid contract work. the memory cores sometimes work out of box, sometimes it maybe months of hard fight to get them working. Example Xilinx DDR IP Core. you route clock feadback to clock capable io xxxx_N you get NO ERROR REPORT, all time is fine, you look all path in FPGA editor, everything is 100% fine. but the DDR memory core just DOES NOT WORK. now you change the clock feadback to IOPAD xxxx_P, and everything works. but there is no noticeable difference in any routing or timing reports. of course, if you read Xilinx datasheets, then you also can see that you MUST use _P pad. but there are many ways to obtain this kind of knowledge. some of them are hard and painful. and our mileage may vary a great deal. my toys at age of 1.5 (in 1967) where metal can GE transistors, so its long path behind. thats why I take the freedom to be sometimes little philosofical, in replies to deep technical questions. Antti some more wisdom from me (had to use web.archive as domain is expired) http://web.archive.org/web/20020427224009/http://case2000.com/R.O.L/Article: 120961
On a sunny day (Thu, 21 Jun 2007 11:09:30 -0000) it happened Antti <Antti.Lukats@googlemail.com> wrote in <1182424170.300639.18270@c77g2000hse.googlegroups.com>: >On Jun 21, 1:01 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: >> On a sunny day (Thu, 21 Jun 2007 17:27:08 +1000) it happened Mark McDougall >> <m...@vl.com.au> wrote in >> <467a2875$0$22415$5a62a...@per-qv1-newsreader-01.iinet.net.au>: >> >> >Gene S. Berkowitz wrote: >> >> >> According to the manufacturer (Century Corp, Japan), it stripes the data >> >> across the multiple cards to speed up access (you must install cards in >> >> pairs). >> >> >My statement stands. You can do all that in a single CPLD... >> >> >Regards, >> >> Agreed, was my idea too. > >its of course nice idea :) >if the functionality could be easily implemented in small simple PLD, >then this CPLD could be sold as competing product to: > >http://www.zentek.co.jp/product_sd_cg200.htm > >or? > >I personally would instantly buy this IP (IDE-SD interface that can >fit into CPLD), but it is a little more than "simple PLD" to achive >this, so I dont expect this to be available. > >Antti > >PS, hm just recalled, I have made a MMC (MMC mode, not SPI) mode IP >core that can configure FPGA from MMC card, this IP core does take 21 >Macrocells (coolrunner-2), other technologies 22 MC. So I think I know >what function takes what resources in CPLD/FPGA. A high performance >standard compliant IDE-SD interface is not fittable into CPLD >(standard CPLD, not counting the cross-over products like machXO/MAX- >II to CPLD's) OK, FPGA, actually I was thinking that first. But make no mistake: what part is [in] the 'driver' and what part is the CPLD [FPGA]. Maybe with some clever doing you could make the hardware part very simple.Article: 120962
On 21 jun, 13:19, Antti <Antti.Luk...@googlemail.com> wrote: > On Jun 21, 12:58 pm, Pablo <pbantu...@gmail.com> wrote: > > > > > On 21 jun, 12:37, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On Jun 21, 12:17 pm, Pablo <pbantu...@gmail.com> wrote: > > > > > I know this topic has been already treated but at the moment I have no > > > > solution yet. > > > > Is it possible to edit this opencore so you could use internal > > > > feedback?. > > > > everything is possible, and the impossible becomes possible - when you > > > do it. > > > > Antti > > > Just do it!. > > > Of course I am trying to do it, but any help is very grateful at least > > for someone like me. > > > At the moment I am trying to use this core without any modification, > > but anything works at the first time. > > That is the reason why I look for help while I am working with it. > > > Anyway, thanks for the answer. It is a very philosophical phrase.I > > thinkthat I am going to copy it. > > > Regards > > Pablo > > ;) gee. > > the thing is that getting some DDR memory IP to working on platform > XYZ may require more work then just changing clock feadback. > you should not expect some one todo this for you, unless its paid > contract work. > > the memory cores sometimes work out of box, sometimes it maybe months > of hard fight to get them working. > > Example > > Xilinx DDR IP Core. > > you route clock feadback to clock capable io xxxx_N > you get NO ERROR REPORT, all time is fine, you look all path in FPGA > editor, everything is 100% fine. > but the DDR memory core just DOES NOT WORK. > > now you change the clock feadback to IOPAD xxxx_P, and everything > works. > but there is no noticeable difference in any routing or timing > reports. > > of course, if you read Xilinx datasheets, then you also can see that > you MUST use _P pad. > > but there are many ways to obtain this kind of knowledge. some of them > are hard and painful. > > and our mileage may vary a great deal. > my toys at age of 1.5 (in 1967) where metal can GE transistors, so its > long path behind. > > thats why I take the freedom to be sometimes little philosofical, in > replies to deep technical questions. > > Antti > some more wisdom from me (had to use web.archive as domain is expired)http://web.archive.org/web/20020427224009/http://case2000.com/R.O.L/ I don't expect that someone does this for me. I only request for some help. I have some idea about how try to solve it but at the moment I am trying to implement a project with this core and a basic vhdl file to read and write in memory. Then if this doesn't work I would try some ideas to do it. This vhdl basic file is what I don't know how to build it. BUt I suppose most people has already done this and I request for their help in which experiencies has taken. PD: Sorry for my English, it is not as perfect as I wish. To finish this topic I want to say that if I request for some help is because I help to anyone who want to ask me. Once again, thanks for answer me and sorry if my question has bothered you. Regards PabloArticle: 120963
On Jun 21, 1:44 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > On a sunny day (Thu, 21 Jun 2007 11:09:30 -0000) it happened Antti > <Antti.Luk...@googlemail.com> wrote in > <1182424170.300639.18...@c77g2000hse.googlegroups.com>: > > > > > > >On Jun 21, 1:01 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > >> On a sunny day (Thu, 21 Jun 2007 17:27:08 +1000) it happened Mark McDougall > >> <m...@vl.com.au> wrote in > >> <467a2875$0$22415$5a62a...@per-qv1-newsreader-01.iinet.net.au>: > > >> >Gene S. Berkowitz wrote: > > >> >> According to the manufacturer (Century Corp, Japan), it stripes the data > >> >> across the multiple cards to speed up access (you must install cards in > >> >> pairs). > > >> >My statement stands. You can do all that in a single CPLD... > > >> >Regards, > > >> Agreed, was my idea too. > > >its of course nice idea :) > >if the functionality could be easily implemented in small simple PLD, > >then this CPLD could be sold as competing product to: > > >http://www.zentek.co.jp/product_sd_cg200.htm > > >or? > > >I personally would instantly buy this IP (IDE-SD interface that can > >fit into CPLD), but it is a little more than "simple PLD" to achive > >this, so I dont expect this to be available. > > >Antti > > >PS, hm just recalled, I have made a MMC (MMC mode, not SPI) mode IP > >core that can configure FPGA from MMC card, this IP core does take 21 > >Macrocells (coolrunner-2), other technologies 22 MC. So I think I know > >what function takes what resources in CPLD/FPGA. A high performance > >standard compliant IDE-SD interface is not fittable into CPLD > >(standard CPLD, not counting the cross-over products like machXO/MAX- > >II to CPLD's) > > OK, FPGA, actually I was thinking that first. > But make no mistake: what part is [in] the 'driver' and what part is the > CPLD [FPGA]. > Maybe with some clever doing you could make the hardware part very simple.- Hide quoted text - > > - Show quoted text - eh, if you read my replies, then I did not outrule this to be implementatble in "3 USD FPGA", there are not so many FPGA with <= 3 USD price tag. And yes fitting into to cheapest FPGA would require near-magical engineering, but could be doable. AnttiArticle: 120964
On Jun 21, 1:44 pm, Pablo <pbantu...@gmail.com> wrote: > On 21 jun, 13:19, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On Jun 21, 12:58 pm, Pablo <pbantu...@gmail.com> wrote: > > > > On 21 jun, 12:37, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On Jun 21, 12:17 pm, Pablo <pbantu...@gmail.com> wrote: > > > > > > I know this topic has been already treated but at the moment I have no > > > > > solution yet. > > > > > Is it possible to edit this opencore so you could use internal > > > > > feedback?. > > > > > everything is possible, and the impossible becomes possible - when you > > > > do it. > > > > > Antti > > > > Just do it!. > > > > Of course I am trying to do it, but any help is very grateful at least > > > for someone like me. > > > > At the moment I am trying to use this core without any modification, > > > but anything works at the first time. > > > That is the reason why I look for help while I am working with it. > > > > Anyway, thanks for the answer. It is a very philosophical phrase.I > > > thinkthat I am going to copy it. > > > > Regards > > > Pablo > > > ;) gee. > > > the thing is that getting some DDR memory IP to working on platform > > XYZ may require more work then just changing clock feadback. > > you should not expect some one todo this for you, unless its paid > > contract work. > > > the memory cores sometimes work out of box, sometimes it maybe months > > of hard fight to get them working. > > > Example > > > Xilinx DDR IP Core. > > > you route clock feadback to clock capable io xxxx_N > > you get NO ERROR REPORT, all time is fine, you look all path in FPGA > > editor, everything is 100% fine. > > but the DDR memory core just DOES NOT WORK. > > > now you change the clock feadback to IOPAD xxxx_P, and everything > > works. > > but there is no noticeable difference in any routing or timing > > reports. > > > of course, if you read Xilinx datasheets, then you also can see that > > you MUST use _P pad. > > > but there are many ways to obtain this kind of knowledge. some of them > > are hard and painful. > > > and our mileage may vary a great deal. > > my toys at age of 1.5 (in 1967) where metal can GE transistors, so its > > long path behind. > > > thats why I take the freedom to be sometimes little philosofical, in > > replies to deep technical questions. > > > Antti > > some more wisdom from me (had to use web.archive as domain is expired)http://web.archive.org/web/20020427224009/http://case2000.com/R.O.L/ > > I don't expect that someone does this for me. I only request for some > help. I have some idea about how try to solve it but at the moment I > am trying to implement a project with this core and a basic vhdl file > to read and write in memory. Then if this doesn't work I would try > some ideas to do it. > > This vhdl basic file is what I don't know how to build it. BUt I > suppose most people has already done this and I request for their help > in which experiencies has taken. > > PD: Sorry for my English, it is not as perfect as I wish. > > To finish this topic I want to say that if I request for some help is > because I help to anyone who want to ask me. > > Once again, thanks for answer me and sorry if my question has bothered > you. > > Regards > Pablo- Hide quoted text - > > - Show quoted text - you should not assume "most people have done xxx" you should not assume anything ;) as all assumptions tend to be false instead of "trying to learn" to be able "todo" things, start DOING them, you will learn on the way. Antti From laurent.pinchart@skynet.be Thu Jun 21 05:19:34 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!wn11feed!worldnet.att.net!208.48.142.85!newsfeed.news2me.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <467a6cd6$0$13850$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: How to simulate testbenches using the ISE simulator in linux Newsgroups: comp.arch.fpga Date: Thu, 21 Jun 2007 14:19:34 +0200 References: <1182116017.579060.135360@d30g2000prg.googlegroups.com> <4677c0e2$0$13852$ba620e4c@news.skynet.be> <1182273982.654732.238610@n15g2000prd.googlegroups.com> <4678fbc4$0$14235$ba620e4c@news.skynet.be> <1182352484.909159.317010@g4g2000hsf.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 16 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 8ccca12d.news.skynet.be X-Trace: 1182428374 news.skynet.be 13850 194.78.198.49:53305 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:132724 X-Received-Date: Thu, 21 Jun 2007 08:19:35 EDT (newsdbm02.news.prodigy.net) Duth wrote: [snip] > Hi Laurent, > > Thanks for helping out here. Just one comment in case you did not > know. The -instyle ise switch is not needed if you are not inside > ISE :). We just use this for out internal use for formatting the > messages better to show in the ise console in case you were wondering. The -intstyle was a left-over from copy&paste operations. Thanks for pointing it out. Laurent Pinchart From laurent.pinchart@skynet.be Thu Jun 21 05:23:40 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!news2.euro.net!feeder.news-service.com!feeder2.cambrium.nl!feed.tweaknews.nl!193.201.147.86.MISMATCH!news.astraweb.com!border1.a.newsrouter.astraweb.com!hwmnpeer01.ams!news.highwinds-media.com!kramikske.telenet-ops.be!nntp.telenet.be!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <467a6dcc$0$13850$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: How to simulate testbenches using the ISE simulator in linux Newsgroups: comp.arch.fpga Date: Thu, 21 Jun 2007 14:23:40 +0200 References: <1182116017.579060.135360@d30g2000prg.googlegroups.com> <4677c0e2$0$13852$ba620e4c@news.skynet.be> <1182273982.654732.238610@n15g2000prd.googlegroups.com> <4678fbc4$0$14235$ba620e4c@news.skynet.be> <1182352484.909159.317010@g4g2000hsf.googlegroups.com> <1182355965.993612.150100@z28g2000prd.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 30 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 8ccca12d.news.skynet.be X-Trace: 1182428620 news.skynet.be 13850 194.78.198.49:53305 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:132725 X-Received-Date: Thu, 21 Jun 2007 08:23:45 EDT (newsdbm02.news.prodigy.net) Hi Ankit, Ankit wrote: > Hi Laurent.. > > Thanx a lot for providing the bash script..But i have > worked out of this problem i wasnt able to reply sooner because i was > trying to overcome this problem which made me land up in another..I > arranged for RHEL 4.0 and i installed Webpack 91i on it the compiler > and simulator are working out fine but it is the IMPACT which is > giving me the problem what happens is when i double click on IMPACT > after checking everything and showing it is successfully checked till > "Fit" it just hangs up and during installation the drivers script do > not get installed that is the drivers cable do not get installed > saying "kernel mismatch"..So is there a way out of this i have tried > installing windrvr6.0 but some how it doesnt seem to work out if > somebody could provide a better solution to this it would be really > great... I clearly advice against using the Jungo WinDriver kernel modules. They bypass the kernel security model to expose resources that should be kept inside the kernel. If possible, use an open-source FPGA/CPLD programmer. Best regards, Laurent PinchartArticle: 120965
On Jun 21, 2:27 am, Mark McDougall <m...@vl.com.au> wrote: > Gene S. Berkowitz wrote: > > According to the manufacturer (Century Corp, Japan), it stripes the data > > across the multiple cards to speed up access (you must install cards in > > pairs). > > My statement stands. You can do all that in a single CPLD... It looks to me like the one-per-card chips are probably buffer memories of some sort.Article: 120966
On Jun 21, 3:22 pm, cs_post...@hotmail.com wrote: > On Jun 21, 2:27 am, Mark McDougall <m...@vl.com.au> wrote: > > > Gene S. Berkowitz wrote: > > > According to the manufacturer (Century Corp, Japan), it stripes the data > > > across the multiple cards to speed up access (you must install cards in > > > pairs). > > > My statement stands. You can do all that in a single CPLD... > > It looks to me like the one-per-card chips are probably buffer > memories of some sort. sure, its very simple: [ATA device IP Core] < BUFFER > [SD Host IP Core] + some small management state machine. it really is simple as that, but I would not call it "buffer memory of some sort" AnttiArticle: 120967
On Jun 21, 8:32 am, Antti <Antti.Luk...@googlemail.com> wrote: > > It looks to me like the one-per-card chips are probably buffer > > memories of some sort. > > sure, its very simple: > > [ATA device IP Core] < BUFFER > [SD Host IP Core] > + some small management state machine. You assume that the operation of the buffers is trivial. I suspect it may not be. Even the ATA interface is non-trivial if you want to support the faster transfer modes. There's probably a reason why it's an FPGA and not simply a CPLD. I'm sure someone could make a more cost-optomized design, but at the extremes of that, performance may suffer. Of course we could also be looking at a product where someone plunked down the parts they thought would be required to make a good solution, but shipped it before getting their HDL code beyond minimal low-rate functionality. > it really is simple as that, but I would not call it "buffer memory of > some sort" Oh, and absent information as to what type of "buffer memory" it is, what exactly would you call it?Article: 120968
Antti wrote: > On 19 Jun., 17:00, cs_post...@hotmail.com wrote: > >>On Jun 19, 9:56 am, Antti <Antti.Luk...@googlemail.com> wrote: >> >> >>>>Yes, that's odd, but doesn't bar us from begining a comparison. >> >>>>How fast have you documented the Xilinx cable going? >> >>>yes that ODD >> >>>and yes it does prevent comparison, actually ;) >>>the USB performance can be influenced by many things, >>>it could be that amontec used FS only hub or root port as example, >> >>So how fast have _you_ gotten the xilinx cable to go? >> >>You seem to be having more fun laughing at Larry's calendar challenges >>than actually seeking to compare performance. >> >>The Amontec claimed performance, while yet unverified, doesn't seem >>unreasble to me, so I'm really curious if you have evidence that the >>xilinx cable is working faster than that for you? > > > actually as you have asked the same thing question SO MANY times, here > is the answer > YES, Xilinx Platform cable WORKS FASTER. > > example: 11MBit bitstream, REDUCED TCK Clock to 12MHz, time : 2.547 > seconds > > On the test board the JTAG chain clock isnt optimal so I can not test > at 24MHz TCK, > I assume the speed performance would be noticeable. > > this doesnt mean that Xilinx software and drivers are good, they are > not, many JTAG operations > could be carried out faster then do, but eh, this is the same thing as > with Actel, they changed to > use windriver USB drivers, and as result their programming times > increased 2 times. > > but hardware wise the Xilinx Platform USB cable is defenetly capable > to get much better performance > then any implementation of FT2232 in plastic box (== Amontec jtagkey, > etc..) ever can. FT2232 has > limitation on max JTAG clock of 6MHz. > > Antti > Dear Antti, Sorry for the delay, but last Friday was the big CRASH. We received lightning on Amontec's House... the lightning comes in over LAN ! We lost 5 computers ! Our servers protected by UPS are safe, HOUFFF ! Strange meteo in Switzerland at this moment. ...Article: 120969
On 21 jun, 13:49, Antti <Antti.Luk...@googlemail.com> wrote: > On Jun 21, 1:44 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > eh, if you read my replies, then I did not outrule this to be > implementatble in "3 USD FPGA", > there are not so many FPGA with <= 3 USD price tag. And yes fitting > into to cheapest FPGA > would require near-magical engineering, but could be doable. > > Antti Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode (DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get 16 MB/sec...... not even bad. Optimizing would bring that to (I think I have seen 800kB/s reported in SPI) 64 MB /sec read.... So that would use _very_simple logic, why keep to any spec... your own driver.Article: 120970
On Jun 21, 4:14 pm, pantel...@yahoo.com wrote: > On 21 jun, 13:49, Antti <Antti.Luk...@googlemail.com> wrote: > > > On Jun 21, 1:44 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > > eh, if you read my replies, then I did not outrule this to be > > implementatble in "3 USD FPGA", > > there are not so many FPGA with <= 3 USD price tag. And yes fitting > > into to cheapest FPGA > > would require near-magical engineering, but could be doable. > > > Antti > > Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode > (DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get > 16 MB/sec...... not even bad. > Optimizing would bring that to (I think I have seen 800kB/s reported > in SPI) > 64 MB /sec read.... > So that would use _very_simple logic, why keep to any spec... your own > driver. the OP was talking about device that 1) is FULLY ATA compliant 2) is FULLY SD Card compliant 3) uses 2 SD cards both in 4 bit mode to maximize speed this has nothing todo with "own spec" and SPI mode AnttiArticle: 120971
On a sunny day (Thu, 21 Jun 2007 07:14:03 -0700) it happened panteltje@yahoo.com wrote in <1182435243.752972.271180@w5g2000hsg.googlegroups.com>: >On 21 jun, 13:49, Antti <Antti.Luk...@googlemail.com> wrote: >> On Jun 21, 1:44 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > >> eh, if you read my replies, then I did not outrule this to be >> implementatble in "3 USD FPGA", >> there are not so many FPGA with <= 3 USD price tag. And yes fitting >> into to cheapest FPGA >> would require near-magical engineering, but could be doable. >> >> Antti > >Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode >(DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get >16 MB/sec...... not even bad. >Optimizing would bring that to (I think I have seen 800kB/s reported >in SPI) >64 MB /sec read.... >So that would use _very_simple logic, why keep to any spec... your own >driver. Oops, divide by 10 please ... Still 6.4 MB/sec would be usable...Article: 120972
On a sunny day (Thu, 21 Jun 2007 14:18:31 -0000) it happened Antti <Antti.Lukats@googlemail.com> wrote in <1182435511.771284.181640@g4g2000hsf.googlegroups.com>: >On Jun 21, 4:14 pm, pantel...@yahoo.com wrote: >> On 21 jun, 13:49, Antti <Antti.Luk...@googlemail.com> wrote: >> >> > On Jun 21, 1:44 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: >> > eh, if you read my replies, then I did not outrule this to be >> > implementatble in "3 USD FPGA", >> > there are not so many FPGA with <= 3 USD price tag. And yes fitting >> > into to cheapest FPGA >> > would require near-magical engineering, but could be doable. >> >> > Antti >> >> Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode >> (DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get >> 16 MB/sec...... not even bad. >> Optimizing would bring that to (I think I have seen 800kB/s reported >> in SPI) >> 64 MB /sec read.... >> So that would use _very_simple logic, why keep to any spec... your own >> driver. > >the OP was talking about device that > >1) is FULLY ATA compliant >2) is FULLY SD Card compliant >3) uses 2 SD cards both in 4 bit mode to maximize speed > >this has nothing todo with "own spec" and SPI mode > >Antti I do not care what OP was talking about, I _do_ care how I could do it. SDcard spec is expensive you know? WTF do I need it for if it can be done in an other way. We were looking for _cheap_ solutions right? Else you just buy a flash disk.Article: 120973
Amontec, Larry wrote: > ON NEXT MONDAY : 17-JUNE-2006 > > Amontec will provide the ‘how-to’ program via a XILINX VIRTEX XC4VLX25 > 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! > > On next Monday, your Amontec JTAG key will be close to the speed of a > Xilinx Platform Cable USB for programming any FPGA and CPLD vendors > (Altera Xilinx Lattice Cypress ...) > > Come back next Monday on http://www.amontec.com ! > > Laurent Hi all, You may download the Amontec SVF Player from http://www.amontec.com/jtagkey.shtml Already tested for programming Altera Lattice Xilinx FPGA s CPLD s and FLASH s. It can be use for programming AVR ATMEGA processors too. But you may use it as custom JTAG Boundary Scan. Infini SCAN LENGTH ! Infini number of TAP (number of Targets) integrating Header and Trailer scans. The amtsvfplayer.exe comes with c project source. Also, you may edit the source, customize it and re-compile a new SVF Player for your specific needs. amtsvfplayer.exe -h to get help on usage. You may execute SVF Files or SVF Lines. A SVF Line could be a concatenation of SVF commands. You may adapt JTAG Frequency (FREQUENCY) via -frequencyFactor. In this way you do not need to edit the SVF yourself. When using -frequencyFactor, the RUNTEST x TCK is automaticaly updated ... Linux version ready to be published. HAVE FUN WITH JTAG AND SVF ! ... but you need to have the JTAGkey. Regards, Laurent http://www.amontec.com Ann: via JTAGkey, you have a lot of ARM Debug Solutions too, including OpenOCD JTAG server, Crossworks, Yagarto ... !Article: 120974
On Jun 21, 9:03 am, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > Sorry for the delay, but last Friday was the big CRASH. We received > lightning on Amontec's House... the lightning comes in over LAN ! We > lost 5 computers ! Our servers protected by UPS are safe, HOUFFF ! Sorry to hear that. You do appear to have recently posted some code for an SVF player. Always good to see manufacturer's providing real user flexibility in using their products! Is this code the how-to for the JTAG speed claim? Was the comparison to a Xilinx cable also run in SVF file mode, or did you have impact reading a native xilinx bitstream file?
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