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On Jun 22, 9:19 am, Evan Lavelle <nos...@nospam.com> wrote: > On Fri, 22 Jun 2007 15:22:52 -0000, Amal <akhailt...@gmail.com> wrote: > >Does anyone have a copy of the last release of "Cadence TestBuilder"? > >I would appreciate if you can give me a copy. > > What was the last release? I've got TestBuilder-01_30-s004_tar.gz, if > that's of any use. > > Evan testbuilder.net appears to be dead. Would you mind sending me a copy? Thanks.Article: 121051
Vimal wrote: > As per my understanding V5 GTP support 1.2V CML standard. I > downloaded the V5 IBIS model from Xilinx website but it does not seem > to contain V5 GTP (1.2V cml) model. > > How can I get the 1.2V CLM IBIS model for V5 GTP? You can only get special encrypted SPICE-models for GTPs, no IBIS-models. To simulate those, you normally need a software upgrade, too, i.e. HyperLynx with the GHz option and a SPICE-simulator. I've only done this with the RocketIOs in Virtex2-Pro, but I suppose the same applies for the GTPs. Back then I simulated with this kit: http://www.mentor.com/products/pcb/expedition/design_kits/hl-rocketio_design_kit.cfm HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 121052
> I used the "fork - join" command which should do just what I want. Only in simulation,but not in real hardware > Unfortunately, my Xilinx Spartan-3 does not support this command. No hardware will support the fork - join command, because it is not synthesizable. As bromley suggested, all the lines in a synthesizabele code will run in parallel based on the events. So you need to just separete operations into different always blocks based on some events. Or you can separate that into different modules if you feel so. Eg: if you want type A and type B operation to be performed on the 'data' and get the output1 and output2. create something like this (dont look at the syntax). module typeA (data,control1,output1); module typeA (data,control2,output2); Two operations will proceed in parallel depending on the control1 and control2. any way you first correctly understand the difference between the software and the Hardware very clearly. When writing a synthesizable verilog code always you should have a clear picture of the underlying hardware. regards Sumesh V SArticle: 121053
Antti wrote: > On 21 Jun., 18:41, "Amontec, Larry" <laurent.ga...@ANTI- > SPAMamontec.com> wrote: > >>Antti wrote: >> >>>On 21 Jun., 17:47, cs_post...@hotmail.com wrote: >> >>>>On Jun 21, 9:54 am, Antti <Antti.Luk...@googlemail.com> wrote: >> >>>>>and too bad tha the "source code" published is 100% useless, as all >>>>>the actual JTAG handling is hidden in an DLL and there is no source >>>>>code available for it. >> >>>>Strongly disagree. >> >>>>First you can use it as intended. >> >>>>Then you can use the functions in the provided header file to >>>>accomplish various other jtag tasks. >> >>>>And if you really want to understand it, well, you have a header file >>>>for Larry's DLL, and Larry's DLL calls the FTD2xx.dll. So you make up >>>>a fake version of the later, and see what a given trial call to >>>>Larry's DLL produces in terms of FTD2xx operations... Yeah, reverse >>>>engineering, but simpler than reverse engineering the xilinx stuff, >>>>and people have done that! >> >>>eh there is absolutly no sense to RE Larry DLL's ;) >>>its nothing magical to found there. >> >>>the "functions provided" did look like primitive replacement for >>>something calles >>>"command line parameter passing" - but well I only looked 2 minutes, >>>maybe there >>>is something more to see. But what I did see did look like useless. >>>I would prefer just run from batch file, then using this customization >>>API >> >>>Antti >> >>Electronic is not Magic but Logic. Only Physic is Magic! >>True Random Number Generator is Magic and Physic but use some Electronics! >> >>It is very simple to talk and think about True Random Number but you >>need more than 2 minutes for developing a True Random Number Generator! >> >>Bla - bla ... as your bla - bla Antti. >> >>Antti, you CANNOT take 2 minutes and then resume by a "too bad" and by a >>"100% useless". >> >>Laurent- Zitierten Text ausblenden - >> >>- Zitierten Text anzeigen - > > > bla-bla, BTW how did you test that your DLL can handle "infinite" > length chain? > if I make SVF file that does masked compare and has single chain > length of 33GBit, this would then be executed ok? 33G is defenetly > less than infinite I think? > > and if I look at 2 pages of source code, then 2 minutes can tell a lot > already > > Antti > Our JTAG HAL (Amontec X Hardware Abstraction Layer) was designed for infinite SCANS ! And it is ... We can do a 33 Giga Scan length via our AMTXHAL. Very easy. If you have a REAL application with a 33 Giga bit please call me. And we will try ! Yes two minutes can tell a lot for me two, but this is not enough for publishing your comments as a "too bad" and by a "100% useless". LaurentArticle: 121054
I have built a EDK project to program an opb_pci bridge into a virtex4fx60 FPGA, in this design, a 100MHz clock from a crystal was the input for DCM, and a 2x ouput(200Mhz) was for the IDELAYCTRL primitives. But the opb_bridge didn't work at all. I used a Agilent's oscilloscope to see if the clocks work well or not. The result was that 100Mhz input clock was OK, but the 200Mhz output was a bad one, just like a mass of noise. So can anyone kindly help me find out what is wrong with the DCM=A3=BF Thank all.Article: 121055
Antti wrote: > On 21 Jun., 17:40, "Amontec, Larry" <laurent.ga...@ANTI- > SPAMamontec.com> wrote: > >>Antti wrote: >> >>>On Jun 21, 4:03 pm, "Amontec, Larry" <laurent.ga...@ANTI- >>>SPAMamontec.com> wrote: >> >>>>Antti wrote: >> >>>>>On 19 Jun., 17:00, cs_post...@hotmail.com wrote: >> >>>>>>On Jun 19, 9:56 am, Antti <Antti.Luk...@googlemail.com> wrote: >> >>>>>>>>Yes, that's odd, but doesn't bar us from begining a comparison. >> >>>>>>>>How fast have you documented the Xilinx cable going? >> >>>>>>>yes that ODD >> >>>>>>>and yes it does prevent comparison, actually ;) >>>>>>>the USB performance can be influenced by many things, >>>>>>>it could be that amontec used FS only hub or root port as example, >> >>>>>>So how fast have _you_ gotten the xilinx cable to go? >> >>>>>>You seem to be having more fun laughing at Larry's calendar challenges >>>>>>than actually seeking to compare performance. >> >>>>>>The Amontec claimed performance, while yet unverified, doesn't seem >>>>>>unreasble to me, so I'm really curious if you have evidence that the >>>>>>xilinx cable is working faster than that for you? >> >>>>>actually as you have asked the same thing question SO MANY times, here >>>>>is the answer >>>>>YES, Xilinx Platform cable WORKS FASTER. >> >>>>>example: 11MBit bitstream, REDUCED TCK Clock to 12MHz, time : 2.547 >>>>>seconds >> >>>>>On the test board the JTAG chain clock isnt optimal so I can not test >>>>>at 24MHz TCK, >>>>>I assume the speed performance would be noticeable. >> >>>>>this doesnt mean that Xilinx software and drivers are good, they are >>>>>not, many JTAG operations >>>>>could be carried out faster then do, but eh, this is the same thing as >>>>>with Actel, they changed to >>>>>use windriver USB drivers, and as result their programming times >>>>>increased 2 times. >> >>>>>but hardware wise the Xilinx Platform USB cable is defenetly capable >>>>>to get much better performance >>>>>then any implementation of FT2232 in plastic box (== Amontec jtagkey, >>>>>etc..) ever can. FT2232 has >>>>>limitation on max JTAG clock of 6MHz. >> >>>>>Antti >> >>>>Dear Antti, >> >>>>Sorry for the delay, but last Friday was the big CRASH. We received >>>>lightning on Amontec's House... the lightning comes in over LAN ! We >>>>lost 5 computers ! Our servers protected by UPS are safe, HOUFFF ! >> >>>>Strange meteo in Switzerland at this moment. >> >>>>...- Hide quoted text - >> >>>>- Show quoted text - >> >>>brrr :( too bad the lightning strike, and lost computers. >> >>>and too bad tha the "source code" published is 100% useless, as all >>>the actual JTAG handling is hidden in an DLL and there is no source >>>code available for it. >> >>>Antti >> >>Dear Antti, >> >>Did you try it ? or do you only search open sources ? >>Is a work too bad and 100% useless because it does not provide ALL in >>Open-Source? >>Do you make $$$ multi-donations for an Open-Source project? We have the >>replies. >> >>Amontec team works daily for providing real user flexibility and >>solutions in using Amontec products ... >> > > > really? > > i have a chameleon, this is PURCHASED not your free gift > (that one did burn in), but I can not use chameleon as solutions > provided > by amontec do not not support chameleon when LPT base address is not > default > (like PCI LPT) > > there is solution to reconfigure Amontex chameleon connected to PCI > LPT, > but this solution is PINAPI(tm) based XSVF by Antti Lukats - solutions > from Amontec are not available. > > Antti > Yes, really, as by our JTAG Accelerator on our Chaleeon POD. This helps many companies using our Chameleon POD in production/test stage (5x to 6x faster than the Macraigor Raven ...). But a tool cannot never support all tricky things coming from custom uses and specific applications ... But I am happy to know about your PINAPI, even if this comes a bit late for us, since major part of designers want USB products, the parallel port is coming rare and annoying). This is why, we provides the already popular Amontec USB JTAGkey now. Regards, Laurent htpp://www.amontec.comArticle: 121056
Thanks for providing the link for Virtex2 pro ibis model. I do have HyperLynx GHZ but I do not have the HSPICE software. Also as per my undestanding Xilinx has changed their GTP I/O design for V5. V5 supports 1.2V CML standard, I will check into what Virtex2 pro supported. Thanks. VimalArticle: 121057
Some of my modules implements a register bank controlled by CPU lines. Inside the module I use register banks, like reg [7:0] dac_sel[0:7]; However if I put these multidimensional register in the module port list, both CVER and IVERILOG complain. I can work around by concatenating the register bank into one long vector and write the vector in the module port list. Being able to exporting register bank would be nice. Is this a shortcoming of the simulators or of the Verilog standard or ask I for something impossible? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 121058
What problems are you having? There is bug in the schematic initial display. You need to press 'ZOOM +' or 'ZOOM -' to make the page layout visible to place a component. Make sure to place I/O markers to allow routing to a physical pin. I/O buffers before outputs markers and after inputs markers allow you to select the I/O type other then default. Use the 'Assign package pins' available in process tab to assign the I/O's to specific pins. (XILINX PACE)Article: 121059
On Jun 24, 6:30 am, Perry <lipeng....@gmail.com> wrote: > I have built a EDK project to program an opb_pci bridge into a > virtex4fx60 FPGA, in this design, a 100MHz clock from a crystal was > the input for DCM, and a 2x ouput(200Mhz) was for the IDELAYCTRL > primitives. > > But the opb_bridge didn't work at all. I used a Agilent's oscilloscope > to see if the clocks work well or not. The result was that 100Mhz > input clock was OK, but the 200Mhz output was a bad one, just like a > mass of noise. > > So can anyone kindly help me find out what is wrong with the DCM=A3=BF > Thank all. Howdy Perry, Unfortunately your description doesn't really provide enough info for people need to help you. You said that you looked at some signals with a scope, but you didn't describe what you saw in detail. Solving problems like this is ALL about detail: 1=2E What voltage swing (and offset from ground) did you see? 2=2E Is your .ucf file correct (pin numbers and voltage type set correctly for both input and outputs signals?) 3=2E Exactly how do you have signals connected in the design (posting the HDL for your clock tree is the best way to have that checked) Good luck, MarcArticle: 121060
> I altered the loader script so that only .data, heap and stack were > placed > in > external memory. However I still got the error. Things have moved onto > another board where thankfully there is sufficient block ram. It barfs up because the .data sections of your executable also contain global variables which can be initialised... and since you do not control the SDRAM, you can't initialize them ! In order to pull this off, you'd need an executable loader which would be aware of the .elf format and would load a .elf file (for instance stored in Flash) and build the adequate structures in your SDRAM when loading the executable.Article: 121061
Vimal wrote: > Thanks for providing the link for Virtex2 pro ibis model. > > I do have HyperLynx GHZ but I do not have the HSPICE software. Same problem here. We bought HyperLynx specifically to simulate RocketIOs... when we first tried it out, it turned out you neeed the GHz option in addition to the tool itself, which the distri never told us about. And after we bought that, too, we still needed the SPICE simulator, again, noone told us that was not included > Also > as per my undestanding Xilinx has changed their GTP I/O design for > V5. V5 supports 1.2V CML standard, I will check into what Virtex2 pro > supported. V2P is/was CML 1.5V. You of course need the model for V5, but everything else is the same (i.e. you need HyperLynx with GHz option and SPICE support), as far as I know. cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 121062
Hi guys. First post to this newsgroup, let's pop the champagne ;) I need your advice on selecting a FPGA module for my needs. Anyway. I need to stream data from a PC to a device, and back. Around 60-80 Mbps. I want to use Ethernet, 100 Mbps should do the job. I need a FPGA somewhere too, to format the data, handle the IO, and do some processing/FIR filtering. For now this will have two applications : streaming many channels of high bandwidth audio (24/192), and instrumentation (DSO). More later. I have a working prototype with the Atmark Techno Suzaku FPGA module. It handles the full 100 Mbps bandwidth (barely) but not in full duplex. However I do not want to use this module in the final design : it isn't really suited. After experimenting with the Suzaku which has a MAC chip, and an Atmel NGW100 which has no FPGA but a decent CPU/MAC with smart DMA I have come to the following conclusions : - I'd like to use the OpenCores MAC core to drive a PHY and DMA the data to a fast memory buffer. - The FPGA will then forward the buffered data to the IO channels in due time - I need a CPU, but it will not touch the data, only parse the packet headers (I use UDP which is nice for this application). - CPU will also handle other stuff like LCD and GPIO - Microblaze is OK - No OS will be used So, I'd need a FPGA module with the following : - 100BaseT Ethernet PHY connected to FPGA - FPGA with enough gates to instantiate OpenCores MAC core, Microblaze, some BRAM buffers, some FIR filters, etc. - 1MB fast memory (SDRAM or SRAM) where I can put my buffers and also my executable code. More is also good ! - Should be small, and not radiate EMI like a radio station - Max cost $200, cheaper is better obviously ! - It should work ;) I'd like something like this : http://www.ixxat.de/powerlink_module_en,18116,5873.html But noone sells it apparently and where is the docs ? I dunno. I could also use a module with a hard CPU if there is a fast access (ie. bus) from CPU to FPGA. I know the Xilinx tools, but I am not a Xilinx fanatic... So, what is your advice ? I'd rather buy a module instead of having to build it...Article: 121063
On Sun, 24 Jun 2007 14:17:54 +0000 (UTC), Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >Some of my modules implements a register bank controlled by CPU >lines. Inside the module I use register banks, like > reg [7:0] dac_sel[0:7]; > >However if I put these multidimensional register in the module port list, >both CVER and IVERILOG complain. I can work around by concatenating the >register bank into one long vector and write the vector in the module port >list. Being able to exporting register bank would be nice. > >Is this a shortcoming of the simulators or of the Verilog standard or ask I >for something impossible? I'ts a feature of Verilog-2001: you cannot pass a memory (array of vectors) through a port. As you correctly say, the workaround is to make a suitable larger vector, and then split it into pieces within and outside the module. SystemVerilog fixes this, allowing pretty much any physically realisable data type on a port. Synthesis support is not universal, though :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 121064
Ah, I've looked (quite hard) at your stuff. Shame you don't have a pcie spartan board, but I guess designing/making them isn't cheap. Still, your 'cheap' PCI card is nice! I shall probably be buying one at some point in the future when I have a non-pcie project. Anyway, its the fact that the board is non-RoHS compliant and can't legally be exported thats stopping Digikey/etc from shipping me it. On Jun 23, 11:56 am, John Adair <g...@enterpoint.co.uk> wrote: > If you buy from Digikey they will ship to the UK. Alternatively nuy > from xilinx distributors in the UK - Silica or Nu-Horizons (formerly > DT Electronics). > > We will have a product in this sector and price point but that is a > while off yet. We have lot's of other things to launch before we show > that product. Our currently lowest priced PCI-E Virtex based product > the Broaddown-4 BD4-LX4010 is about GBP=A3 950 + VAT. > > John Adair > Enterpoint Ltd.www.enterpoint.co.uk > > On 23 Jun, 05:40, randomd...@gmail.com wrote: > > > Apologies if this is a bit too off-topic for the list, but I'm > > guessing other Englanders (and other nationalities for that matter) > > have similar issues. > > Anyway, I really want a PCI-E spartan board, and Xilinx's s3pcie board > > is cheap. Unfortunately it isn't RoHS compliant, so I can't get it > > them to ship it to England - are there any reshipping services that'd > > do it? Anything short of me taking a flight to the US to get it would > > be good. > > > Failing that, has anyone heard any plans of an RoHS compliant board > > being made? > > > Alternatively, if there are any other pcie boards in a similar > > pricepoint, that'd be good (though I've scoured the net looking for > > one). > > > Ta..Article: 121065
Uwe Bonnes wrote:
> Some of my modules implements a register bank controlled by CPU
> lines. Inside the module I use register banks, like
> reg [7:0] dac_sel[0:7];
>
> However if I put these multidimensional register in the module port list,
> both CVER and IVERILOG complain. I can work around by concatenating the
> register bank into one long vector and write the vector in the module port
> list. Being able to exporting register bank would be nice.
>
> Is this a shortcoming of the simulators or of the Verilog standard or ask I
> for something impossible?
I can't answer the verilog question, but I can
commiserate about the general problem of where to
put cpu io registers/decoders that cover multiple modules.
If I put them all in one module, register assignments
are simple but wiring and changes are messy.
If I distribute them, duplicate assignments are possible.
For now, I prefer to distribute a logical bus to
all the modules with the following fields.
address, writeData, write_stb, readData, read_stb
I infer registers and decoders in the module
that uses them, and keep track of address
and bit allocations using global constants.
-- Mike Treseler
Article: 121066I'm using Altera's "Cyclone II Starter Kit", and while the board seems to work fine, I can't figure out one of the bundled utility programs. I installed the Cyclone II Starter Kit CD on my Windows/XP machine. I'm able to use Quartus II 7.1 (web) to compile and then download projects to the board -- That works fine. However, I cannot get the "Control Panel - Starter II Kit" application to work. I launch it, and the application window comes up. It appears to work fine -- I can 'open USB' connection to my board, then click on the various tabs (sram, sdram, led, etc.) and toggle the controls. However, when I click 'set' on anything, nothing happens. I see the blue-light on my Kit board flicker momentarily, so it's getting some kind of traffic from the PC. But otherwise, nothing happens. For example, I tried the 'SRAM' tab, and wrote several unique values (0x0123, 0x4567) to the SRAM at address 0x00 and 0x01. But, when I read them back, they always come back 0x0000. The Control Panel's built-in self-test also fails on the sdram, sram, and flash. What am I doing wrong? I tried toggling the RUN/PROG switch (SW12) back and forth, then cycling power to the board. With either position, Control Panel applet still doesn't work.Article: 121067
I tried using the Virtex2 pro Rocketio toolkit using HyperLynx version 7.7. I am having some problem simulating it. The software is not able to locate the WDB server. I do not know what it means. It gives following error: Error running ADMS: No WDB server present. I will have to check with our Mentor contact and resolve this. Please let me know if you have any suggestions. My initial reaction to this is that it is a bit more involved then what I expected. I was hoping that I will have the ibis model that I can associate with a differential driver and receiver. Thanks. VimalArticle: 121068
Antti wrote: > there are 4 times IDE-SD ASIC's, from company called c-guys > 1 per SD card. those chips include FULL IDE2SD interface, > each of them has local onchip buffers for 2 sector > FPGA does some management only, to combine the 4 IDE into one, > the SD IP core is not inside the FPGA at all.. Not a very smart design then... -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 121069
On Jun 22, 4:14 pm, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > Innews:1182481520.530724.54480@i38g2000prf.googlegroups.com > timestamped Thu, 21 Jun 2007 20:05:20 -0700, "h...@hit.edu.cn" > <h...@hit.edu.cn> posted: > "On 6 22 , 5 58 , "Marc Battyani" <Marc.Batty...@fractalconcept.com> > wrote: > > <h...@hit.edu.cn> wrote > [..] > > > > > The estimated memory usage is 2GB or so, while the calculations > > > required is listed below: > > > > > integer addition 2442 Giga operations per second > [ ^^^^^^^^^^ > N.B. "per second".] > > > float add 814 Giga operations per second > > > float substrac 2424 Giga operations per second > > > float muliply 1610 Giga operations per second > > > float divide 809 Giga operations per second > > > > > I want these calculations done in one minite, so we can divide the > > > operations by 60. > [ ^^^^^^^^^^ > N.B. one minute.] > [ ^^^^^ ^^^^^^ > N.B. the person of Harbin Institute of Technology of China typed > "divide" but clearly conveyed and understood the concept of needing to > multiply in order to speed up an implementation to perform five > minutes' worth of calculations of the original implementation's in one > second and simply mixed up the English word "divide" with > "multiply". I am reminded of a language lesson in which I mixed up a > word for "close" with a word for "open" (or maybe it was the other way > round) so the teacher mocked me by trying to indicate that such > miscommunication could result in disaster if I was giving an order to > control a dam instead of a door or window.] > > > As a matter of fact, if the calculations could be done in 5 minites, > > > it is OK for me. So for minimum requirment, divide the above numbers > > > by 300(=60*5). > > > > Is it single or double precision floats? > > > > Divided by 300 the numbers are not very high: > > 10.7G fadd/fsub > > 5.3G fmul > > 2.7G fdiv" > > Hello, > > In case you missed them, please see my notes above in square brackets > (and to see what the ^ characters are being used to point at, view in > a monospace font such as Courier). > > The numbers should be divided by the reciprocal of 300 (or, for > efficient calculations, multiplied by 300) so instead of 10.7Gflops; > 5.3Gflops; and 2.7Gflops the results should be approximately... > 244200 Gigafloating point operations per second for additions; > 727200 Gigafloating point operations per second for subtractions; > 483000 Gigafloating point operations per second for multiplications; > and > 242700 Gigafloating point operations per second for divisions. > > "[..] > > It is double precision. And can you please explain it for me why it > matters?" > > Slower and more memory (but less inaccurate). > > "The another question is that as you mentioned memory bandwidth could > be an issue, can you evaluate the approximately required memory > bandwidth?" > > The more bigger values which will be flowing through your gates, the > more bits per second you will want to be able to handle. I am > surprised that you did not notice the inappropriate calculation of > 1610 Gflops / 300 = 5.3Gflops so if you plan on spending a lot of > money on your new implementation, please for your own sake, > double-check everything. > > Regards, > Colin Paul Gloster I got what you mean, but the fact is what I wrote may make you confused. The total computation is described below: integer add 2442 Giga operations per second float add 814 Giga operations per second float substrac 2424 Giga operations per second float muliply 1610 Giga operations per second float divide 809 Giga operations per second If I need to get the operations done in one second, I need to finish these number of calculations. While if I need to get the operations done in one minute, I need to finish ( these number of calculations / 60 ) So it is to divide the time needed, not to multiply.Article: 121070
I have post an topic serveral days ago, and there is the link. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/ee8cd744f6c3c10b?tvc=2# The total computation is described below: integer add 2442 Giga operations float add 814 Giga operations float substract 2424 Giga operations float muliply 1610 Giga operations float divide 809 Giga operations And I need these operations done in 1 ~ 3 minutes, so what kind of FPGA is needed? And should I use multiple FPGAs to finish the computation? What if I need the work done in 10 minutes? I prefer Xilinx FPGA. And if possible, lower speed grade device is better, at least for budget reason.Article: 121071
hitsx@hit.edu.cn wrote: > I prefer Xilinx FPGA. And if possible, lower speed grade device is > better, at least for > budget reason. T think this will be very expensive with FPGAs. Maybe this is a better solution: http://www.reghardware.co.uk/2007/06/21/nvidia_launches_tesla/ I've read an article about it in a magazin and they claim to be by a factor of 25 faster than a usual desktop, if the algorithm is highly parallelizable. Use multiple cards and you can reach every speed you want, if it is parallelizable. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 121072
I'm currently working on a design where there isn't an available GC pin to bring a clock in (bad design, not mine). It's an 80MHz single- ended clock, but the design requires an 80MHz and 120MHz clock, so I need a DCM. This design has been proven working on another platform that allows me to bring the clock into a GC pin. When I try the design on the platform that does not allow the GC pin, I go through an IBUF to a DCM and then to BUFG's. There are intermittent failures seen when testing this design. After reading through the latest V4 user guide, it seems that going from an IBUF to a DCM is perfectly valid, but the DCM will be unable to successfully deskew the output clocks wrt the input. This design has an internal loopback mode in which case the skew on these clocks should not matter because they are no longer being used to clock in/out IOB data. Even in this mode, intermittent failures are seen, which leads me to believe it's not a skew issue, but rather just an intermittently dirty clock. I tried going into a CC pin to a BUFIO, then BUFR, then into the DCM, but the design failed to route so I don't think BUFR's are able to drive DCM input clocks. The clock is forwarded over from another FPGA, and I've already tried different drive strength and slew rate combinations on the driving device just because I'm running out of ideas. Nothing seemed to make any differences. Please let me know If anyone has any suggestions.Article: 121073
Vimal wrote: > It gives following error: > > Error running ADMS: No WDB server present. > > I will have to check with our Mentor contact and resolve this. Please > let me know if you have any suggestions. Sorry, can't help, never seen this... cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 121074
On Jun 24, 1:31 pm, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > Antti wrote: > > On 21 Jun., 17:40, "Amontec, Larry" <laurent.ga...@ANTI- > > SPAMamontec.com> wrote: > > >>Antti wrote: > > >>>On Jun 21, 4:03 pm, "Amontec, Larry" <laurent.ga...@ANTI- > >>>SPAMamontec.com> wrote: > > >>>>Antti wrote: > > >>>>>On 19 Jun., 17:00, cs_post...@hotmail.com wrote: > > >>>>>>On Jun 19, 9:56 am, Antti <Antti.Luk...@googlemail.com> wrote: > > >>>>>>>>Yes, that's odd, but doesn't bar us from begining a comparison. > > >>>>>>>>How fast have you documented the Xilinx cable going? > > >>>>>>>yes that ODD > > >>>>>>>and yes it does prevent comparison, actually ;) > >>>>>>>the USB performance can be influenced by many things, > >>>>>>>it could be that amontec used FS only hub or root port as example, > > >>>>>>So how fast have _you_ gotten the xilinx cable to go? > > >>>>>>You seem to be having more fun laughing at Larry's calendar challenges > >>>>>>than actually seeking to compare performance. > > >>>>>>The Amontec claimed performance, while yet unverified, doesn't seem > >>>>>>unreasble to me, so I'm really curious if you have evidence that the > >>>>>>xilinx cable is working faster than that for you? > > >>>>>actually as you have asked the same thing question SO MANY times, here > >>>>>is the answer > >>>>>YES, Xilinx Platform cable WORKS FASTER. > > >>>>>example: 11MBit bitstream, REDUCED TCK Clock to 12MHz, time : 2.547 > >>>>>seconds > > >>>>>On the test board the JTAG chain clock isnt optimal so I can not test > >>>>>at 24MHz TCK, > >>>>>I assume the speed performance would be noticeable. > > >>>>>this doesnt mean that Xilinx software and drivers are good, they are > >>>>>not, many JTAG operations > >>>>>could be carried out faster then do, but eh, this is the same thing as > >>>>>with Actel, they changed to > >>>>>use windriver USB drivers, and as result their programming times > >>>>>increased 2 times. > > >>>>>but hardware wise the Xilinx Platform USB cable is defenetly capable > >>>>>to get much better performance > >>>>>then any implementation of FT2232 in plastic box (== Amontec jtagkey, > >>>>>etc..) ever can. FT2232 has > >>>>>limitation on max JTAG clock of 6MHz. > > >>>>>Antti > > >>>>Dear Antti, > > >>>>Sorry for the delay, but last Friday was the big CRASH. We received > >>>>lightning on Amontec's House... the lightning comes in over LAN ! We > >>>>lost 5 computers ! Our servers protected by UPS are safe, HOUFFF ! > > >>>>Strange meteo in Switzerland at this moment. > > >>>>...- Hide quoted text - > > >>>>- Show quoted text - > > >>>brrr :( too bad the lightning strike, and lost computers. > > >>>and too bad tha the "source code" published is 100% useless, as all > >>>the actual JTAG handling is hidden in an DLL and there is no source > >>>code available for it. > > >>>Antti > > >>Dear Antti, > > >>Did you try it ? or do you only search open sources ? > >>Is a work too bad and 100% useless because it does not provide ALL in > >>Open-Source? > >>Do you make $$$ multi-donations for an Open-Source project? We have the > >>replies. > > >>Amontec team works daily for providing real user flexibility and > >>solutions in using Amontec products ... > > > really? > > > i have a chameleon, this is PURCHASED not your free gift > > (that one did burn in), but I can not use chameleon as solutions > > provided > > by amontec do not not support chameleon when LPT base address is not > > default > > (like PCI LPT) > > > there is solution to reconfigure Amontex chameleon connected to PCI > > LPT, > > but this solution is PINAPI(tm) based XSVF by Antti Lukats - solutions > > from Amontec are not available. > > > Antti > > Yes, really, as by our JTAG Accelerator on our Chaleeon POD. This helps > many companies using our Chameleon POD in production/test stage (5x to > 6x faster than the Macraigor Raven ...). > But a tool cannot never support all tricky things coming from custom > uses and specific applications ... > But I am happy to know about your PINAPI, even if this comes a bit late > for us, since major part of designers want USB products, the parallel > port is coming rare and annoying). > This is why, we provides the already popular Amontec USB JTAGkey now. > > Regards, > Laurent > htpp://www.amontec.com- Hide quoted text - > > - Show quoted text - PINAPI (Pin API) was developed by me VERY long time, initially to provide hardware abstraction layer for PIC and AVR and EEPROM Programming software. The first was developed for MS DOS, and used TSR type of drivers. It was very succesful in that terms that PINAPI enabled programming software did support many hardware I had never seen or validated for the use. In several cases working better than hardware vendors own software. It was later used on WIn 3.1, and is used mostly internally now on modern windows. Unfortunatly the PINAPI was not fully "upgraded" to use Windows added functionality, eg all PINAPI DLLs for windows still are based on very close spec to the initial spec. However even so there is succesful use it, one example that you can examine is Xilinx SystemACE player, you can playback Xilinx ACE onto any PINAPI driver as if the ACE would be executed by the Xilinx SystemACE CF. http://code.google.com/p/fpga-tools/downloads/list here you can get the source code of the application. Full source of the PINAPI drivers and all components, are not currently public, but on my list to make public. another use is Spartan3E NOR flash programmer for Xilinx sample, also uses PINAPI drivers, next one "SPI direct" programmer, that will flash SPI flash in similar fashion as Altera "jtag indirect" but it is cross FPGA vendor neutral. Antti
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