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If the setup time on the FF is not met, then it could possibly enter the metastable state. If it does, it will recover rather quickly...I can't remember the exact figure...but you can't be certain of any output. It could go either way. Even if it doesn't go metastable, once you break the setup time, you cannot know for certain what the output will be. Therefore, you would never be able to 100% trust your bus analyzer. I am basing this on how I understand you post. You mention in the second one that you are using a 'local oversampling clock'. Is this just some integer multiple of the bus speed? If it is, then you can try to figure out a way to do data recovery on the oversampled data. Then you can shove data into the CPLD asynchronously, oversample it X times, recover the data, push it into the local clock domain, and analyze it.Article: 121026
cxu_dl@yahoo.com wrote:
> Just want to add that I have a local oversampling clock, and the bus
> could switch at anytime, say 0.1ns before the clock edge. and the cpld
> requires setup time of 1.8ns.
>
Setup violations are unavoidable in synchronizers.
I would use two flop synchronizers in a separate
entity/module and just assume that it works.
The alternative is to use false path constraints for STA.
Make sure the fast clock period is less
than the input pulse widths, and use the
slow clock only as in input.
-- Mike Treseler
Article: 121027The problem with violating set-up time is not the ambiguity of the output. If the input switches withing that window, then a 0 as an answer is every bit as good as a 1. Who cares? The real problem is the increased output delay,if the input changes during that sub-femtosecond critial part of the set-up time window. Then the output may fall back at an undefined time after its last clock. But modern flip-flops are very fast. A metastable delay of more than 3 ns is extremely rare. The Xilinx app note is XAPP094 (I think) You can also google: Metastability, Xilinx, Alfke... Peter Alfke On Jun 22, 8:57 am, Iwo Mergler <Iwo.Merg...@soton.sc.philips.com> wrote: > cxu...@yahoo.com wrote: > > On 6 22 , 10 28 , cxu...@yahoo.com wrote: > >> Hi, > >> I apologize if this question is too stupid... basically I want to > >> build a protocol analyzer with a CoolRunner II cpld. the CPLD will > >> watch the bus line and extract data. I have passed behaviorial > >> simulation and fitted the device. but post-fit timing simulation gives > >> me some setup time violations and the output goes to X afterwards. I > >> read document that says ASYNC_REG can be used but it is not available > >> on coolrunner cpld. Then I'm very concerned about what happens in the > >> real circuit. The bus line will not switch in sync with the sampling > >> clock, due to different clock domains, jitters etc. what happens in > >> the real circuit when the setup time is violated? will the cpld go > >> into metastable state for ever? This must be an old problem that has > >> been long solved, but how? can anyone help? thanks a lot.... > > >> Hsu > > > Just want to add that I have a local oversampling clock, and the bus > > could switch at anytime, say 0.1ns before the clock edge. and the cpld > > requires setup time of 1.8ns. > > You can't get rid of metastability, but you can reduce it to > spectacularly low likelihoods. > > The classic way of doing this is to route the signals through > extra flip-flops. 1-2 are usually enough for most applications. > > Violating the setup time on the first FF gives you a certain > chance of it entering a metastable state. It won't stay in it > forever - it just takes longer to switch. The metastable state > must last longer than the clock period to affect the second FF, > which is very unlikely. > > The critical setup time windows which could cause a problem are in > the sub-femtosecond range - somewhere within your setup time window. > I think Xilinx have a appnote somewhere about the details. > > Kind regards, > > IwoArticle: 121028
Any information on the subject will be highly appreciated. Thanks, /MikhailArticle: 121029
On Jun 21, 2:54 am, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote:
I tried to email offline to discuss some of these issues more, but
your email bounces :(
John
This is an automatically generated Delivery Status Notification.
Delivery to the following recipients failed.
hitsx@hit.edu.cn
Article: 121030
Hello,
I have a oscillator with 16 MHz connected to a gclk pin of a Spartan
3E. Inside the FPGA , I use the 16 MHz clock and a clock generated by
multiplying the 16 MHz with 8 with a DFS.
The code is someting like
module bla (..., input clk, ...);
wire clk8;
clkmult clk_m8
(
.CLKIN_IN(clk),
.CLKFX_OUT(clk8)
);
always @ (posedge clk)
begin
(do a lot)
end
always @ (posedge clk8)
begin
(do a lot with a lot of registers)
end
endmodule
clkmult is a generated by the clock wizard for external input, no reset and
no feedback.
I banged my head against the code, but always PAR tells:
WARNING:Route:455 - CLK Net:ale_IBUFG may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
Any hints on what I do wrong?
Thanks
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 121031On Jun 23, 7:04 am, Totally_Lost <air_b...@yahoo.com> wrote: > On Jun 21, 2:54 am, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote: > I tried to email offline to discuss some of these issues more, but > your email bounces :( > > John > > This is an automatically generated Delivery Status Notification. > > Delivery to the following recipients failed. > > h...@hit.edu.cn I am sorry to hear that. I think perhaps my school mail system is under maintenance. Could you please send the mail to hitsx@163.com This is my private mailbox. Thanks a lot.Article: 121032
Apologies if this is a bit too off-topic for the list, but I'm guessing other Englanders (and other nationalities for that matter) have similar issues. Anyway, I really want a PCI-E spartan board, and Xilinx's s3pcie board is cheap. Unfortunately it isn't RoHS compliant, so I can't get it them to ship it to England - are there any reshipping services that'd do it? Anything short of me taking a flight to the US to get it would be good. Failing that, has anyone heard any plans of an RoHS compliant board being made? Alternatively, if there are any other pcie boards in a similar pricepoint, that'd be good (though I've scoured the net looking for one). Ta..Article: 121033
On 6 23 , 12 33 , motty <mottobla...@yahoo.com> wrote: > If the setup time on the FF is not met, then it could possibly enter > the metastable state. If it does, it will recover rather quickly...I > can't remember the exact figure...but you can't be certain of any > output. It could go either way. Even if it doesn't go metastable, > once you break the setup time, you cannot know for certain what the > output will be. Therefore, you would never be able to 100% trust your > bus analyzer. I am basing this on how I understand you post. > > You mention in the second one that you are using a 'local oversampling > clock'. Is this just some integer multiple of the bus speed? If it > is, then you can try to figure out a way to do data recovery on the > oversampled data. Then you can shove data into the CPLD > asynchronously, oversample it X times, recover the data, push it into > the local clock domain, and analyze it. Thank you for the suggestion. yes the local clock is a integer multiple of the norminal bus speed. If the consequence of the timing violation is a misinterpretation of 0 or 1 then it's not a problem , since it will be treated as bit width variation. My original concern was that the output going into metable state and oscillate for prolonged time. Now I read Peter's XAPP094 I no longer worry about this, since my clock period is 20ns, way longer than the already unlikely 3ns...Article: 121034
On 6 23 , 1 02 , Peter Alfke <p...@xilinx.com> wrote: > The problem with violating set-up time is not the ambiguity of the > output. If the input switches withing that window, then a 0 as an > answer is every bit as good as a 1. Who cares? > The real problem is the increased output delay,if the input changes > during that sub-femtosecond critial part of the set-up time window. > Then the output may fall back at an undefined time after its last > clock. > But modern flip-flops are very fast. A metastable delay of more than 3 > ns is extremely rare. > The Xilinx app note is XAPP094 (I think) > You can also google: Metastability, Xilinx, Alfke... > Peter Alfke > > On Jun 22, 8:57 am, Iwo Mergler <Iwo.Merg...@soton.sc.philips.com> > wrote: > > > cxu...@yahoo.com wrote: > > > On 6 22 , 10 28 , cxu...@yahoo.com wrote: > > >> Hi, > > >> I apologize if this question is too stupid... basically I want to > > >> build a protocol analyzer with a CoolRunner II cpld. the CPLD will > > >> watch the bus line and extract data. I have passed behaviorial > > >> simulation and fitted the device. but post-fit timing simulation gives > > >> me some setup time violations and the output goes to X afterwards. I > > >> read document that says ASYNC_REG can be used but it is not available > > >> on coolrunner cpld. Then I'm very concerned about what happens in the > > >> real circuit. The bus line will not switch in sync with the sampling > > >> clock, due to different clock domains, jitters etc. what happens in > > >> the real circuit when the setup time is violated? will the cpld go > > >> into metastable state for ever? This must be an old problem that has > > >> been long solved, but how? can anyone help? thanks a lot.... > > > >> Hsu > > > > Just want to add that I have a local oversampling clock, and the bus > > > could switch at anytime, say 0.1ns before the clock edge. and the cpld > > > requires setup time of 1.8ns. > > > You can't get rid of metastability, but you can reduce it to > > spectacularly low likelihoods. > > > The classic way of doing this is to route the signals through > > extra flip-flops. 1-2 are usually enough for most applications. > > > Violating the setup time on the first FF gives you a certain > > chance of it entering a metastable state. It won't stay in it > > forever - it just takes longer to switch. The metastable state > > must last longer than the clock period to affect the second FF, > > which is very unlikely. > > > The critical setup time windows which could cause a problem are in > > the sub-femtosecond range - somewhere within your setup time window. > > I think Xilinx have a appnote somewhere about the details. > > > Kind regards, > > > Iwo Thank you all for the kind suggestions and help, I added two flip- flops synchronizers in front of my other logic to make it more solid... That APP NOTE was about Virtex II FPGA, I suppose flip-flops in CoolRunner are the same, or even better than that, right?Article: 121035
Hi Programmers this is my first time to join the Forum I'm a senior student in the University of Jordan of Computer Engineering Department My question is that we know that the EDK tool is like a small controller that is programed into the FPGA & tha it is a ready to use package, now is there such a package that can act as a USB2.0 controller that i can use on my the Spartan 3E kit. even though there is a USB port on the kit but apparently it is only for programming purposes please if any one can help me because i need this information for my graduation project. THNx for your time to read thisArticle: 121036
If you buy from Digikey they will ship to the UK. Alternatively nuy from xilinx distributors in the UK - Silica or Nu-Horizons (formerly DT Electronics). We will have a product in this sector and price point but that is a while off yet. We have lot's of other things to launch before we show that product. Our currently lowest priced PCI-E Virtex based product the Broaddown-4 BD4-LX4010 is about GBP=A3 950 + VAT. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 23 Jun, 05:40, randomd...@gmail.com wrote: > Apologies if this is a bit too off-topic for the list, but I'm > guessing other Englanders (and other nationalities for that matter) > have similar issues. > Anyway, I really want a PCI-E spartan board, and Xilinx's s3pcie board > is cheap. Unfortunately it isn't RoHS compliant, so I can't get it > them to ship it to England - are there any reshipping services that'd > do it? Anything short of me taking a flight to the US to get it would > be good. > > Failing that, has anyone heard any plans of an RoHS compliant board > being made? > > Alternatively, if there are any other pcie boards in a similar > pricepoint, that'd be good (though I've scoured the net looking for > one). > > Ta..Article: 121037
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:f5hkq1$df3$1@lnx107.hrz.tu-darmstadt.de... > > I banged my head against the code, but always PAR tells: > WARNING:Route:455 - CLK Net:ale_IBUFG may have excessive skew because > 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template. > > > Any hints on what I do wrong? > > Thanks > Hi Uwe, Did you connect the clock to an IOB? If you connect it to things that aren't dedicated clk pins you'll see warnings like that. You can use the FPGA editor tool to see where the clock net connects. HTH, Syms.Article: 121038
log -r /* is the command but if the simulation runs for a long time, you probably need a big enough disk quota. On Jun 21, 4:08 pm, fastgreen2...@yahoo.com wrote: > Sorry for this newbie-like question, but I can't remember how I did it > before for the life of me. > > Normally I pre-select certain signals before I run the sim, and look > at those in waves. The problem is, if you want to look at signals > that weren't pre-selected, you have to select them and re-run the sim, > which is time-consuming. > > I know there is a way so that you can have all signals (or all > submodule signals) simulated and stored in a database so you can drag > necessary signals into the waves as needed. This is without having > all signals show up in the waves. > > I thought this was a Modelsim command. Or, is it a language specific > command in the design/tb? Help? > > Thanks,Article: 121039
Symon <symon_brewer@hotmail.com> wrote: > "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message > news:f5hkq1$df3$1@lnx107.hrz.tu-darmstadt.de... > > > > I banged my head against the code, but always PAR tells: > > WARNING:Route:455 - CLK Net:ale_IBUFG may have excessive skew because > > 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template. > > > > > > Any hints on what I do wrong? > > > > Thanks > > > Hi Uwe, > Did you connect the clock to an IOB? If you connect it to > things that aren't > dedicated clk pins you'll see warnings like that. You can use the FPGA > editor tool to see where the clock net connects. > HTH, Syms. clk connects to Pin 82 (IO_L11P_2/D2/GCLK2) on a XC3S500E-208. Config mode is Serial Master, so the dual mode function D2 should not be used. As shown, I normally don't instantiate Clock Buffer, but while fiddling around I also tried that with no avail. For a test I connected the DFS input to some other (non-clock) FPGA input, and clk was routed with a global net. I use webpack 9.1 on suse 10.2. I already tried to run fpga_editor, as your answer in another thread found with Google groups suggests. Starting fpga_editor however makes the disk spin and the CPU work for a while, a window flash up and disappear immediate. I tried also the DISPLAY =:0 trick, but to no avail. Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 121040
On Jun 23, 5:21 am, "Mohammad Abbas" <mohammad_...@hotmail.com> wrote: > even though there is a USB port on the kit but apparently it is only for programming purposes please if any one can help me because i need this information for my graduation project. THNx for your time to read this I believe the USB chip on that board is connected to the JTAG only. There is a way to add your own registers to the JTAG function of the spartan, which would give you a limited to way to get data into and out of the board. You could try to modify the board adding some addition wires from the USB chip to the FPGA for user data. You could buy a Nexys board from Digilent (same company which makes most of the xilinx boards) which has USB for programming and for data, though getting the data working may be challenging. They also sell the USB chip as a stand alone accessory. You could buy a USB to serial converter and implement a serial port in the FPGA. You could use some other interfaceArticle: 121041
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:f5j5vq$pv$1@lnx107.hrz.tu-darmstadt.de... > > clk connects to Pin 82 (IO_L11P_2/D2/GCLK2) on a XC3S500E-208. > Config mode is Serial Master, so the dual mode function D2 should not be > used. > As shown, I normally don't instantiate Clock Buffer, but while fiddling > around I also tried that with no avail. > Hi Uwe, So the clk comes out of the FPGA on Pin 82, right? If that's the case, you should probably use the IOB's DDR registers to get the clock out. If you wire the data input of the rising edge DDR FF to '1' and the input to the falling edge FF to '0', then connect the clock to the clk input of both, the clock will appear on the output and your clock net will only connect to clk pins. HTH, Syms.Article: 121042
I have installed the xilinx ise 8.2i. I want to make a simple design for test. I created a schematic project and added "and2" . I want to compile this project and program it to cpld, so one pin will be input 1, another will be input2, and another will be output. Then I can connect output to a led to see if the and truth table is correct with my inputs. Can someone advise me what I should do (all I have is an empty schematic and the aforementioned gate) (I have cpld and access to all pins via soldering iron, cpld will be connected to 5V battery, or 5V from a usb line) It's all basic (or should be) Thanks in advanceArticle: 121043
Symon <symon_brewer@hotmail.com> wrote: > "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message > news:f5j5vq$pv$1@lnx107.hrz.tu-darmstadt.de... > > > > clk connects to Pin 82 (IO_L11P_2/D2/GCLK2) on a XC3S500E-208. > > Config mode is Serial Master, so the dual mode function D2 should not be > > used. > > As shown, I normally don't instantiate Clock Buffer, but while fiddling > > around I also tried that with no avail. > > > Hi Uwe, > So the clk comes out of the FPGA on Pin 82, right? If that's the case, you > should probably use the IOB's DDR registers to get the clock out. If you > wire the data input of the rising edge DDR FF to '1' and the input to the > falling edge FF to '0', then connect the clock to the clk input of both, > the clock will appear on the output and your clock net will only connect > to clk pins. clk is a input. An oscillator is connected on pin 82. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 121044
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message
news:f5jfqc$4uu$1@lnx107.hrz.tu-darmstadt.de...
>
> clk is a input. An oscillator is connected on pin 82.
>
Hi Uwe,
OK, in that case my advice is useless!
So, does your cct look like?
IOB ---> clk ----> bufg -|--> DCM ---> bufg ----> clk8
|
|--> FFs, etc.
Cheers, Syms.
Article: 121045I'm working with the xilinx corgen cic v3.0. I'm finding that to get a decent rejection in the images (60 dB) I need about 4 stages. My input is only 10 bit and I still end up with a 66 bit output, 50 of which are thrown away. As a result my design won't fit in my device. Seems horribly inefficient to me, so I have some questions: 1. My coregen says it doesn't support V4 for the cic so I've been compiling for V2. Seems like the DSP48 with the large accumulator is ideal for CICs? 2. Looks like the exponential bit growith is from the number of stages. Since noone uses more than 16 bits at the output why can't the output of the first integrator be trimmed back to 16 bit before feeding the next and so on? 3. If the cic is just a box car filter wouldn't it be easier to implement as a single subtractor/accumulator whose inputs are the current sample and the sample delayed by R? At least for reasonable R (< 8192) seems like it should fit in block ram okay. Thanks for any help, ClarkArticle: 121046
Symon <symon_brewer@hotmail.com> wrote: > "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message > news:f5jfqc$4uu$1@lnx107.hrz.tu-darmstadt.de... > > > > clk is a input. An oscillator is connected on pin 82. > > > Hi Uwe, > OK, in that case my advice is useless! > So, does your cct look like? > IOB ---> clk ----> bufg -|--> DCM ---> bufg ----> clk8 > | > |--> FFs, etc. As my code example showed, I like to write code without instantiating manufacturer specific code. So I let it to ISE to invoke the BUFGs. Obviously it doesn the right thing when no DCM is connected to the GCLK input pin, and it does the right thing for the output of the DCM. However with the DCM, I need to explicitly instantiate the BUFG between the GCLK input and the DCM to use the output of the BUFG to drive the clock nets. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 121047
Hi guys: I'm writing a program in Verilog where I need for several blocks of code to execute concurrently (parallel blocks). I used the "fork - join" command which should do just what I want. Unfortunately, my Xilinx Spartan-3 does not support this command. Is there another way to get parallel blocks in Verilog? Thanks for any replies. DonArticle: 121048
On Sat, 23 Jun 2007 13:25:21 -0700, eromlignod <eromlignod@aol.com> wrote: >Is there another way to get parallel blocks in Verilog? Each "always" block executes in parallel with every other "always" block. That's how you model concurrency in hardware - each "always" block typically represents an independent piece of hardware, busily and continually doing its own thing. fork...join is occasionally handy for modelling certain kinds of concurrent activity in simulation, but is never synthesisable. What are you trying to do? It sounds suspiciously as though you are trying to map a software view of the world on to hardware, without having a clear picture of the underlying hardware architecture that you want to implement. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 121049
As per my understanding V5 GTP support 1.2V CML standard. I downloaded the V5 IBIS model from Xilinx website but it does not seem to contain V5 GTP (1.2V cml) model. How can I get the 1.2V CLM IBIS model for V5 GTP? Thanks Vimal
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