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emu writes: > is there any open source DDR SDRAM controller IP available (VHDL) for > the DDR SDRAM on this kit ? Try Xilinx app note XAPP454, or maybe XAPP253, XAPP702 or XAPP851.Article: 120651
Mavrick <> wrote: > > In my application, I need to interface the FPGA LVDS > output to CML that is normally powered at 3.3V. > <snip> > the desired common mode voltage range is vcc-100mv to > vcc-300mv where vcc = 3.3V. > If you want to do LVDS -> CML, I'd look at the translators from TI/OnSemi/Micrel for that function; I think you can find some with < 100 ps part-part skew. (SN65CML100,SY58603U) BrianArticle: 120652
My apologies to those who'd consider this spam, but my house in Milpitas, CA was burglarized and among the less mainstream objects stolen were a Tektronix THS730 oscilloscope and a Digilent Spartan 3E-1600 Development Board. If anyone comes across a suspect sale of this board for sale, please let me know. Thanks, TommyArticle: 120653
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:1181699439.988788.212790@n15g2000prd.googlegroups.com... > My apologies to those who'd consider this spam, but my house in > Milpitas, CA was burglarized and among the less mainstream objects > stolen were a Tektronix THS730 oscilloscope and a Digilent Spartan > 3E-1600 Development Board. > > If anyone comes across a suspect sale of this board for sale, please > let me know. > > Thanks, > Tommy > Wow. High tech burglars in Milpitas. Maybe it's time to move to Sunnyvale. Sorry to hear about your loss. BobArticle: 120654
Thanks very much. :-)Article: 120655
Hi, Could someone explain me briefly which is the basic difference between static configuration and dynamic reconfiguration in Virtex5 ? Assuming I have to deal with the biggest Virtex5 device (XC5VLX330T) and my option will be a static configuration, which solution will be the fastest ? Which is the best avilable hardware reference design for the Virtex5 series? I mean one from which you may learn about configuration, DDR2 interfacing, RocketIO, power supply tricks (after you've read datasheets and application notes). thank you, VasileArticle: 120656
On Jun 13, 9:01 am, vasile <picli...@gmail.com> wrote: > Hi, > > Could someone explain me briefly which is the basic difference between > static configuration and dynamic reconfiguration in Virtex5 ? In my opinion, Static reconfiguration erases the configuration SRAM and reprograms, hence the device actually (restart) after configuration. While in case of dynamic reconfiguration configuration memory is not erased. Dynamic reconfiguration is mainly Partial and part of device is reconfigured and rest of the device works as it was doing before configuration. This requires insertion of bus macros and proper floor planning. > > Assuming I have to deal with the biggest Virtex5 device (XC5VLX330T) > and my option will be a static configuration, which solution will be > the fastest ? "Solution ?", Perhaps you are talking about mode of configuration. In my opinion, (which may be wrong), out of JTAG, Master/slave serial, and selectMap; Select Map is the fastest mode of configuration. Partial reconfiguration is supported only with JTAG and Selectmap interfaces. > > Which is the best avilable hardware reference design for the Virtex5 > series? I mean one from which you may learn about configuration, DDR2 > interfacing, RocketIO, power supply tricks (after you've read > datasheets and application notes). > I did not try to find one. I think that you can get some design (Schemetics) from Avnet website, If the designed any...... Hope it works MHArticle: 120657
Hello group.
As some of you requested it, I have updated the KCAsm pico/pacoblaze
assembler. The new version supports register aliases (really
implemented as aliases for any kind of assembler symbols), and also
the generation of "mem" files to be used with the data2mem utility. If
you are interested, feel free to test it and send me any reports if
you find bugs. The distribution is available at
http://bleyer.org/pacoblaze/kcasm-2.3-beta1.zip.
Please, if you also encounter bugs in the PacoBlaze core don't
hesitate to contact me. Over the last years the main source of
improvement of PacoBlaze has been user bug reports. I use the core a
lot in my projects and correct the errors I find on the fly, but that
is not a true coverage test.
BTW, lately I have been running 3 customized and reprogrammable
PacoBlazes running in parallel in my Marmaduke board (http://
bleyer.org/marmaduke.jpg) for peripheral control (SPI devices, MIDI
and a bus similar to CAN). The core really excels in that kind of
applications ;-)
Cheers!
--
/"It would appear that we have reached the limits of
PabloBleyerKocik / what it is possible to achieve with computer
technology,
pablo / although one should be careful with such statements,
as
@bleyer.org / they tend to sound pretty silly in 5 years."-J.von
Neumann
Article: 120658> Beyond than the really important home projects, > like hi-def Asteroids, I also have some homebrew > RF test equipment in mind. > > > I hopefully will have an S3E board set up for other > purposes in the next month or few, I'll try to look > at some LVDS -> TMDS biasing schemes when I do. > Yeah, it can't be that hard. If you figure out the analogue stuff the DCI encoding is fairly easy I think. Wonder if you can get away with patching a socket onto the S3E board, I have one on my desk :) no, don't distract me, I'm in the process of releasing Frogger and Scramble - had enough of real work for this morning !! /MikeArticle: 120659
"Paul Leventis" <paul.leventis@gmail.com> wrote in message news:1181666559.404950.181080@i13g2000prf.googlegroups.com... > > With some of our FPGAs, there can be signal integrity advantages of > physically connecting your unused I/Os to ground (regardless of > internal setting), primarily because this provides better ground > return current paths in the PCB under the FPGA (assuming you are using > through vias). Even if your outputs are set to "outputs driving > ground", you won't get much return current through the I/O buffer > itself -- but the act of adding the via will reduce the size of > inductive loops in the PCB via region, reducing your inductive > coupling. > > Regards, > > Paul Leventis > Altera Corp. > Hi Paul, So, I think you're saying the advantage is in having more ground vias, right? Attaching the I/O to the ground has only a small effect? Cheers, Syms.Article: 120660
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:5d59eaF32s4reU1@mid.individual.net... > I'm doing a PCB design for a client which incorporates a Cyclone II. > > I have only used two of the 8 dedicated clock pins so had left the > rest floating. > > During a schematic review one of the client's engineers said that he > thought it might be a good idea to tie the unused clock pins to GND. > > I have never done this before, I was under the impression that these > were weakly held high or low but can't find any reference to this in the > documentation. > > If these aren't pulled weakly I'd definitely add the extra few components, > but don't want to add extra stuff to be placed/routed/built if it's > not necessary. > > > What's the panel's view? Take a look at the .PIN file output and see what it has to say. 'Unused' pins will fall into one of the following categories, do as it suggests. -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. -- This pin should be connected to GND. It may also be connected to a -- valid signal on the board (low, high, or toggling) if that signal -- is required for a different revision of the design. -- GND* : Unused I/O pin. This pin can either be left unconnected or -- connected to GND. Connecting this pin to GND will improve the -- device's immunity to noise. -- RESERVED : Unused I/O pin, which MUST be left unconnected. -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. KJArticle: 120661
On Jun 11, 3:30 pm, Eric Smith <e...@brouhaha.com> wrote: > Brian Davis <brimda...@aol.com> writes: > > Seems like a simple bias network could shift the > > (DC-balanced) encoding scheme from LVDS to TMDS > > levels Yes, but it would not be HDMI or DVI compliant. We do this from the LVDS outputs on a Virtex4 to a MAX3814 cable equalizer. Simple capacitive coupling works, because there is a current source (pull up) in the CML inputs on this chip. > Can you get TMDS drivers that aren't part of a DVI transmitter chip > (which also does the encoding)? As above. Be careful, there are a number of things that won't work. Most CML stuff we looked at has a pullup in the ouput driver (which is not compliant with HDMI), instead of the input, which would also require pullup resistors to bias. Many of the TMDS muxes, are simple analog muxes, and not CML drivers. Cable equalizers are the only things that we found a year ago that seemed reasonable choices. Market may have changed. > It doesn't appear that DVI transmitter chips cost much, so is it > really worthwhile to try to avoid using one? 8 IO pins total required on the FPGA. Ability to embed audio or other data for HDMI. Complete control over the protocol. To go from an 8 bit data stream to a differential pair with TMDS encoding running at the max toggle rate of the FPGA pins is not a terribly difficult design to do. Three of these in parallel (with a very slight difference, depending on which channel it is) makes a complete interface. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 38 Chauncy St #1101; Boston, MA 02111 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 120662
I have generated a .bit file and try to program xc2v3000 FPGA but through impact gives a message that checking done pin.............done pin do not high , program terminated. so i verify operation in impact and impact gives a error message that top_design.msk does not exist . my qustion is where .msk file will be generated and is it really needed during programming FPGAs. i checked all other probable error possibilities , so please give comment.Article: 120663
Sunnyvale might be their next stop. The only barrier I see is the number of traffic lights to get past on the way there. I'd watch Ebay for such an item, or items, turning up for auction together. Unfortunately if they know what the stuff is they probably know someone in your area that will buy it. John Adair Enterpoint Ltd. "Bob" <nimby_NEEDSPAM@roadrunner.com> wrote in message news:JZmdnW5oj-f4y_LbnZ2dnUVZ_qqrnZ2d@giganews.com... > > "Tommy Thorn" <tommy.thorn@gmail.com> wrote in message > news:1181699439.988788.212790@n15g2000prd.googlegroups.com... >> My apologies to those who'd consider this spam, but my house in >> Milpitas, CA was burglarized and among the less mainstream objects >> stolen were a Tektronix THS730 oscilloscope and a Digilent Spartan >> 3E-1600 Development Board. >> >> If anyone comes across a suspect sale of this board for sale, please >> let me know. >> >> Thanks, >> Tommy >> > > Wow. High tech burglars in Milpitas. Maybe it's time to move to Sunnyvale. > > Sorry to hear about your loss. > > Bob > >Article: 120664
On Jun 12, 1:52 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > Xilinx does use digikey, so they also have NO MINIMUM order. > > I see no difference here, BOTH ARE BAD in that sense that the latest > and greatest silicon is NOT AVAILABLE. > > not from Xilinx online, not from Lattice online. > > Lattice could do an example here, and OFFER IMMEDIATE 1 OFF XP2 > example ONLINE orders > > I bet most people would instanlty order. > > just 1 per customer, GIFT PACKAGED XP2 sample. One click order, no > questions, just PAY and get it. > > but eh, one can always dream... I do > > well, while dreaming that Xilinx/Lattice would improve their online > store to include ES silicon, guess what I am designed in? Actel PA3, > gee the QFN132 package is real nice one, glad to see XP2 includes this > package as well. To Lattice, I would have preferred XP over PA3, but > there was no tiny package available. Xilinx, same words: S3AN in > QFN132 would win many designs over MAX2,machXO,PA3,XP2... but S3AN > only has big ugly packages :( The reason that engineering samples are not available through online ordering is because this is a critical phase for a manufacturer and they want two things; one is to know who the customers are so they can learn as much as possible about the customer and application (including the sales potential, which is crucial and gets reported up the food chain) and to be able to provide support, sometimes in a proactive way. With new parts, FPGA makers prefer to give out early engineering samples to the companies with larger potential and more experience. The support a company can offer has a finite limit, so they want to make sure their biggest customers are successful first, then they can go after the smaller buyers. You have to consider the vendor's position and give them a little slack on early sampling. If they don't meet their goals in this early stage, it can doom a product that may never catch up!Article: 120665
"J.Ram" <jrgodara@gmail.com> wrote in message news:1181732731.232269.185750@d30g2000prg.googlegroups.com... >I have generated a .bit file and try to program xc2v3000 FPGA but > through impact gives a message that checking done pin.............done > pin do not high , program terminated. > so i verify operation in impact and impact gives a error message that > top_design.msk does not exist . > my qustion is where .msk file will be generated and is it really > needed during programming FPGAs. > i checked all other probable error possibilities , so please give > comment. > http://groups.google.com/advanced_search?q=done%20impact search comp.arch.fpga HTH, Syms.Article: 120666
<SPAM> Pleased to announce the release of Frogger and Scramble (with source code) at www.fpgaarcade.com. Enjoy.... </SPAM>Article: 120667
On Jun 11, 2:42 pm, "MikeJ" <m...@fpgaarcade.nospam.com> wrote: > I looked into this, then realised you can buy a small chip which not only > had a decent DAC to give you RGB analogue outputs, it also drives DVI. > There is one on the cheaper V5 eval board from Xilinx. As I need a DAC > anyhow it seems the way forward ... > /Mike > > Brian- Hide quoted text - > > - Show quoted text - Whats the device that has DAC and DVI outputs? does it also have a color space converter? Ycrcb to RGB?? The only one I saw was a chrontel 7303 and they never answer my calls or emails... thanks -BillArticle: 120668
Can I do this all in a FPGA? I would like to sync to an incoming pulse (its actually going to be a register write) that I will receive at approx 100hz, and generate a 8Khz output clock. This will be a recovered sync from a master device, but the devices are SW based so there will be a fair amount of jitter (~+/- 500us) .. but this jitter is expected to be bounded and stable (not slipping in time) over a long period. Is it possible to use a local 50Mhz oscillator and create and up/down counter based on the 100hz signal, then slightly adjust the 8Khz clock rate based on this? I=E2=80=99m a newbie so please bare with me =EF=81=8A. Is there something out their like this? I did some searches, but seems most PLL type applications are not syncing to such a slow input (100hz). Also I am only concerened with long term frequency lock (well average) from the master providing the 100hz to the slave generating the 8Khz (the 100hz is based on the master 8K on the other side of the network, unfortunitly I cannot increase the 100Hz pulse rate) I would like to try to keep this all digital if possible since I do not have a local PLL on board to work with.. I do have a Altera Cyclone II FPGA that I will be targeting for this application. Thanks much! -BillArticle: 120669
ch7301c http://www.chrontel.com/products/7301.htm I am rather worried about sourcing it though. "ZR1TECH" <ZR1TECH@gmail.com> wrote in message news:1181740275.313996.152770@a26g2000pre.googlegroups.com... > On Jun 11, 2:42 pm, "MikeJ" <m...@fpgaarcade.nospam.com> wrote: >> I looked into this, then realised you can buy a small chip which not only >> had a decent DAC to give you RGB analogue outputs, it also drives DVI. >> There is one on the cheaper V5 eval board from Xilinx. As I need a DAC >> anyhow it seems the way forward ... >> /Mike > >> > Brian- Hide quoted text - >> >> - Show quoted text - > > Whats the device that has DAC and DVI outputs? does it also have a > color space converter? Ycrcb to RGB?? > The only one I saw was a chrontel 7303 and they never answer my calls > or emails... > thanks > -Bill > >Article: 120670
Hi Could someone just confirm for me that I can connect the config block to 3.3V in a Virtex 4 device. I have checked the data sheet and it seems to indicate this. I just want to check as I have been using Virtex 2 Pro devices which need to be 2.5V. JonArticle: 120671
> You do not need to connect unused general or clock inputs to ground if > you configure them as "inputs tri-stated with weak pull-up" or as > "outputs driving ground" in Quartus. Paul, Looking at the data sheet for CycloneII (I think, it was last week) the dedicated clock inputs didn't look like they had this option. I've just done a test build setting the unused clock inputs to 'tri-stated with weak pullups' with a CycloneI. In the *.pin file the unused clock was listed as GND+ .... -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. -- This pin should be connected to GND. It may also be connected to a -- valid signal on the board (low, high, or toggling) if that signal -- is required for a different revision of the design. So it looks like unused clocks _should_ be tied somewhere (through a resistor to keep the assembly test people happy). NialArticle: 120672
On Wed, 13 Jun 2007 13:27:39 -0000, ZR1TECH <ZR1TECH@gmail.com> wrote: >Can I do this all in a FPGA? > >I would like to sync to an incoming pulse (its actually going to be a >register write) that I will receive at approx 100hz, and generate a >8Khz output clock. Yes, definitely. Getting *really* good results may be quite tricky, though. > >This will be a recovered sync from a master device, but the devices >are SW based so there will be a fair amount of jitter (~+/- 500us) .. >but this jitter is expected to be bounded >and stable (not slipping in time) over a long period. > >Is it possible to use a local 50Mhz oscillator and create and up/down >counter based on the 100hz signal, then slightly adjust the 8Khz clock >rate based on this? For sure. The interesting question is, what are you really trying to achieve? Are you trying to ensure that yuo get as nearly as possible 80 output pulses between each pair of 100Hz register writes? Or are you trying to get an essentially constant frequency that is, over very long periods, locked to the long-term average of the 100Hz? What I'm getting at is that anything that responds promptly to changes in the 100Hz input will obviously cause jitter on the 100 Hz to propagate to the output. Likewise, anything that smooths the 8kHz output so that it has minimal jitter, and its frequency changes slowly and smoothly, will of course fail to respond to rapid changes in the 100Hz signal's behaviour. You need to know something about the statistics of the reference signal, and the desired behaviour of the output. Having said all that, the frequencies you describe are so slow that you have LOTS of time to do any calculations that might be needed; so you can do quite sophisticated filtering with a small amount of hardware (or even with software in an embedded CPU of some kind). I did something loosely similar when I wanted to know the exact position of a rotating flywheel, but could see only a single index pulse per revolution. In that case I was able to make use of the known physics of the rotating object, and the known behaviour of the index pulse sensor, to make things work better. Some interesting juggling was necessary to get the thing into lock quickly at startup time - it's often a good idea to have two operating modes, "acquiring lock" and "holding lock". And then you have to be VERY careful about what happens as you transition from one mode to the other. By the way: that example was recovering a roughly 5kHz pulse train from a roughly 30Hz signal, and I did it all in a little PIC microcontroller! And no, you can't have the code; it was so long ago that I have certainly lost it all! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 120673
Hi, I have a core which generates 400+ parallel outputs per once. Each output can take only 3 possible values only: A,B,C [they can be coded in binary using only 2 bits]. I am looking to write these 400+ outputs to the off chip ram, the quickest time possible, without affecting the core processing speed or halting its execution. Do you see any smart implementation to achieve this goal! The core processes a 16-bit input word I am using Virtex-II Pro with one off chip bank sram Many thanks :)Article: 120674
MikeJ wrote: > Pleased to announce the release of Frogger and Scramble (with source > code) at www.fpgaarcade.com. Cool! You also have the Scramble protection I see - that had me beat... I'm guessing that since the equations are now public, then there's no reason why MAMEDEV can't be given that information to replace the dodgy hack that's in the Scramble driver atm? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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