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an unhappy owner of the fresh new Spartan-3A development kit from Xilinx: reason for unhappiness: 1) NO examples how to use DDR2 IP core with Spartan3A 2) NO EDK reference design for this board at all 3) NO EDK Board support package available Spartan 3A is only supported by EDK 9.1, but EDK 9.1 seems have bugs that force the need to run synthesis manually (automated build doesnt work) Should we now really wait EDK 9.1 SP2 ? My Spartan-3A kit was delayed at post for 30 days, so when i finally got it I was extremly happy!!! But it seems it arrived too early as Xilinx has not support for this board yet? :( AnttiArticle: 118576
I understand that there will be skew. But the alternative solution to run source synchronous is lot more complex. The Paralllel LVDS I/Os from V5 run at maximum speed of 1 Gbps per channel. I have to run them trhough external 4:1 high speed mux (16 of these) to get 16 high speed channels each running at 3.2 Gbps each. This is possible but it is not simple task either. I understand that there will be a skew of 1 to 3 UI from channel to channel but as per my understanding this skew is fixed. Thus if there is a 5 ps resolution software programmable delay element in line with the high speed channels then the mis aligned channels can be aligned usinng the software programmable delay elements. For example if I need 16, 3.2 Gbps data channels then I use the 17th channel as a forwarded clock running at 1.6 GHz. Again all 17 channels can go through the precise delay elements for channel alignement purpose. On power-up the link will operate at slowest possible speed say 100 Mbps but the transceivers can keep on running at 3.2 Gbps. The FPGA fabric will pass the data 32 times in order to make it run at slower speed of 100 Mbps. In this mode 1 to 3 UI misalignment may not be a problem as it will be running at such a slow speed. When changed to higher speed (3.2 Gbps), there will be a training algorithm to align the channels using software programmable delay elements.Article: 118577
MNiegl wrote: > Hi everyone, > > I have a problem that is bugging me for 2 days now and I was hoping > someone here might be able to help me out. > The problem is as follows: > I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA > on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which > I want to derive from the on-board 100 MHz oscillator. For this I need > to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for > all the other frequencies the RAM controller [generated with MIG 1.6] > needs (main problem is the 200 MHz shifted by 90 deg). The first one > works perfectly fine, only the second one never locks. [snip] Hi, I had all kinds of problems (DCMs not locking was one of them) with MIG 1.6 and a Virtex4FX 100. I'd strongly advise you upgrade to MIG 1.7. RobArticle: 118578
On Apr 30, 3:29 pm, Rob Dimond <r...@nospam.maxeler.com> wrote: > MNiegl wrote: > > Hi everyone, > > > I have a problem that is bugging me for 2 days now and I was hoping > > someone here might be able to help me out. > > The problem is as follows: > > I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA > > on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which > > I want to derive from the on-board 100 MHz oscillator. For this I need > > to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for > > all the other frequencies the RAM controller [generated with MIG 1.6] > > needs (main problem is the 200 MHz shifted by 90 deg). The first one > > works perfectly fine, only the second one never locks. > > [snip] > > Hi, > > I had all kinds of problems (DCMs not locking was one of them) with MIG > 1.6 and a Virtex4FX 100. I'd strongly advise you upgrade to MIG 1.7. > > Rob Hi, In the meantime I found a work-around using a FX20 as a "clock generator". I basically just moved the first of the 2 DCMs into the other FPGA and now feed an LVDS 200 MHz coming from a DCM into the bigger FPGA. Surprisingly, now the second one immediately locked. We'll see if the rest of the RAM controller does so as well. I still might try an update to MIG 1.7, I have just been a bit reluctant to do so as this would also mean migrating to ISE 9.1 and I don't want to switch software versions while working on a single project (which I'm doing since about 8 months now) if not absolutely necessary. This might be a point where it is absolutely necessary though. Cheers, MichaelArticle: 118579
On Apr 30, 3:55 am, Antti <Antti.Luk...@xilant.com> wrote: > Latest example: > MicroBlaze Working Design with EDK 8.1 > Update to EDK 8.2 -> DDR Memory failing (was working with 8.1) > Update to EDK 9.1 -> : > > ./synthesis.sh: line 2: $'\r': command not found > > !? > > If Xilinx really does ANY software testing before release things like > that should no happen. These could be actual functional bugs, but they sound a lot more like version problems - options changing between versions without enough thought put into the impact on existing designs. Looks like there could be issues with both tool options, and perhaps paramaters passed to bundled functional blocks?Article: 118580
..but working fine using 32bit install (bin/nt/setup.exe of the DVD). Anyone have (or have a solution to) this problem?Article: 118581
Antti <Antti.Lukats@xilant.com> writes: > Hi > > I really dont understand why Xilinx isnt hiring people who can develop > and test software? > Is the world-wide shortage of engineers really that bad? > > Latest example: > MicroBlaze Working Design with EDK 8.1 > Update to EDK 8.2 -> DDR Memory failing (was working with 8.1) > Update to EDK 9.1 -> : > > ./synthesis.sh: line 2: $'\r': command not found I had that one too - I faffed around for a bit to sort it. I can;t find my notes, but I think I had to downgrade my cygwin bash IIRC, much like we had to do with make in a previous incarnation. To be fair, it broke on my own .bashrc as well - I may have ticked the wrong box on the Cygwin install for DOS/Unix file formats... I currently have: $ bash --version GNU bash, version 2.05.0(1)-release (i686-pc-cygwin) Copyright 2000 Free Software Foundation, Inc. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 118582
I need some vhdl code to configure a xupv2p board and how I'm supose to do the implementation part.Article: 118583
Wooooo! A new record! <rogodani@gmail.com> wrote in message news:1177946755.075527.289820@n76g2000hsh.googlegroups.com... >I need some vhdl code to configure a xupv2p board and how I'm supose > to do the implementation part. >Article: 118584
<rogodani@gmail.com> wrote in message news:1177946755.075527.289820@n76g2000hsh.googlegroups.com... >I need some vhdl code to configure a xupv2p board and how I'm supose > to do the implementation part. You need a programming cable and Xilinx software to configure your xupv2p board. So what are you asking for?Article: 118585
Wow... possibly the MOST impressively vague request for help I've ever read on here! And there are often some very very vague posts on here... that's really rather impressive. Often you get grammatically incorrect and technically incorrect... but such an graceful combination of the two is really a find. "I need some vhdl code..<etc..>.. and how I'm supose to do the implementation part" - yeaup, certainly not and english sentance. Missing a noun I would think... perhaps... "I need some vhdl code and INSTRUCTIONS for how i'm supposed to <etc..>"? Something along those lines. And for the technical side... "I need some vhdl code to configure a board".... boards don't get configured last I checked.. fpga's do... and thats gets done by a bitstream ... which gets programmed into a configuration prom.... and is synthesized from vhdl code... which puts us a grand total of 3-4 degrees of freedom between VHDL code and Configuration... it's almost as fun as playing 7 degrees of kevin bacon! :-) I could probably find a better use of my lunch hour... but this is just way too much fun. On Apr 30, 11:25 am, rogod...@gmail.com wrote: > I need some vhdl code to configure a xupv2p board and how I'm supose > to do the implementation part.Article: 118586
As far as I know, VMetro does not have any TS201 based boards. However, you will find ones at www.bittware.com with TS201s and PCI interfaces. ----- Ron Huizen BittWare "colin" <colin_toogood@yahoo.com> wrote in message news:1177922732.403279.153230@u30g2000hsc.googlegroups.com... > On 28 Apr, 09:24, eapen.abraham@gmail.com wrote: >> Hi, >> >> Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656 >> device? I'm trying to implement this in a current project and need >> details. The bridging is done via an Altera FPGA which also has to >> have custom logic for other functions such as Ethernet, sFPDP,etc. >> >> I know that the TS201 core runs at 600 MHz and the I/O bus at around >> 83.5 MHz. But at what speed does the PLX 9656 local bus run? Can the >> TS201 be connected directly to the PLX chip? Are there anyother >> alternatives to the PLX chip? > > If your budget can cope, I suggest www.vmetro.com for both of your > threads roday >Article: 118587
> Thanks Peter for the suggestion. But my problem is coming up with the
> state diagram for this FSM. How can I implement what you suggested on
> a state diagram? Thanks.
Here you go, I hope the ASCII art looks OK (if not, change to
monospaced font):
shift reg. = 111
+----+ --------------------> +----+
| S0 | | S1 |
+----+ <-------------------- +----+
shift reg. = 000
Article: 118588On Apr 27, 2:22 pm, Austin Lesea <aus...@xilinx.com> wrote: > Well, it seems that if you are doing everything right, and it worked > last time at 160 MHz, it has no excuse but to work this time. Michael, Did you turn offf autocalibration macro on the DCM? If not see this post: http://groups.google.com/group/comp.arch.fpga/msg/c6707d13feb794ad?hl=en& IIRC the autocalibration macro breaks around 200MHz... it is inserted automatically. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 38 Chauncy St #1101; Boston, MA 02111 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 118589
<Anson.Stuggart@gmail.com> schreef in bericht
news:1177871564.475673.53180@y80g2000hsf.googlegroups.com...
> I'm designing a debounce filter using Finite State Machine. The FSM
> behavior is it follows the inital input bit and thinks that's real
> output until it receives 3 consecutive same bits and it changes output
> to that 3 consecutive bit until next 3 consecutive bits are received.
> A reset will set the FSM to output 1s until it receives the correct
> input and ouput.
>
> This is the test sequence with input and correct output.
>
> 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
> 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
>
> The state diagram I came up has 6 states and it's named SEE1, SEE11,
> SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
> the input. Because it just came from SEE1 and before SEE1, it came
> from SEE000, so at SEE1 it can not change ouput to 1 which is what I
> have specified that state's ouput to be.
>
> Anyone knows how to solve this problem? Or maybe there's other better
> ways to design the state diagram?
>
> Thanks,
>
> Anson
>
Came into this this discussion late. Read the available texts but sure
missed some due to the "experimental" status of my ISPs newsserver. Also did
not analyse the tables to make sure I make my own mistakes:) So I came to
the next table:
Input Curent Next
state state
0 000 000
1 000 001
0 100 000
1 100 001
0 001 000
1 001 011
0 011 000
1 011 110
0 110 111
1 110 110
0 010 111
1 010 110
0 111 101
1 111 110
0 011 000
1 101 110
0 101 000
All possible (eight) states have been accounted for. As you need only six
states, you can combine state 000 with state 100 and state 110 with state
010. The leftmost bit of the state code is your output signal. See state
diagram below.
+--+
0| |
| v
.------.
| 000 |----------+
+--------->| 100 | |
| | |<------+ |
|0 '------' | |1
| ^ 0| |
| | | v
.------. |0 .------.
| | | | |
| 101 | | | 001 |
| |---------+ | | |
'------' | | '------'
^ | | |
| | | |1
|0 | | |
| | | v
.------. | | .------.
| | | +-------| |
| 111 | | | 011 |
| | | | |
'------' 1| '------'
^ | | |
| | v |
0| |1 .------. |1
| +-------->| | |
| | 110 |<------+
+------------| 010 |
'------'
| ^
1| |
+--+
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
petrus bitbyter
Article: 118590Hi everybody, I would like to obtain people's opinion on the use of different synthesis tools to target FPGA designs. I am thinking of tools from Synopsys, Mentor graphics and synplicity. If there are others, I would like to know. These are excellent for targetting ASIC designs where every little space and power dissipation is critical. My question is, is it worth using these expensive tools when there are also synthesis tools created by the manufacturers of the FPGAs such as xilinx ISE which is free.(I use xilinx exclusively. Sorry to the Altera fans out there). Secondly are the first tools much much more efficient than the ones xilinx offers such that the gain obtained from them offsets the cost of the tool. Thirdly which one is better for Xilinx FPGAs. Thanks a lot for your time, AmishArticle: 118591
On Apr 29, 3:12 pm, John Popelish <jpopel...@rica.net> wrote: It was a bit larger than I remembered, but if anyone is interested, here is the code I used to debounce and edge detect an 8 bit PIC port. This process was called once a millisecond. ; read port C, debounce and fire single shots ; shift input data down movf cinfil,w ; fetch cinfil movwf cinfil1 ; copy to cinfil1 bsf STATUS,RP0 ; select regiater page 1 movf cin1,w ; fetch 1ms old values movwf cin2 ; overwrite 2ms old data movf cin,w ; fetch stale value of cin movwf cin1 ; store as 1ms old data bcf STATUS,RP0 ; select regiater page 0 ; read new port C values movf PORTC,w ; read port C bsf STATUS,RP0 ; select register page 1 movwf cin ; store port C data in cin ; (0=start, 1=up, 2= down, 3=home, 4=temp high not, 5=temp low not, 6=lid closed, 7=spare) ; debounce requires 3 similar states in a row to supercede filtered value ; and cin, cin1 and cin2 to detect 3 1s in a row andwf cin1,w ; and 1 ms old data with new version andwf cin2,w ; and 2 ms old data with this movwf cinand ; save this combination for later ; or cin, cin1 and cin2 to detect three 0s in a row movf cin,w ; get latest values iorwf cin1,w ; or latest and 1ms old data iorwf cin2,w ; or 2 ms old data with this andwf cinfil1,w ; and debounced state of port C inputs with this ; to clear any 1s that have been followed by 3 0s in a row. iorwf cinand,w ; or cinand, to set any zeros that have been followed ; by 3 1s in a row. movwf cinfil1 ; update filtered (debounced version of port C inputs) bcf STATUS,RP0 ; select register page 0 movwf cinfil ; update filtered (debounced version of port C inputs) bsf STATUS,RP0 ; select register page 1 ; fire turn on and turn off single shots ; if present is off and last was on, set "off ss" bit comf cinfil1,w ; compliment cinfil bits andwf cinfld,w ; and with delayed bits bcf STATUS,RP0 ; select register page zero movwf cinofss ; store as turn off single shot bits bsf STATUS,RP0 ; select register page 1 ; if last was off, and present is on, set "on ss" bit comf cinfld,w ; compliment delayed inputs andwf cinfil1,w ; and current value of inputs bcf STATUS,RP0 ; select register page 0 movwf cinonss ; store as turn on single shot bitsArticle: 118592
> My question is, > is it worth using these expensive tools when there are also synthesis > tools created by the manufacturers of the FPGAs such as xilinx ISE > which is free. Yes. They have better quality of results and less bugs. Well, Synplify does anyway. > (I use xilinx exclusively. Sorry to the Altera fans out > there). No doubt they will be gutted. > Secondly are the first tools much much more efficient than the > ones xilinx offers such that the gain obtained from them offsets the > cost of the tool. Depends on the design. > Thirdly which one is better for Xilinx FPGAs Synplify Pro. Cheers, JonArticle: 118593
jpopelish@rica.net wrote: > On Apr 29, 3:12 pm, John Popelish <jpopel...@rica.net> wrote: > It was a bit larger than I remembered, but if anyone is interested, > here is the code I used to debounce and edge detect an 8 bit PIC > port. This process was called once a millisecond. None of this is topical in comp.lang.c. Please remove that group from your distribution. Thanks. BrianArticle: 118594
billwang05@gmail.com wrote, On 30/04/07 04:42: <snip> > Do you mean a 1 in the input string at power-up or after reset? If so, > state Init_1&SEE111 is where it should go. Would people PLEASE drop comp.lang.c from the groups, as this is OBVIOUSLY not topical in a C programming group. -- Flash GordonArticle: 118595
axr0284 wrote:
> My question is,
> is it worth using these expensive tools when there are also synthesis
> tools created by the manufacturers of the FPGAs such as xilinx ISE
> which is free.
I would not buy special synthesis tools
until I found a problem with the vendor tools.
I find that good simulation tools get the
most use and provide the most value during design.
I need synthesis to check fit and fmax,
but edit, sim, edit, sim,... is the tight loop.
> Secondly are the first tools much much more efficient than the
> ones xilinx offers such that the gain obtained from them offsets the
> cost of the tool. Thirdly which one is better for Xilinx FPGAs.
I know of one case where a Mentor tool
fit a design that wouldn't fit with ise.
I know of no such cases with quartus,
but I don't doubt that they exist.
-- Mike Treseler
Article: 118596It's simple; just stop eating. But be careful not to overdo it, and remember to keep drinking... Oh, sorry, you mean *quickly*. -- Mit der Dummheit kämpfen Götter selbst vergebens.Article: 118597
there is one example in sdram directory of s3ask_test design (follow 3A reference design in xilinx web site), but this is only an implementation of the DDR2 testbench ; the one that is generated with mig 1.7. (a led blink if memory fails) In mig user guide ug086, there is a brief explanation of the design ; and I am too new to design to use it without tb (i.e. read / write example from fpga with picoblaze would be a must...) ; if you can help, I will apperciate. I got 3 starter kit 3A from avnet in less than 1,5 week On Apr 30, 2:43 pm, Antti <Antti.Luk...@xilant.com> wrote: > an unhappy owner of the fresh new Spartan-3A development kit from > Xilinx: > > reason for unhappiness: > > 1) NO examples how to use DDR2 IP core with Spartan3A > 2) NO EDK reference design for this board at all > 3) NO EDK Board support package available > > Spartan 3A is only supported by EDK 9.1, but EDK 9.1 seems have bugs > that force the need to run synthesis manually (automated build doesnt > work) > > Should we now really wait EDK 9.1 SP2 ? > > My Spartan-3A kit was delayed at post for 30 days, so when i finally > got it I was extremly happy!!! > > But it seems it arrived too early as Xilinx has not support for this > board yet? :( > > AnttiArticle: 118598
one more complaint... I was really disappointed that the EDK evaluation software was not bundled and shipped with 3A kits (it was in 3E)...Article: 118599
rogodani@gmail.com wrote: > I need some vhdl code to configure a xupv2p board and how I'm supose > to do the implementation part. > Get some software to run on a cpu and then you just design it
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