Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On May 1, 8:41 am, ZHI <threeinchn...@gmail.com> wrote:
> Hi,
> I want to learn using textio. Here I use Read data from scr.txt to IP
> core RAM and Write them to the text1.txt. I wrote the codes here but
> it doesn't work. Any suggestions about this is very appreciated.
> One more thing, when i use Modelsim to Run by step. It alway gives the
> error information and cannot finish the simulation. I don't what it
> means.
> ******************************************************
> Trace back: Error opening C:/Documents and Settings/zq500/Local
> Settings/Temp/xil_1700_6
> # while executing
> # "error $winName"
> # (procedure "view" line 82)
> # invoked from within
> # "view source"
> # (procedure "vsimcmd::viewProcessSource" line 2)
> # invoked from within
> # "vsimcmd::viewProcessSource /check/uut/u0/select_outputb"
> # ("after" script)
> # 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
> Settings/Temp/xil_1700_6}
> # 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
> Settings/Temp/xil_1700_6}
> **************************************************************************
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_signed.all;
> use ieee.std_logic_textio.all;
> use std.textio.all;
>
> entity check is
> end check;
>
> architecture serial of check is
>
> component checkram
> port (
> addra: IN std_logic_VECTOR(2 downto 0);
> addrb: IN std_logic_VECTOR(2 downto 0);
> clka: IN std_logic;
> clkb: IN std_logic;
> dina: IN std_logic_VECTOR(7 downto 0);
> doutb: OUT std_logic_VECTOR(7 downto 0);
> wea: IN std_logic);
> end component;
>
> signal addra: std_logic_vector(2 downto 0):=(others=>'0');
> signal addrb: std_logic_vector(2 downto 0):=(others=>'0');
> signal dina: std_logic_vector(7 downto 0) :=(others=>'0');
> signal doutb: std_logic_vector(7 downto 0) :=(others=>'0');
> signal wea: std_logic :='1';
> signal wrd: std_logic :='0';
> signal clk : std_logic :='0';
> signal reset: std_logic :='1';
> file from_file:text open READ_MODE is "src.txt";
> file to_text:text open WRITE_MODE is " text1.txt";
> begin
> UUT:checkram port map
> (
> addra => addra,
> addrb => addrb,
> clka => clk,
> clkb => clk,
> dina => dina,
> doutb => doutb,
> wea =>wea
> );
>
> clock_process: PROCESS
> BEGIN
> clk <= NOT (clk);
> WAIT FOR 5 ns;
> END PROCESS clock_process;
>
> reset <= '0' after 1 ns;
>
> ramRd: process (clk,reset)
> variable buf_out,buf_in:line;
> variable num: std_logic_vector(7 downto 0):=(others=>'0');
> variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
> begin
> if reset='1' then
> iptaddr :=(others=>'0');
> elsif clk'event and clk='1' then
> while not (endfile(from_file))loop
>
> READLINE(from_file,buf_out);
> READ(buf_out,num);
> WRITE (buf_in,doutb);
> WRITELINE(to_text,buf_in);
> wea <='1';
> addra<=iptaddr;
> dina<= num;
> iptaddr:=iptaddr+"1";
> end loop;
> end if;
> end process;
> ---------------------------------------
> addPro: process (addra,reset)
> begin
> if reset='1' then
> wea<='1';
> wrd<='0';
> elsif addra = "111" then
> wea<='0';
> wrd <='1';
> end if;
> end process;
> ----------------------------------------
> output: process(clk,wrd,reset)
> variable buf_in:line;
> variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
> begin
> if reset='1' then
> addrb <=(others=>'0');
>
> elsif clk'event and clk ='1' then
> if wrd <= '1' then
> addrb <= addrb+"001";
> end if;
> WRITE (buf_in,doutb);
> WRITELINE(to_text,buf_in);
>
> end if;
> end process;
> end serial;
ZHI,
Below is what I got. The src.txt was referenced to my current
modelsim directory. When I created the file, that error went away.
I think the error you got was from the component checkram whose code
you did not post.
Newman
---------------------------------------------------------------------
# //
# Loading C:\eda\Modeltech_6.2c\win32pe/../std.standard
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_1164(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_arith(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_signed(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../std.textio(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_textio(body)
# Loading work.check(serial)
# ** Error: (vsim-7) Failed to open VHDL file "src.txt" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
vhdl_tb/fileio.vhd
# ** Warning: (vsim-3473) Component instance "uut : checkram" is not
bound.
# Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
vhdl_tb/fileio.vhd
Article: 118626On Apr 30, 2:55 am, Antti <Antti.Luk...@xilant.com> wrote: > Hi > > I really dont understand why Xilinx isnt hiring people who can develop > and test software? > Is the world-wide shortage of engineers really that bad? > > Latest example: > MicroBlaze Working Design with EDK 8.1 > Update to EDK 8.2 -> DDR Memory failing (was working with 8.1) > Update to EDK 9.1 -> : > > ./synthesis.sh: line 2: $'\r': command not found > > !? > > If Xilinx really does ANY software testing before release things like > that should no happen. > With ALL latest major releases the "time to first fatal error" from > the new install has been > less than 20 minutes. This is not acceptable for software that is to > be used to develop > commercial products. > > Should i go back to EDK 8.1 for this one design? > > Antti, > who really doesnt want to start another fight to get the buggy xilinx > sw to work. The synthesis error you have reported usually comes from having the newer bash shell installed which no longer accepts the Windows carriage return. Refer to Xilinx Answer Record 24134: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=24134 Cheers, SteveArticle: 118627
On 30 Apr 2007 05:13:44 -0700, mludwig <gyelod@gmail.com> wrote: >I get the following error in PACE after starting "Assign Package Pins" >in ISE 9.1 SP3: >ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhdl' or >'verilog' keyword, found 'work'. >It happens with a clean new project and a single top-level VHDL module >and its constraint file. >It seems that nobody encountered this issue before. Any ideas? Looks like you've included a .prj file into the project.... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 118628
John, We generally try to discourage cascading, as the jitter only increases. That said, we do expressly prohibit a cascade of the CLKFX output to the input of another DCM (not supported). So, we do support the DLL outputs, to the next DCM input type of cascade. In V5, with the PLL, we can now do whatever cascading you want, as long as there is a PLL between the DCMs (any output to PLL, PLL to input of next DCM). Since customers have such a hard time characterizing their jitter, it is simpler to generally recommend against cascading. It is also true that a single DCM can provide a great deal of functionality, and all of its outputs can be used (potentially). Often a cascade DCM design can be done by two DCMs in parallel. Like a PLL, the DCM only fails one way: it fails to lock, or loses lock. That said, the causes are those which I have already detailed: too much jitter, input frequency changing while trying to lock, frequency changing after lock, missing pulses. AustinArticle: 118629
I have a new board where I switched from the xcf08p to the xcf32p serial prom devices. The 32p programs fine and when I cycle power the current jumps up and my test led lights which should mean that the fpga is configured. However, the PPC in the v4fx12 device is dead or not running. Running XMD returns all zeros for the processor ID and I get no output from my bootloader code. Downloading the fpga manually works fine. One other difference is that I'm using the revision select lines on the 32p where I didn't on the 08p but the lines are both set correctly and it does appear that the fpga loads but then freezes. Any ideas what might cause this? Thanks, ClarkArticle: 118630
On May 1, 10:50 am, "cpope" <cep...@nc.rr.com> wrote: > I have a new board where I switched from the xcf08p to the xcf32p serial > prom devices. The 32p programs fine and when I cycle power the current jumps > up and my test led lights which should mean that the fpga is configured. > However, the PPC in the v4fx12 device is dead or not running. Running XMD > returns all zeros for the processor ID and I get no output from my > bootloader code. > > Downloading the fpga manually works fine. > > One other difference is that I'm using the revision select lines on the 32p > where I didn't on the 08p but the lines are both set correctly and it does > appear that the fpga loads but then freezes. Any ideas what might cause > this? > > Thanks, > Clark Clark, Don't understand the relationship to this thread but I found something on the Xilinx website that may or may not be related to what you are seeing. I did not read the errata. ----------------------------------------------------------------------------------------------- XCF08P, XCF16P, & XCF32P Errata and Deviations from the Data Sheet Intermittent Power Ramp Fa A test escape has been discovered with the devices named above which for some applications results in device failure during "Power on Reset Activation." Devices that have a VCCint ramp during "Power on Reset Activation" that takes longer than 1ms to reach 1.6V may see failures. Associated Products: Configuration PROMs ------------------------------------------------------------------------------------------------ NewmanArticle: 118631
On Apr 28, 4:09 pm, jhal...@TheWorld.com (Joseph H Allen) wrote:
> This is the way I make arbiters:
>
> // Concise priority arbiter
> input [26:0] req; // Bit zero is highest priority
> wire [26:0] gnt = req & -req; // Isolate least significant set bit
>
> Since this method uses fast carry logic, it's quite fast- the best win is in
> FPGAs, where the carry chain is much faster than regular routing. If you
> can do a 32-bit add in one cycle, you can certainly do a 27-bit priority
> arbiter. With ASICs or fully custom, you can pick the carry lookahead method
> of your choice. Notice also that it is very easy to parameterize.
>
> It's not hard to make a full round-robin arbiter out of this:
>
> reg [26:0] prev; // Previous winner (saved from last cycle)
> wire [26:0] req1 = req & ~((prev - 1) | prev); // Mask off previous winners
> wire [26:0] gnt1 = req1 & -req1; // Select new winner
> wire [26:0] winner = |gnt1 ? gnt1 : gnt; // Start from bit zero if none
>
> // Save previous winner
> always @(posedge clk) if (winner) prev <= winner;
>
> The idea is that this expression converts from "one-hot" coding to
> "thermometer" coding: ((x-1)|x))
>
> Want more tricks? I highly recommend Henry Warren's _Hacker's Delight_:
> http://www.hackersdelight.org
>
> See also HAKMEM- MIT AI Lab Memo No. 239:
> http://www.inwap.com/pdp10/hbaker/hakmem/hakmem.html
> (It seems that the people at the AI lab were interested in just about
> anything except AI :-)
>
> Also the unpublished (but downloadable) Volume 4A of Knuth's _The Art of
> Computer Programming_:
>
> http://www-cs-faculty.stanford.edu/~knuth/taocp.html
>
> --
> /* jhal...@world.std.com AB1GO */ /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Hi Joseph,
Thank you so much for you instruction.
> // Concise priority arbiter
> input [26:0] req; // Bit zero is highest priority
> wire [26:0] gnt = req & -req; // Isolate least significant set bit
>
> Since this method uses fast carry logic, it's quite fast- the best win is in
> FPGAs, where the carry chain is much faster than regular routing. If you
> can do a 32-bit add in one cycle, you can certainly do a 27-bit priority
> arbiter. With ASICs or fully custom, you can pick the carry lookahead method
> of your choice. Notice also that it is very easy to parameterize.
I'm so sorry that I can NOT understand your idea. Maybe, I should read
the documents you recommend first. Anyway, it would be great for me if
you spend your ttime explaining to me again.
> It's not hard to make a full round-robin arbiter out of this:
I've heard about it. And I understand your idea. Thanks a lots for
telling me.
Once again, thank you so much for your help.
Best regards,
Quang Anh
Article: 118632On May 1, 5:35 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On 30 Apr 2007 05:13:44 -0700, mludwig <gye...@gmail.com> wrote: > > >I get the following error in PACE after starting "Assign Package Pins" > >in ISE 9.1 SP3: > >ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhdl' or > >'verilog' keyword, found 'work'. > >It happens with a clean new project and a single top-level VHDL module > >and its constraint file. > >It seems that nobody encountered this issue before. Any ideas? > > Looks like you've included a .prj file into the project.... > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I got this error for every 9.1 project of mine, so I created a new project and added a single VHDL module (new). It has been made top module, and launched "Assign package pins" for it. Asked me, if I want to add a new ucf file to the design, answered yes and PACE opened, but with the error. ??? I am clueless.Article: 118633
On Apr 30, 8:09 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > ..but working fine using 32bit install (bin/nt/setup.exe of the DVD). > > Anyone have (or have a solution to) this problem? Hi Morten, You may be trying to install a configuration not supported on your platform. Check out Answer Record 23663: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23663 Hope this helps. -KamalArticle: 118634
"Newman" <newman5382@yahoo.com> wrote in message news:1178032912.349257.47850@e65g2000hsc.googlegroups.com... > On May 1, 10:50 am, "cpope" <cep...@nc.rr.com> wrote: > > I have a new board where I switched from the xcf08p to the xcf32p serial > > prom devices. The 32p programs fine and when I cycle power the current jumps > > up and my test led lights which should mean that the fpga is configured. > > However, the PPC in the v4fx12 device is dead or not running. Running XMD > > returns all zeros for the processor ID and I get no output from my > > bootloader code. > > > > Downloading the fpga manually works fine. > > > > One other difference is that I'm using the revision select lines on the 32p > > where I didn't on the 08p but the lines are both set correctly and it does > > appear that the fpga loads but then freezes. Any ideas what might cause > > this? > > > > Thanks, > > Clark > > > Clark, > Don't understand the relationship to this thread but I found > something on the Xilinx website that may or may not be related to what > you are seeing. I did not read the errata. > > -------------------------------------------------------------------------- --------------------- > XCF08P, XCF16P, & XCF32P Errata and Deviations from the Data Sheet > Intermittent Power Ramp Fa > > > A test escape has been discovered with the devices named above which > for some applications results in device failure during "Power on Reset > Activation." Devices that have a VCCint ramp during "Power on Reset > Activation" that takes longer than 1ms to reach 1.6V may see failures. > > Associated Products: Configuration PROMs > -------------------------------------------------------------------------- ---------------------- > > Newman > Thanks, but I get the same result whether I run from Impact or whether I power cycle the board. When I'm using Impact the board power supplies should be well settled so I don't think it's anything to do with transients at power up. -ClarkArticle: 118635
Hi, Please help. Where can I find the pass transistor's working curve under 1.2V that is widely used in IC design preferebly in any articles, instead of in books? Thank you. WengArticle: 118636
The checkram is generated by the IP core generator. Actually it has no
problem in the inital simulation. When I run by step the simulation,
It got the error information.
Newman wrote:
> On May 1, 8:41 am, ZHI <threeinchn...@gmail.com> wrote:
> > Hi,
> > I want to learn using textio. Here I use Read data from scr.txt to IP
> > core RAM and Write them to the text1.txt. I wrote the codes here but
> > it doesn't work. Any suggestions about this is very appreciated.
> > One more thing, when i use Modelsim to Run by step. It alway gives the
> > error information and cannot finish the simulation. I don't what it
> > means.
> > ******************************************************
> > Trace back: Error opening C:/Documents and Settings/zq500/Local
> > Settings/Temp/xil_1700_6
> > # while executing
> > # "error $winName"
> > # (procedure "view" line 82)
> > # invoked from within
> > # "view source"
> > # (procedure "vsimcmd::viewProcessSource" line 2)
> > # invoked from within
> > # "vsimcmd::viewProcessSource /check/uut/u0/select_outputb"
> > # ("after" script)
> > # 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
> > Settings/Temp/xil_1700_6}
> > # 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
> > Settings/Temp/xil_1700_6}
> > **************************************************************************
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_arith.all;
> > use ieee.std_logic_signed.all;
> > use ieee.std_logic_textio.all;
> > use std.textio.all;
> >
> > entity check is
> > end check;
> >
> > architecture serial of check is
> >
> > component checkram
> > port (
> > addra: IN std_logic_VECTOR(2 downto 0);
> > addrb: IN std_logic_VECTOR(2 downto 0);
> > clka: IN std_logic;
> > clkb: IN std_logic;
> > dina: IN std_logic_VECTOR(7 downto 0);
> > doutb: OUT std_logic_VECTOR(7 downto 0);
> > wea: IN std_logic);
> > end component;
> >
> > signal addra: std_logic_vector(2 downto 0):=(others=>'0');
> > signal addrb: std_logic_vector(2 downto 0):=(others=>'0');
> > signal dina: std_logic_vector(7 downto 0) :=(others=>'0');
> > signal doutb: std_logic_vector(7 downto 0) :=(others=>'0');
> > signal wea: std_logic :='1';
> > signal wrd: std_logic :='0';
> > signal clk : std_logic :='0';
> > signal reset: std_logic :='1';
> > file from_file:text open READ_MODE is "src.txt";
> > file to_text:text open WRITE_MODE is " text1.txt";
> > begin
> > UUT:checkram port map
> > (
> > addra => addra,
> > addrb => addrb,
> > clka => clk,
> > clkb => clk,
> > dina => dina,
> > doutb => doutb,
> > wea =>wea
> > );
> >
> > clock_process: PROCESS
> > BEGIN
> > clk <= NOT (clk);
> > WAIT FOR 5 ns;
> > END PROCESS clock_process;
> >
> > reset <= '0' after 1 ns;
> >
> > ramRd: process (clk,reset)
> > variable buf_out,buf_in:line;
> > variable num: std_logic_vector(7 downto 0):=(others=>'0');
> > variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
> > begin
> > if reset='1' then
> > iptaddr :=(others=>'0');
> > elsif clk'event and clk='1' then
> > while not (endfile(from_file))loop
> >
> > READLINE(from_file,buf_out);
> > READ(buf_out,num);
> > WRITE (buf_in,doutb);
> > WRITELINE(to_text,buf_in);
> > wea <='1';
> > addra<=iptaddr;
> > dina<= num;
> > iptaddr:=iptaddr+"1";
> > end loop;
> > end if;
> > end process;
> > ---------------------------------------
> > addPro: process (addra,reset)
> > begin
> > if reset='1' then
> > wea<='1';
> > wrd<='0';
> > elsif addra = "111" then
> > wea<='0';
> > wrd <='1';
> > end if;
> > end process;
> > ----------------------------------------
> > output: process(clk,wrd,reset)
> > variable buf_in:line;
> > variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
> > begin
> > if reset='1' then
> > addrb <=(others=>'0');
> >
> > elsif clk'event and clk ='1' then
> > if wrd <= '1' then
> > addrb <= addrb+"001";
> > end if;
> > WRITE (buf_in,doutb);
> > WRITELINE(to_text,buf_in);
> >
> > end if;
> > end process;
> > end serial;
>
> ZHI,
> Below is what I got. The src.txt was referenced to my current
> modelsim directory. When I created the file, that error went away.
> I think the error you got was from the component checkram whose code
> you did not post.
>
> Newman
>
> ---------------------------------------------------------------------
> # //
> # Loading C:\eda\Modeltech_6.2c\win32pe/../std.standard
> # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_1164(body)
> # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_arith(body)
> # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_signed(body)
> # Loading C:\eda\Modeltech_6.2c\win32pe/../std.textio(body)
> # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_textio(body)
> # Loading work.check(serial)
> # ** Error: (vsim-7) Failed to open VHDL file "src.txt" in rb mode.
> # No such file or directory. (errno = ENOENT)
> # Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
> vhdl_tb/fileio.vhd
> # ** Warning: (vsim-3473) Component instance "uut : checkram" is not
> bound.
> # Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
> vhdl_tb/fileio.vhd
Article: 118637Weng, If you need spice models for devices, contact your local semiconductor fabrication house (Chartered, UMC, TSMC, etc..) and request the models for the technology node you are interested in. Choices are typically: low power, or high performance (high Vt, low Vt); 130nm, 90nm (the min gate length), and so on. Generally speaking, these models (which are used by IC designers) are kept under very strict non-disclosure for new technology nodes. Depending on how advanced the models are, BSIM 4, or BSIM 4.5 spice models are the "best" right now, and many are good to use in RF analog circuits, and have proximity effects, NBTI, and other real world behaviors modeled, too. Austin Weng Tianxiang wrote: > Hi, > Please help. > > Where can I find the pass transistor's working curve under 1.2V that > is widely used in IC design preferebly in any articles, instead of in > books? > > Thank you. > > Weng >Article: 118638
Hi Antti, Regarding your specific concerns on the Spartan-3A Starter Kit, there is a known issue where the board assembler failed to set the jumpers correctly. On the Spartan-3A Starter Kit product page, under the documentation banner, there is a "Product Notification" addressing this issue. You can view it directly at http://www.xilinx.com/bvdocs/ipcenter/customer_notification/S3AKit_ProdNotify.pdf Hope that helps, Eric "Antti" <Antti.Lukats@xilant.com> wrote in message news:1177756760.643183.186850@h2g2000hsg.googlegroups.com... > Hi > > I do have have plenty of Xilinx development hardware. I did thinkt hat > for sure enough that i can pick up some board for almost any task. > > Now I just wanted to check out the Xilinx standard webserver demo, > should be easy i did think. Ok first I picked up Memec/Avnet Spartan3 > Microblaze Board. This i have used before, and it used to work. But > the Avnet reference design is made for EDK 8.1, after update to EDK > 8.2 the DDR memory did not work anymore. > > Oh, well this is not so recent board, they have not updated the design > to pass memory test with EDK 8.2, so what lets take some more recent > development board. Then all should work? > > So I startup the Spartan-3A Board.. goto Xilinx website to download > the EDK reference designs. > > I look > and I look > I and I get upset > more and more... > > There are NO REFERENCE designs for the Spartan-3A board!!!! > Except some picoblaze thingies that are currently of zero interest for > me. > > So I am still short of development boards? > Which one should I try next? Memec VP20 board? > Some Xilinx or Digilent board? > > I think Digilent S3E board would have working reference design, but > this board I dont have. > > Disappointed really. > Not to mention that the S3A board was supposed to be fully preloaded > with demos, but all I see is led chaser. > And when I plug the USB cable WinXP asks me to insert Xilinx > installation disk, what isnt included in the package. > > Xilinx platform cable drivers are all installed so it should all work > without "installation disk", but now it does not. > > Antti > Who really doesnt want to troubleshoot "small things that Xilinx and > related vendors just forget..." > > Sure I will now try to make the EDK design for S3A board myself, but > should the DDR2 IP core not work out of the box on the S3A board, then > I will be way more ..... > > I have DDR2 experience with Xilinx FPGA's... should it not want to > work on S3A, I really dont want to seek down the issues. If Digilent > is offering a low cost board with DDR2 memory, then there should be > also at least ONE working design demonstrating the EDK DDR2 IP core > use with S3A >Article: 118639
On May 1, 4:39 pm, austin <aus...@xilinx.com> wrote: > John, > > We generally try to discourage cascading, as the jitter only increases. > > That said, we do expressly prohibit a cascade of the CLKFX output to the > input of another DCM (not supported). > > So, we do support the DLL outputs, to the next DCM input type of cascade. > > In V5, with the PLL, we can now do whatever cascading you want, as long > as there is a PLL between the DCMs (any output to PLL, PLL to input of > next DCM). > > Since customers have such a hard time characterizing their jitter, it is > simpler to generally recommend against cascading. > > It is also true that a single DCM can provide a great deal of > functionality, and all of its outputs can be used (potentially). > > Often a cascade DCM design can be done by two DCMs in parallel. > > Like a PLL, the DCM only fails one way: it fails to lock, or loses > lock. That said, the causes are those which I have already detailed: > too much jitter, input frequency changing while trying to lock, > frequency changing after lock, missing pulses. > > Austin Hi, aside from that, I have some good news, as I finally got my cascade running. I inserted another counter after config done to hold the first DCM in reset for a bit longer period and this did the trick. So now I get exactly the frequencies I want to get without any problems. I still don't quite understand why it behaved so much different than in the last design, but oh well, at least it works ;-) Many thanks to everyone who helped with ideas and suggestions! Cheers, MichaelArticle: 118640
Andy <jonesandy@comcast.net> writes: > Unless you are prototyping an ASIC (and want portability of the code > to ASIC tools), I would not recommend Synopsys for FPGA synthesis. Which tool are you talking about? DC, FPGA Compiler, FPGA Compiler II, or DC-FPGA? The latest Synopsys tool in the FPGA-camp was DC-FPGA, but they terminated the product long time ago. A bit pity I think because it was great to have an ASIC flow acompatible FPGA synthesis tool. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 118641
I am working on a little project using the 8.203i tools. P&R is taking quite a long time now. Was in the middle of a build and realized I had forgot something. Selected STOP in the Implement menu and did the immediate kill thing. Waited about 15 seconds and it was still cranking along, so I brought up task manager and killed the whole program (figured it would be faster). BIG MISTAKE!!! I relaunch ISE and the project is now corrupt. No problem, I reload my backup. Rerun ISE and the project is still corrupt. I stop every task having to do with ISE and try again, still corrupt. I reboot the PC and try again, still corrupt. I erase the entire directory and copy an much older version into the same area, still corrupt. Try a different project. Works fine. It appears that ISE is trying to help me out in some way be remembering something about this project that is stored in some area that I have no idea about. To get around this, I had to re-create the entire project file in the same directory. Then I copied my last project over the top of it. This solved it. I guess the rule is, never kill ISE to save time. If anyone knows about this cache feature and how to flush it, I would be interested in hearing about it. ThanksArticle: 118642
> Hi, > > aside from that, I have some good news, as I finally got my cascade > running. I inserted another counter after config done to hold the > first DCM in reset for a bit longer period and this did the trick. So > now I get exactly the frequencies I want to get without any problems. > I still don't quite understand why it behaved so much different than > in the last design, but oh well, at least it works ;-) > > Many thanks to everyone who helped with ideas and suggestions! > > Cheers, > Michael > How long did you have to wait? (clock cycles and frequency, or time) What is being used in first DCM (phase shift takes longer to lock)? Was this in V2, V2P, S3, S3E, V4 or V5? If V4, is the "auto-cal" DCM enabled (the NBTI fix)? AustinArticle: 118643
Whew!! Close call... PepiArticle: 118644
On May 1, 8:53 pm, austin <aus...@xilinx.com> wrote: > > Hi, > > > aside from that, I have some good news, as I finally got my cascade > > running. I inserted another counter after config done to hold the > > first DCM in reset for a bit longer period and this did the trick. So > > now I get exactly the frequencies I want to get without any problems. > > I still don't quite understand why it behaved so much different than > > in the last design, but oh well, at least it works ;-) > > > Many thanks to everyone who helped with ideas and suggestions! > > > Cheers, > > Michael > > How long did you have to wait? (clock cycles and frequency, or time) > > What is being used in first DCM (phase shift takes longer to lock)? > > Was this in V2, V2P, S3, S3E, V4 or V5? > > If V4, is the "auto-cal" DCM enabled (the NBTI fix)? > > Austin Everything concerns a XCV4FX60 ES. Actually, I don't think that the first DCM needs longer to lock (I only use CLK2X, no phase shift), there just seem to be some kind of synchronization problems between setting the lock out and having an actually high-quality output clk when the DCM comes right out of the config phase. Therefore the first one gets his lock later on, while the second one gets released from the reset state too soon and can't achieve lock anymore. At least that's what it looks like to me. In the current system the auto-cal is disabled as I first wanted to see if that would influence things (it didn't). I will try it with the reset included and the auto-cal enabled and report back to you if it still works. Cheers, MichaelArticle: 118645
Hi, My question is straight'n'simple: what's the *most efficient* way of reading a 64-bit value from a slave PLB peripheral in software? Is there any *weird* behaviour I should be made aware of when I read 32- bit value instead? In principle, PLB should be able to handle 64-bit transaction but not PPC software of course. Is there anyway to map this transaction to a consecutive pair of PPC software registers? Thanks in advance, Regards, -MannyArticle: 118646
Yeah, I guess it is the problem of the IP core RAM. I wander if the ip core RAM can be simulated in ModelSim. When I removed the IP core RAM part, and just using textio read and write, that will be no problem. cpope wrote: > "Newman" <newman5382@yahoo.com> wrote in message > news:1178032912.349257.47850@e65g2000hsc.googlegroups.com... > > On May 1, 10:50 am, "cpope" <cep...@nc.rr.com> wrote: > > > I have a new board where I switched from the xcf08p to the xcf32p serial > > > prom devices. The 32p programs fine and when I cycle power the current > jumps > > > up and my test led lights which should mean that the fpga is configured. > > > However, the PPC in the v4fx12 device is dead or not running. Running > XMD > > > returns all zeros for the processor ID and I get no output from my > > > bootloader code. > > > > > > Downloading the fpga manually works fine. > > > > > > One other difference is that I'm using the revision select lines on the > 32p > > > where I didn't on the 08p but the lines are both set correctly and it > does > > > appear that the fpga loads but then freezes. Any ideas what might cause > > > this? > > > > > > Thanks, > > > Clark > > > > > > Clark, > > Don't understand the relationship to this thread but I found > > something on the Xilinx website that may or may not be related to what > > you are seeing. I did not read the errata. > > > > -------------------------------------------------------------------------- > --------------------- > > XCF08P, XCF16P, & XCF32P Errata and Deviations from the Data Sheet > > Intermittent Power Ramp Fa > > > > > > A test escape has been discovered with the devices named above which > > for some applications results in device failure during "Power on Reset > > Activation." Devices that have a VCCint ramp during "Power on Reset > > Activation" that takes longer than 1ms to reach 1.6V may see failures. > > > > Associated Products: Configuration PROMs > > -------------------------------------------------------------------------- > ---------------------- > > > > Newman > > > > Thanks, but I get the same result whether I run from Impact or whether I > power cycle the board. When I'm using Impact the board power supplies should > be well settled so I don't think it's anything to do with transients at > power up. -ClarkArticle: 118647
Michael, Thanks. I am trying to keep track of DCM issues, so that we can either make the documentation better, or the hardware better (in future chips). AustinArticle: 118648
On May 1, 2:08 pm, ZHI <threeinchn...@gmail.com> wrote:
> The checkram is generated by the IP core generator. Actually it has no
> problem in the inital simulation. When I run by step the simulation,
> It got the error information.
>
>
>
> Newman wrote:
> > On May 1, 8:41 am, ZHI <threeinchn...@gmail.com> wrote:
> > > Hi,
> > > I want to learn using textio. Here I use Read data from scr.txt to IP
> > > core RAM and Write them to the text1.txt. I wrote the codes here but
> > > it doesn't work. Any suggestions about this is very appreciated.
> > > One more thing, when i use Modelsim to Run by step. It alway gives the
> > > error information and cannot finish the simulation. I don't what it
> > > means.
> > > ******************************************************
> > > Trace back: Error opening C:/Documents and Settings/zq500/Local
> > > Settings/Temp/xil_1700_6
> > > # while executing
> > > # "error $winName"
> > > # (procedure "view" line 82)
> > > # invoked from within
> > > # "view source"
> > > # (procedure "vsimcmd::viewProcessSource" line 2)
> > > # invoked from within
> > > # "vsimcmd::viewProcessSource /check/uut/u0/select_outputb"
> > > # ("after" script)
> > > # 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
> > > Settings/Temp/xil_1700_6}
> > > # 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
> > > Settings/Temp/xil_1700_6}
> > > **************************************************************************
> > > library ieee;
> > > use ieee.std_logic_1164.all;
> > > use ieee.std_logic_arith.all;
> > > use ieee.std_logic_signed.all;
> > > use ieee.std_logic_textio.all;
> > > use std.textio.all;
>
> > > entity check is
> > > end check;
>
> > > architecture serial of check is
>
> > > component checkram
> > > port (
> > > addra: IN std_logic_VECTOR(2 downto 0);
> > > addrb: IN std_logic_VECTOR(2 downto 0);
> > > clka: IN std_logic;
> > > clkb: IN std_logic;
> > > dina: IN std_logic_VECTOR(7 downto 0);
> > > doutb: OUT std_logic_VECTOR(7 downto 0);
> > > wea: IN std_logic);
> > > end component;
>
> > > signal addra: std_logic_vector(2 downto 0):=(others=>'0');
> > > signal addrb: std_logic_vector(2 downto 0):=(others=>'0');
> > > signal dina: std_logic_vector(7 downto 0) :=(others=>'0');
> > > signal doutb: std_logic_vector(7 downto 0) :=(others=>'0');
> > > signal wea: std_logic :='1';
> > > signal wrd: std_logic :='0';
> > > signal clk : std_logic :='0';
> > > signal reset: std_logic :='1';
> > > file from_file:text open READ_MODE is "src.txt";
> > > file to_text:text open WRITE_MODE is " text1.txt";
> > > begin
> > > UUT:checkram port map
> > > (
> > > addra => addra,
> > > addrb => addrb,
> > > clka => clk,
> > > clkb => clk,
> > > dina => dina,
> > > doutb => doutb,
> > > wea =>wea
> > > );
>
> > > clock_process: PROCESS
> > > BEGIN
> > > clk <= NOT (clk);
> > > WAIT FOR 5 ns;
> > > END PROCESS clock_process;
>
> > > reset <= '0' after 1 ns;
>
> > > ramRd: process (clk,reset)
> > > variable buf_out,buf_in:line;
> > > variable num: std_logic_vector(7 downto 0):=(others=>'0');
> > > variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
> > > begin
> > > if reset='1' then
> > > iptaddr :=(others=>'0');
> > > elsif clk'event and clk='1' then
> > > while not (endfile(from_file))loop
>
> > > READLINE(from_file,buf_out);
> > > READ(buf_out,num);
> > > WRITE (buf_in,doutb);
> > > WRITELINE(to_text,buf_in);
> > > wea <='1';
> > > addra<=iptaddr;
> > > dina<= num;
> > > iptaddr:=iptaddr+"1";
> > > end loop;
> > > end if;
> > > end process;
> > > ---------------------------------------
> > > addPro: process (addra,reset)
> > > begin
> > > if reset='1' then
> > > wea<='1';
> > > wrd<='0';
> > > elsif addra = "111" then
> > > wea<='0';
> > > wrd <='1';
> > > end if;
> > > end process;
> > > ----------------------------------------
> > > output: process(clk,wrd,reset)
> > > variable buf_in:line;
> > > variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
> > > begin
> > > if reset='1' then
> > > addrb <=(others=>'0');
>
> > > elsif clk'event and clk ='1' then
> > > if wrd <= '1' then
> > > addrb <= addrb+"001";
> > > end if;
> > > WRITE (buf_in,doutb);
> > > WRITELINE(to_text,buf_in);
>
> > > end if;
> > > end process;
> > > end serial;
>
> > ZHI,
> > Below is what I got. The src.txt was referenced to my current
> > modelsim directory. When I created the file, that error went away.
> > I think the error you got was from the component checkram whose code
> > you did not post.
>
> > Newman
>
> > ---------------------------------------------------------------------
> > # //
> > # Loading C:\eda\Modeltech_6.2c\win32pe/../std.standard
> > # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_1164(body)
> > # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_arith(body)
> > # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_signed(body)
> > # Loading C:\eda\Modeltech_6.2c\win32pe/../std.textio(body)
> > # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_textio(body)
> > # Loading work.check(serial)
> > # ** Error: (vsim-7) Failed to open VHDL file "src.txt" in rb mode.
> > # No such file or directory. (errno = ENOENT)
> > # Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
> > vhdl_tb/fileio.vhd
> > # ** Warning: (vsim-3473) Component instance "uut : checkram" is not
> > bound.
> > # Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
> > vhdl_tb/fileio.vhd- Hide quoted text -
>
> - Show quoted text -
--------------------------------------------------------------------------------------------------
# invoked from within
# "vsimcmd::viewProcessSource /check/uut/u0/
select_outputb" <<===
# ("after" script)
# 2: ::tkerror {Error opening C:/Documents and Settings/zq500/
Local
Settings/Temp/xil_1700_6}
I believe the <<=== points to something in the checkram uut
component. My initial thought was that embedded spaces in the path
might be causing some problem (Documents and Settings)... some tools
have problems with this. Can't remember if Modelsim does.
Since I cannot duplicate the problem, I am at a loss to help you.
Newman
Article: 118649"Default User" <defaultuserbr@yahoo.com> schreef in bericht news:59nb7eF2i6v9uU1@mid.individual.net... > John Popelish wrote: > >> This is exactly the state diagram I drew before answering >> the post. Nice work. > > This has nothing to do with comp.lang.c. Please remove that newsgroup > from your distribution. > > > > > Brian FAIK the OP was asking about the design of a finite state machine. Nothing said about the implementation. C is a perfect language to build finite state machines. The solution can for instance be implemented in a microcontroller using C, most likely as a part of a larger design. (Although I'd prefer assembler for small programs.) It can be implemented the same way in programmable hardware using VHDL or Verilog. As a matter of fact, it is so simple you can even implement it using old fashioned devices with flipflops and gates. I can build all this possibilities plus some I did not mention. Still complaints? petrus bitbyter
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z