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Here is what you can do: Without any DCM feedback, there is no defined phase relationship between your 30 and 240 MHz. If, however, you buffer the CLK0 output and feed it back to the DCM input, the rising edge of every eighth 240 MHz cycle will be aligned with the rising of your 30 MHz input at the point where it meets the DCM. Any further synchronization is up to your creativity. Peter Alfke On May 10, 12:00 pm, fastgreen2...@yahoo.com wrote: > Peter - thanks again. > > So, I can use 30mhz CLKIN to create CLKFX @240mhz (M=8,D=1)... > but can I use CLKFB to remove the insertion delay here? All documents > I looked at talk about > CLKIN out of the range _and_ using only FX outputs (with no CLKFB > hooked up). I can see > why that's the case. > > If that's the case, how do I receive the 240Mhz data that's > synchronous to the 30Mhz input clock > - the delay from the pad thru ibufg, dcm, bufg is not quantified, I > don't believe. I wouldn't know how > to align the clock to the data. (In the lab, I can, but not over > temp, volt, etc...) I mentioned receiving > the data in the original post, maybe it got missed.Article: 119076
I have been tetsing with Xilinx V5 LXT board for transceiver evaluation. Currently I am focusing on the transmitter to determine channel alignment. This particular board has 16 transceivers. We programmed them in a generic operational mode with 8b/10b disabled and data rate of 3.125Gbps. For this one board we are seeing that 13 channels are aligned within 60 ps while the 14th channel is off by about 200 ps. It will be great if all channels were with 60 ps. We also did some jitter measurements of data with respect to 1.6GHz clock generated by one of the Xilinx Transceievrs. Preliminary results show that the effective eye opening from the transceiver is .7609 UI. These channels have 4” of trace to the SMA connector. So if we have a long trace to the receiver then the eye opening will be slightly lower then this. I have couple of question for the transmitter portion. (1) Do you think that we should not have one of the 14 channels misaligned by 200ps? (2) Is there any thing we can do to get better transmit eye opening then 0.7609 UI? Our receiver has requirement of 0.75 UI. My concern is that when we get the V5 FXT device then this number will get worst at higher data rates (> 3.2 Gbps) On the receiver side, I have couple of questions: (1) Can the CDR lock on the reference clock? (2) If yes to question 1, then we are thinking that we can provide the divided reference clock from the forwarded clock. For 3.2 Gbps operation the forwarded clock will be 1.6 GHz. We can divide this clock down to the valid reference clock frequency that the CDR can take. Can this work? Our purpose is to use this in lab environment and not for very long duration. (3) Is there any way we can program the phase interpolator for each receiver? This can be used for clock alignment purposes during training. If so it will be good to get some details.Article: 119077
Yeh Kolja, I will definitely start with something simple first.
Since I haven't begin to understand the concept of coefficient and
upsampling.
Ah thanks Paul, for taking out the time to explain some concept. (trying to
digest all of them though >_<)
Well, interpolation is basically creating more datapoints between the
original fixed datapoints right?
Linear interpolation ar. I hope i can progress not from linear interpolation
as it seems that the results i will be getting should be very poor.
But I will have to see how far i will be able to go from linear
interpolation. hope to be able to scale some video input from a vcd players.
Though i will have to worry about the I/O of the boards and other hardware
related issues.
Will check out the DSP books that you recommended too! :)
"Paul" <pauljbennett@gmail.com> wrote in message
news:1178285538.481886.251680@l77g2000hsb.googlegroups.com...
> OK... think time domain signal... say your signal x = [1 10 5 3] and
> you want to upsample this to twice the sampling frequency.... if you
> did a simple linear interpolation you'd get x_upsampled = [1 5.5 10
> 7.5 5 4 3 ?] that last datapoint{?} is kinda arbitrary, presumably
> you'd just set it to 3. However, signals are defined as a sum of
> sinusoids, and generally they fit that model fairly well - when you
> have something that doesn't, it takes more sinusoids to fit it.. thats
> the general theory behind a fourier transform, right? So linear
> interpolation isn't really you're best solution. You can
> mathematically prove that if you had an infinitely long signal, and an
> infinitely perfect low pass filter, the "perfect" upsampling is done
> by inserting zeros x_zero = [1 0 10 0 5 0 3 0], and low pass
> fitlering it. Obviously, neither the infinite sequence or the perfect
> LPF is realistic. If you do the math (or plug it into matlab), the
> FFT of x (shfited to place zero frequency in the center), X=[-7 -4+7j
> 19 -4-7j] If you take the FFT of x_zero, X_ZERO = [19 -4-7j -7
> -4+7j 19 -4-7j -7 -4+7j] Note, this is simply X repeated.
> So how do you get back your correct frequency spectrum? An ideal LPF
> returns X_UPSAMPLE=[0 0 -7 -4+7j 19 -4-7j 0 0]. Now note
> this... if you use matlab and take the inverse FFT of this (the
> shifted version of this actually) you get [1.0000 5.8107
> 10.0000 8.6391 5.0000 3.6893 3.0000 0.8609]
> Actually... you get this divided by 2 (you need to multiply by your
> upsampling facor, that comes out in the math) with a risidual
> imaginary part due to the fact that it's an even length sequence, so
> you just look at the real part. Point being however, note that the
> interpolated values are NOT what you get using straight linear
> interpolation. this is because this method takes into account the
> curvature of the rest of the sequence and stuff.
>
> That being said.... for this project, I would imagine that simple
> linear interpolation is plenty adequate! A 2 dimensional version of
> this example above would be quite tricky and take a lot of processing
> power. But read the chapter in your DSP book on upsampling - it will
> cover all this :-) Actually, not positive, but the stock, every
> college in the world uses, oppenheim & shaeffer signals & systems book
> MIGHT even go into it in one of the later chapters.
>
>
>> > How accurate do your interpolations need to be? Think basic 1-
>> > dimensional DSP.. how do you upsample a signal? insert zeros between
>> > samples and LPF, right? Or do the same thing in the F-domain by zero
>> > padding the ends of the FFT and inverse-FFT'ing. Either of these
>> > methods in 2 dimensions is going to be a lot of computation and a lot
>> > of taking stuff in and out of memory in different orders. DDR
>> > memories like you to take stuff out in the same order you put them
>> > in... they slow down big time when you try to jump around.. So if you
>> > do this, you will need to some up with some clever methods of read out
>> > pieces from DDR in the incorrect order, and then re-reading from a
>> > local, smaller, block ram in the order you actually want. This will
>> > take careful planning and a lot of simulation, even an experienced
>> > designer would have a tricky time with this and probably get it wrong
>> > in simulation the first shot.
>>
>> Woah, ok I'm totally lost in here. But no problem, I will take note of
>> these
>> points and consult my profs or someone
>
Article: 119078I agree, im really puzzled by this. As you indicated i have followed the guidelines when putting these constraints in the ucf. I have tried with and without " with no change in the result. Additional information: When i run without these constraint i get no errors and i get the FRAME_ECC instanciated correctly. (Verified in FPGA editor.) Also i use only the CRCERROR output from the primitive when i infer it in the VHDL code.Article: 119079
Hi all, I'm implementing a design which uses ROMs. The design was synthesized under precision. I used the .edf file for implementation under ise 9.1.03i. Unfortunately, I'm getting this error: ERROR:NgdBuild:604 - logical block 'rom_in/ix58499z9781' with type 'FALSE' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'FALSE' is not supported in target 'virtex4'. What to do in this case ? cheersArticle: 119080
Ben, Perhaps Xilinx would do itself (and users) a favor when they would dump their own UI's like EDK and ISE and start using Eclipse (http://www.eclipse.org/) instead. - Less chance to introduce UI bugs and more resources to concentrate on core business. - Uniform look and feel across Xilinx tools and (some) other vendors. - increase the chances for users to integrate it with other tooling like version management (like ClearCase) and/or software tooling (like vxWorks). Wim Mosterman (who has a bogus email address because he doesn't like spam) Ben Jones wrote: > "Mike Lundy" <novas0x2a@gmail.com> wrote in message > news:1178640182.911706.234880@e65g2000hsc.googlegroups.com... > >> If most of your man hours are spent doing new device support, who >> is fixing bugs? > > Steve said that the majority of >200 developers' time is spent on coding up > support for new devices and silicon features. He was not suggesting that > they are too busy to fix bugs. > >> Who is testing? No offense intended, but it seems >> like the answer is "not enough people." > > There are never enough people testing software! :) > > The developers test their modules as they develop new code. They test when > they integrate their modules. The software verification group test the > software at many levels. The IP developers do a lot of alpha testing since > we usually need bleeding edge tools for the latest families. The FAEs test > the software. And so on. > > Could we do better? Yes, I think so. Do we just ship it as soon as it > compiles (as seems to be commonly implied around here)? No, we really don't. > > I'm a big fan of open source software and I'd love to see more OSS projects > surrounding FPGA technology. But I'm not quite sure about the feasibility of > what's being suggested in this thread. > > First of all, what exactly is the scope of this "open source ISE" supposed > to be? If it's just a vendor-agnostic IDE for designing FPGAs, then it > sounds like a trivial wrapper around the proprietary synthesis and back-end > tool flows. Most serious FPGA developers already have their own makefiles > and associated infrastructure that eases the portability of their design > from one vendor's device to another's. At which point, slapping a sparkly > GUI on top of it is not a high priority for them. > > Now taking it up a level, an open-source implementation of something like > EDK (~SOPC builder) would be interesting. The idea of FPGA design as the > convenient stitching together of prefab building blocks, either from a > standard library or custom-made for the current project, has a lot of > mileage in it. And it's an ideal way to factor out vendor dependencies. > > An open-source equivalent of the Core Generator (~MegaWizard) could work; > all these things help to hide the low-level implementation details and focus > on the system level. A free and open-source solution for managing libraries > of parameterizable IP would really help people to create portable designs > while still making efficient use of the target architecture. (I'm not > talking about people instantiating shift registers and counters here, but > higher-level processing blocks.) > > But would it make sense to try and do an open source FPGA floor-planning > tool? I don't think so. The level of dependence on the device internals is > prohibitive. For the same reason, mapping, packing, placement and routing > algorithms look destined to remain proprietary, at least for the time being. > OSS versions would lag a vendor-proprietary system significantly because > vendors just won't release early details of their new architectures to the > general public. They need to retain a competitive advantage or they will go > out of business. I cannot see that changing; at least not until there is one > single company's architecture dominating the FPGA landscape (a la Intel in > the late 1990s). > > There are obvious parallels here with the software world and general-purpose > processors, but there are differences too. The EDA back-end is significantly > more complex than (say) the GCC back-end, because the FPGA feature set - as > exposed to the "programmer" - is considerably more complicated too. It's > tempting to argue that because GCC was possible, that an open-source > vendor-independent HDL-to-gates compiler is possible too. But this is proof > by analogy. > > My conclusion is that the only parts of the FPGA toolchain that vendors will > likely be willing to open-source are the bits that the open-source community > would not be interested in anyway. A notable exception is the JTAG > programming stuff, as has been pointed out by several others. I would be > incredibly happy to see a proper, flexible, standard stack for accessing > JTAG devices - and to achieve that, I think an open source effort is pretty > much the *only* approach that will work. > > Cheers, > > -Ben- > >Article: 119081
Hi! I was successful in the past using xc3sprog to program Spartan3 (50, 200) and the associated serial flash. Can anyone say something about xc3sprog and Spartan3E and Spartan3A devices? A quick scan in the devlist.txt shows no E/A device but that does not mean it won't work. I don't have any board with this devices to do the test. To xilinx: The tools for CPLD/FPGA programming should be /user land/ and /open source/. I do not care about fancy stuff like ChipScope, keep that proprietary if you need to. --- Thanks, mmihaiArticle: 119082
"WiMos" <WiMos@philips.com> wrote in message
news:jFV0i.1020$Q66.491@lon04-news-philips...
> Ben,
>
> Perhaps Xilinx would do itself (and users) a favor when they would dump
> their own UI's like EDK and ISE and start using Eclipse
> (http://www.eclipse.org/) instead.
Guess what? The EDK software development environment already uses Eclipse.
:)
Personally I am not a big fan of any sort of IDE/GUIs; I prefer a known good
text editor and a collection of command-line tools. The EDK GUI, though,
adds value above and beyond this by giving you a bus-centric view of your
design's connectivity. Indeed, this sort of high-level module-based design
is about the only reason I would want to use any tool other than a simple
text editor for FPGA design entry...
Cheers,
-Ben-
Article: 119083On May 10, 2:25 pm, jmariano <jmarian...@gmail.com> wrote: > Dear All, > > I'm sure this question was already been posted (and answered) in this > list, but I could > not find a suitable answer for my little knowledge of this matters, > so, with my > apologies, i'm posting it again. > > I'm developing a microblaze system based on the Spartan-3 starter kit > board. I need to > access the on-board SRAM from my C code. I have hooked the SRAM to the > OPB bus using BSB. > The automatically generated memory_test application works just fine. > > I just need the memory to hold data during program execution, e.g, > int's, I d'ont have > any sort of timing requirements. > > My question is: how i'm I suppose to read and write to/from the SRAM? > Just use the > XIo_Out/In(32, 16, 8) library functions or is their a more efficient > way of accessing the > memory? I'm particulary confused by the functions on the XEmc library, > that are related > to the SRAM, but I really d'ont know what they do. > > Tank you all, > > Jos=E9 Mariano As Antti has said, you only have to create a pointer such as int *sdram_pointer=3D(int *)(0x22000000) *sdram_pointer=3D..... sdram_pointer++; .=2E..Article: 119084
Hi all, currently I am investigating a data sorting algorithm on hardware. The algorithm was implemented in VHDL and is currently running on a Xilinx Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect in the target application. Therefore I made an analysis with the Xilinx Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying results. Now I'd like to make an estimation what this circuit would consume on a comparable ASIC 0.13µm CMOS technology (the FPGA is also based on a 0.13µm CMOS technology). The target clock frequency is 180 MHz, activity ratio is 15%. Is there any rule of thumb or calculation rule? Any help is highly appreciated !!!! Regards GeroArticle: 119085
I'm using Ken Chapman's uart_tx in a Spartan3A design.
The HDL compler can't find the module/primitive, so I wonder if I did
everything right here.
What I did was the following:
- Download and unpack xapp223.zip from Xilinx
- Include uart_tx.EDN in my design, no problem
- Instantiate it in my code, copy/paste from Spartan3A demo source
"terminal.v"
- Compile, got error
I know the uart documentation says it's fit for any Virtex or Spartan-
II, but seeing that it works in the Spartan3A demo I should be able to
use it in my code on the same board.
Can you explain what went wrong here?
Thanks,
B=F8rge
Here's my instantiation:
uart_tx uart_transmitter (
.data_in(outdata_uart),
.write_buffer(write_to_uart),
.reset_buffer(reset_local),
.en_16_x_baud(en_16_x_baud),
.serial_out(RS232_DCE_TXD),
.buffer_full(uart_buffer_full),
.buffer_half_full(),
.clk(clk_100)
);
Here's my comple error message:
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
* Design Hierarchy
Analysis *
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
ERROR:HDLCompilers:87 - "sources/implementation.v" line 346 Could not
find module/primitive 'uart_tx'
-->
Article: 119086On 2007-05-11, Ben Jones <ben.jones@xilinx.com> wrote: > Personally I am not a big fan of any sort of IDE/GUIs; I prefer a known good > text editor and a collection of command-line tools. The EDK GUI, though, > adds value above and beyond this by giving you a bus-centric view of your > design's connectivity. Indeed, this sort of high-level module-based design > is about the only reason I would want to use any tool other than a simple > text editor for FPGA design entry... This is certainly one feature that seems to make the EDK rather nice. Once SystemVerilog (SV) support is more widespread some of that advantage might disappear since the SV interface construct makes it significantly easier to connect modules to a bus-centric design. (I guess you don't like Verilog but perhaps VHDL 2006 has something similar? I don't remember if I've read anything about such a feature.) In my imaginary "perfect" development environment, my editor would be able to extract bus based information and show it graphically but the basic information about bus connectivity should only be located in the source code. This way my design would be easier to port between different design environments. /AndreasArticle: 119087
I definately was not saying that linear interpolation results will be
"very" poor... in fact... I'd bet some commercial scalers do it that
way.... At any rate... I'd be cautious of shooting for the stars -
you're better off with an obtainable project... Here's some
considerations...
640x480 = 307200points... which, if you're talking about RGB input,
means 307200 points of Red, Green & Blue each.... 307200points x
60fps = 18.4MSample/s per color... lets assume you're processing the
three colors independently... I know the Spartan3 development boards
have 50MHz clocks on them. I probably wouldn't try to push a Spartan
design much past 100MHz unless it was a VERY empty part (the higher
the utilization the more difficult it is to place and route it at a
higher speed). Now, assuming 100MHz, processing 3 colors
independently, that basically means you can do 5 "operations" in a
sample time... if you want to double your output rate (i.e. - scale up
to 1280x960) that may be as low as 2.5 operations, depending what the
operation is and if it needs to be done at the higher or lower rate.
In short what that gets down to is that anymore operations than that
must be done in different "blocks" of the design (i.e. they use more
resources). And that is going to quickly run you up against the limit
in terms of the number of multipliers in the spartan probably.
Now those are all TOTALLY ballpark, off the cuff numbers. My gut
instinct would be that linear interpolation will be NO problem at all
in the spartan at 100MHz, I'd bet you could even do it at those
resolutions at 50MHz. But my other gut instinct there is also that
any real significant amount of processing beyond linear interpolation
is going to get really tight, really quick. I think as a student
you're better off not trying to attempt a really tightly packed
design. The reason I say that is that to get a really tight design to
place and route correctly and meet timing you need to really know all
the ins and outs of the software tools (the Xilinx software). You
have to set all sorts of settings, possibly go in an manually place
critical parts of the design, etc... etc.... And that's REALLY not
what you want to be spending your time on as a student. Your purpose
is to learn about the logical part of FPGA design, and that's going to
be tricky enough on its own - I really wouldnt recommend working
yourself into that tight a position... You're really going to have a
lot on your plate with this design as it is.
At any rate.. that's my advice.. anyone else is welcome to
disagree...
On May 11, 1:14 am, "Ken Soon" <c...@xilinx.com> wrote:
> Yeh Kolja, I will definitely start with something simple first.
> Since I haven't begin to understand the concept of coefficient and
> upsampling.
>
> Ah thanks Paul, for taking out the time to explain some concept. (trying to
> digest all of them though >_<)
> Well, interpolation is basically creating more datapoints between the
> original fixed datapoints right?
> Linear interpolation ar. I hope i can progress not from linear interpolation
> as it seems that the results i will be getting should be very poor.
> But I will have to see how far i will be able to go from linear
> interpolation. hope to be able to scale some video input from a vcd players.
> Though i will have to worry about the I/O of the boards and other hardware
> related issues.
> Will check out the DSP books that you recommended too! :)
>
> "Paul" <pauljbenn...@gmail.com> wrote in message
>
> news:1178285538.481886.251680@l77g2000hsb.googlegroups.com...
>
>
>
> > OK... think time domain signal... say your signal x = [1 10 5 3] and
> > you want to upsample this to twice the sampling frequency.... if you
> > did a simple linear interpolation you'd get x_upsampled = [1 5.5 10
> > 7.5 5 4 3 ?] that last datapoint{?} is kinda arbitrary, presumably
> > you'd just set it to 3. However, signals are defined as a sum of
> > sinusoids, and generally they fit that model fairly well - when you
> > have something that doesn't, it takes more sinusoids to fit it.. thats
> > the general theory behind a fourier transform, right? So linear
> > interpolation isn't really you're best solution. You can
> > mathematically prove that if you had an infinitely long signal, and an
> > infinitely perfect low pass filter, the "perfect" upsampling is done
> > by inserting zeros x_zero = [1 0 10 0 5 0 3 0], and low pass
> > fitlering it. Obviously, neither the infinite sequence or the perfect
> > LPF is realistic. If you do the math (or plug it into matlab), the
> > FFT of x (shfited to place zero frequency in the center), X=[-7 -4+7j
> > 19 -4-7j] If you take the FFT of x_zero, X_ZERO = [19 -4-7j -7
> > -4+7j 19 -4-7j -7 -4+7j] Note, this is simply X repeated.
> > So how do you get back your correct frequency spectrum? An ideal LPF
> > returns X_UPSAMPLE=[0 0 -7 -4+7j 19 -4-7j 0 0]. Now note
> > this... if you use matlab and take the inverse FFT of this (the
> > shifted version of this actually) you get [1.0000 5.8107
> > 10.0000 8.6391 5.0000 3.6893 3.0000 0.8609]
> > Actually... you get this divided by 2 (you need to multiply by your
> > upsampling facor, that comes out in the math) with a risidual
> > imaginary part due to the fact that it's an even length sequence, so
> > you just look at the real part. Point being however, note that the
> > interpolated values are NOT what you get using straight linear
> > interpolation. this is because this method takes into account the
> > curvature of the rest of the sequence and stuff.
>
> > That being said.... for this project, I would imagine that simple
> > linear interpolation is plenty adequate! A 2 dimensional version of
> > this example above would be quite tricky and take a lot of processing
> > power. But read the chapter in your DSP book on upsampling - it will
> > cover all this :-) Actually, not positive, but the stock, every
> > college in the world uses, oppenheim & shaeffer signals & systems book
> > MIGHT even go into it in one of the later chapters.
>
> >> > How accurate do your interpolations need to be? Think basic 1-
> >> > dimensional DSP.. how do you upsample a signal? insert zeros between
> >> > samples and LPF, right? Or do the same thing in the F-domain by zero
> >> > padding the ends of the FFT and inverse-FFT'ing. Either of these
> >> > methods in 2 dimensions is going to be a lot of computation and a lot
> >> > of taking stuff in and out of memory in different orders. DDR
> >> > memories like you to take stuff out in the same order you put them
> >> > in... they slow down big time when you try to jump around.. So if you
> >> > do this, you will need to some up with some clever methods of read out
> >> > pieces from DDR in the incorrect order, and then re-reading from a
> >> > local, smaller, block ram in the order you actually want. This will
> >> > take careful planning and a lot of simulation, even an experienced
> >> > designer would have a tricky time with this and probably get it wrong
> >> > in simulation the first shot.
>
> >> Woah, ok I'm totally lost in here. But no problem, I will take note of
> >> these
> >> points and consult my profs or someone- Hide quoted text -
>
> - Show quoted text -
Article: 119088In simulation, the compiler has the OPTION to unroll a loop if it thinks it would be more efficient to execute that way. But it does not have to (it may be too large, or the loop may not be statically bound). Therefore the loop index is absolutely not static. Synthesis tools always unroll loops (that's why they have to be statically bound for synthesis), and the index is then "treated as if static". In other words, the value of the index for each iteration is known at synthesis time and need not be calculated in hardware. Ditto for any otherwise static expressions of the index (i.e. "i+1" is treated as static, etc.). But from the language compilation/LRM point of view, it is not static. AndyArticle: 119089
On May 10, 12:43 am, fastgreen2...@yahoo.com wrote: > I'm restricted to 30Mhz LVDS clock input. From this, I need to > generate 240Mhz to be used internally. Restriction comes an ASIC that > I'm interfacing to. What options do I have here? > > Based on what I see in ds302 by Xilinx, I haven't found a clean (or, > any) solution. Minimum clock speed I need is 32Mhz for DCM. If the > min speed weren't an issue, I could cascade two DCMs - 4x and 2x - to > get 8x. (I know, cascading is not ideal due to jitter). > > Am I stuck? The 30Mhz clock is actually for data coming in at 240Mhz > rate. > > Is there any way out of this? In addition to Peter comments, you might want to read XAPP265 (High- Speed Data Serialization and Deserialization, 840 Mb/s LVDS). PatrickArticle: 119090
Great, tank you both very much. Regards, jose marianoArticle: 119091
On May 3, 7:41 pm, jhal...@TheWorld.com (Joseph H Allen) wrote:
> In article <1178200419.714442.227...@l77g2000hsb.googlegroups.com>,
>
> romi <webe...@gmail.com> wrote:
> >On May 2, 9:11 am, jhal...@TheWorld.com (Joseph H Allen) wrote:
> >> // Concise priority arbiter
> >> input [26:0] req; // Bit zero is highest priority
> >> wire [26:0] gnt = req & -req; // Isolate least significant set bit
> >> reg [26:0] prev; // Previous winner (saved from last cycle)
> >> wire [26:0] req1 = req & ~((prev - 1) | prev); // Mask off previous winners
> >> wire [26:0] gnt1 = req1 & -req1; // Select new winner
> >> wire [26:0] winner = |gnt1 ? gnt1 : gnt; // Start from bit zero if none
> >> // Save previous winner
> >> always @(posedge clk) if (winner) prev <= winner;
> >Since gnt1 implies that there was a req1, wouldn't it be better
> >(faster) to use req1 in the winner selection?
> >wire [26:0] winner = |req1 ? gnt1 : gnt; // Start from bit zero if
> >none
>
> Yes. Cool. :-)
>
> Here are some other variations:
>
> If the carry chain is really fast, get rid of the mux:
>
> wire [53:0] req1 = { req, req & ~((prev - 1) | prev) };
> wire [53:0] gnt1 = req1 & -req1;
> wire [26:0] winner = gnt1[53:27] | gnt1[26:0];
>
> Or use wrap-around carry, if you don't mind the combinatorial loop:
>
> // Rotate previous winner one bit to the left. If no previous winner,
> // pretend it was prev[26].
> wire [26:0] prev1 = |prev ? { prev[25:0], prev[26] } : 27'd1;
>
> // Wrap-around two's complement where the add 1 is just to the left of the
> // previous winner instead of at bit 0.
> wire [27:0] tmp = { 1'b0, ~req } + ({ 1'b0, prev1 } | { 27'b0, tmp[27] });
>
> wire winner = req & tmp[26:0];
>
> This is probably the fastest, but you need a synthesis tool which allows
> combinatorial loops.
>
> --
> /* jhal...@world.std.com AB1GO */ /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Hello,
> This is probably the fastest, but you need a synthesis tool which allows
> combinatorial loops.
Since I'm doing a real job, I need to perform STA (Static Timing
Analysis) for my design. Therefore, combinational loops are not
allowed. Now, I'm investigating some ways and follow some instructions
from someone. But it seems that I can not make thing better. However,
my project manager told me that he would probably allow me to use a
different technology library to synthesize my design if the timing was
not met finally.
By the way, thank you so much for all your helps so far.
Quang Anh
Article: 119092Hi. Debugging a board with V4FX12 I noticed a strange behaviour of the PPC ICU. It seems that the ICU has an undocumented data transfer timeout. According to the docs, the PLB arbiter implements a timeout for the address transfer. My slave acknowledges a read address immediately, but then sits for a long time (up to 80 cycles) before it actually starts delivering data. On my board, I observe PPC crashes. Almost immediately before a crash, the PPC ICU seems to give up on such a lengthy data transfer stage. After about 70 cycles or so, it suddenly issues a new read request, for the address that follows the pending read. As if it had given up and dropped the previous one. Shortly after, the program crashes. I couldn't confirm, but I suppose that "to give up" also means "mark the instruction cacheline as valid, although it isn't". There's another symtom as well. Since my slave and the arbiter do not have the timeout implemented, the data is eventually delivered. On the 3rd of 4 cycles (where my slave asserts RdComp), the ICU suddenly sends PLB_ABORT. This is while it has the new read request already pending (as secondary read). After the secondary request is removed, I see that ICU issues 9 times a read request (for an unrelated address or recently executed code) that is immediately followed by PLB_ABORT. The abort is so quick that the request never makes it into the PAValid=1 stage. Nonetheless this pattern is repeated 9 times. It seems to me that the PPC ICU has some kind of timeout, which is triggered by the lengthy data transfer time of my slave. It also seems to have some "purge" or "recover from errors" mode where it exhibits that strange ABORT behaviour. Can anyone confirm this? Did I miss it in a datasheet? I "fixed" my slave by reducing the aack to rddack time. Now I reject incoming requests with REARBITRATE until they can be served more timely. However, I'm unsure about how many cycles my slave is allowed to consume. While the crashes did go away, I would like to know for sure that they won't come back when my program code/data map happens to have a "worst case" layout (with respect to the PLB access patterns generated by executing it). Kind regards & have a nice weekend, MarcArticle: 119093
well, i'm at a loss... Perhaps it could be worth your while making a _VERY_ small code that only uses these signals with some dumb logic to see if you can narrow it down to a code optimisation, or a bug in the place/route. Ben <peter> wrote in message news:eea6b0c.3@webx.sUN8CHnE... >I agree, im really puzzled by this. As you indicated i have followed the >guidelines when putting these constraints in the ucf. > > I have tried with and without " with no change in the result. > > Additional information: > > When i run without these constraint i get no errors and i get the > FRAME_ECC instanciated correctly. (Verified in FPGA editor.) > > Also i use only the CRCERROR output from the primitive when i infer it in > the VHDL code.Article: 119094
It seems that precision has a bug, because when I saw the ug70-2.2, there, they have mentioned that when using RAMB16, the attributes "READ_WIDTH_A" and "WRITE_WIDTH_A" must have a value for example WRITE_WIDTH_A=9; READ_WIDTH_A=1. if they are not assigned, so they will never be implemented.(see ug70-2.2 page 137). In my case, precision didn't set the WRITE_WIDTH_A (because I was implementing a ROM =no writes) after I got this error. I added this attribute, re-synthesized the design,and implementation from .edf file was successful.Article: 119095
"Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message
news:f21qd9$keo$1@news.lysator.liu.se...
> On 2007-05-11, Ben Jones <ben.jones@xilinx.com> wrote:
>> Personally I am not a big fan of any sort of IDE/GUIs; I prefer a known
>> good
>> text editor and a collection of command-line tools. The EDK GUI, though,
>> adds value above and beyond this by giving you a bus-centric view of your
>> design's connectivity. Indeed, this sort of high-level module-based
>> design
>> is about the only reason I would want to use any tool other than a simple
>> text editor for FPGA design entry...
>
> This is certainly one feature that seems to make the EDK rather nice.
> Once SystemVerilog (SV) support is more widespread some of that advantage
> might disappear since the SV interface construct makes it significantly
> easier to connect modules to a bus-centric design. (I guess you don't like
> Verilog but perhaps VHDL 2006 has something similar? I don't remember if
> I've read anything about such a feature.)
I'm not a Verilog fan, but I am at least mildly impressed with SystemVerilog
in this respect. You can *almost* achieve the same sort of thing with
record-type ports in VHDL, and there is a proposal for interfaces in VHDL
200x.
> In my imaginary "perfect" development environment, my editor would be
> able to extract bus based information and show it graphically but the
> basic information about bus connectivity should only be located in
> the source code. This way my design would be easier to port between
> different design environments.
That would certainly be nice. The EDK approach at least uses human
read/write-able text files for storing the connectivity and configuration
data, and provides an extensible scripting framework for accessing this
design database. Manually updating the text files causes automatic updates
to the system assembly view. (Only downside: it uses TCL... so it's really
slow...)
So it's a bit like your ideal environment, only not all that portable (for
obvious reasons). :-)
-Ben-
Article: 119096Hi Self, This is a known issue in the unisim_vcomp file that Xilinx is going to fix soon. Due to the fact that this is only for simulation, this component was left out. If you put the following component declaration in the testbench, you can avoid this error: JTAG_SIM_VIRTEX5_inst : JTAG_SIM_VIRTEX5 generic map (PART_NAME => "LX30") -- Specify target V5 device. Possible values are: "LX30", "LX50", "LX85", "LX110", "LX220", "LX330" port map ( TDO => TDO, -- JTAG data output (1-bit) TCK => TCK, -- Clock input (1-bit) TDI => TDI, -- JTAG data input (1-bit) TMS => TMS -- JTAG command input (1-bit) ); Hope this helps Duth On May 10, 3:00 pm, self <pete.dud...@comcast.net> wrote: > Guys > > I am trying to simulate the BSCAN_VIRTEX5 component. The Xilinx > simulation guide, sim.pdf, says that you can instantiate a > JTAG_SIM_VIRTEX5 in your testbench to control the BSCAN component. > > So far I have been unable to get either theISEsimulatoror the Aldecsimulatorto resolve the JTAG_SIM_VIRTEX5 component. I get this > message in theISEsimulator: "Undefined symbol 'JTAG_SIM_VIRTEX5". > > Can anyone tell me what library I need to include in my testbench to > resolve the JTAG_SIM_VIRTEX5 component? > > For reference I include my testbench VHDL. > > Thanks > > Pete > > --------------------------------------------------------------------------- > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.std_logic_arith.all; > library UNISIM; > use UNISIM.VComponents.all; > use UNISIM.VPKG.all; > > ENTITY jtag_interface_tb_vhd IS > END jtag_interface_tb_vhd; > > ARCHITECTURE behavior OF jtag_interface_tb_vhd IS > > signal tdo, tck, tdi, tms : std_logic; > > COMPONENT jtag_interface PORT( > data_in : IN std_logic_vector(31 downto 0); > clk_out : OUT std_logic; > addr_out : OUT std_logic_vector(31 downto 0); > data_out : OUT std_logic_vector(31 downto 0); > we : OUT std_logic); > END COMPONENT; > > SIGNAL data_in : std_logic_vector(31 downto 0) := (others=>'0'); > SIGNAL clk_out : std_logic; > SIGNAL addr_out : std_logic_vector(31 downto 0); > SIGNAL data_out : std_logic_vector(31 downto 0); > SIGNAL we : std_logic; > > constant tck_period : time := 1us; > > BEGIN > > JTAG_SIM_VIRTEX5_inst : JTAG_SIM_VIRTEX5 > generic map (PART_NAME => "LX30") -- Specify target V5 device. > Possible values are: "LX30", "LX50", "LX85", "LX110", "LX220", > "LX330" > port map ( > TDO => TDO, -- JTAG data output (1-bit) > TCK => TCK, -- Clock input (1-bit) > TDI => TDI, -- JTAG data input (1-bit) > TMS => TMS -- JTAG command input (1-bit) > ); > > -- Instantiate the Unit Under Test (UUT) > uut: jtag_interface PORT MAP( > clk_out => clk_out, > addr_out => addr_out, > data_out => data_out, > data_in => data_in, > we => we); > > tck_proc:process > begin > tck <= '0'; > wait for tck_period/2; > tck <= '1'; > wait for tck_period/2; > end process; > > stim_proc: process > begin > -- force into reset state. > tms <= '1'; > tdi <= '0'; > wait for tck_period*10; > wait; > end process; > > ENDArticle: 119097
For anyone still struggling with this issue, there is a workaround of this issue as mentioned in the Xilinx Answer Record # 24859: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=24859 On May 9, 12:45 pm, networkfabul...@gmail.com wrote: > I recently switched over to ISE 9.1 and I noticed a problem where ISE > won't recognize the design hierarchy. Thinking that it might be > something specific to my design, I tried the example design files > provided with one of the Xilinx cores and lo and behold the design > hierarchy is incorrect again. > > Eventually I figured out that it is the synthesis directives (e.g. "// > synthesis syn_noclockbuf = 1") that seem to cause this problem. When I > remove the synthesis directives, ISE 9.1 recognizes the hierarchy > correctly. This behavior is repeatable: > > 1. When I remove the synthesis directives, the hierarchy appears > correctly. > 2. When I include the synthesis directives, the hierarchy disappears. > > Has anyone else noticed something similar or have any insight into > fixing this problem?Article: 119098
On May 11, 9:59 am, "Benjamin Todd" <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > well, i'm at a loss... > > Perhaps it could be worth your while making a _VERY_ small code that only > uses these signals with some dumb logic to see if you can narrow it down to > a code optimisation, or a bug in the place/route. > > Ben > > <peter> wrote in messagenews:eea6b0c.3@webx.sUN8CHnE... > >I agree, im really puzzled by this. As you indicated i have followed the > >guidelines when putting these constraints in the ucf. > > > I have tried with and without " with no change in the result. > > > Additional information: > > > When i run without these constraint i get no errors and i get the > > FRAME_ECC instanciated correctly. (Verified in FPGA editor.) > > > Also i use only the CRCERROR output from the primitive when i infer it in > > the VHDL code. I've reproduced this error. It's a 9.1i SP2 regression. Earlier versions work. I'll file a CR. Bret (Xilinx Product Applications)Article: 119099
Geronimo Stempovski wrote: > Hi all, > > currently I am investigating a data sorting algorithm on hardware. The > algorithm was implemented in VHDL and is currently running on a Xilinx > Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect > in the target application. Therefore I made an analysis with the Xilinx > Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying > results. > > Now I'd like to make an estimation what this circuit would consume on a > comparable ASIC 0.13µm CMOS technology (the FPGA is also based on a 0.13µm > CMOS technology). The target clock frequency is 180 MHz, activity ratio is > 15%. Is there any rule of thumb or calculation rule? > > Any help is highly appreciated !!!! > > Regards Gero > > power is .5*c*v**2*f*sf. Sounds like you know everything but C. So you would need to synthesize or otherwise get a gate count, assume a load per gate and go from there. -- Del Cecchi "This post is my own and doesn’t necessarily represent IBM’s positions, strategies or opinions.”
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