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On May 25, 9:02 pm, Andrea05 <c...@email.it> wrote: > On 25 Mag, 20:45, austin <aus...@xilinx.com> wrote: > > > > > Andrea, > > > Since there are no MGT's, you will need to use some IO's from IO banks. > > > You can use: some number of LVDS 100 ohm differential drivers to > > receivers (one direction only, use two sets of buses), a group of single > > ended IOs matched to a ribbon cable (with ground, signal, ground, > > dignal, this is close to 50 ohms, and can go perhaps 10 meters at the > > speed you need). > > > I suggest the single ended groups, perhaps 8 wires for data, and one > > forwarded clock (for nine signals), and a bus like this for each direction. > > > Clocking these 8 wires at even 10 MHz, would provide 80 Mb/s. At this > > slow a rate, you don't really need to clock forward, but I still would > > suggest it (along with the data, there is the clock on the ninth wire to > > strobe the other end). That way, you don't have to figure out how to > > get the clock off of one pcb, and get it to the other one (for a system > > synchronous solution). > > > Just have registers at each end, and create your own (very simple) > > protocol. If a "data valid" or "data waiting" signal is needed, just > > use another wire. 20 wire ribbon cables are pretty common (ten signal, > > ten grounds). Drive the transmit end with something like LVCMOS 8 mA > > FAST, which is very close to 50 ohms, and there should be no overshoot, > > or undershoot, and the Signal integrity will be good. If that is still > > too strong, 6 mA, and even 4 mA drivers can be selected. > > > The only reason a protocol is required with the MGTs (like aurora:http://www.xilinx.com/products/design_resources/conn_central/grouping... > > is that designers need huge bandwidth, and in order to re-synchronize > > multiple MGTs (channel bonding), a layer is required to manage all that > > stuff. > > > With a simple parallel interface, you pretty much only need to implement > > what you need. > > > To connect these buses to the 405PPC, you will either have to interface > > to the PLB bus, or create an input and output port that is connected to > > the 405PPC. Depending on how fancy you want this to be, it could be as > > simple as input and output instructions (you create the protocol in > > software), or as fancy as a FIFO buffer with DMA into memory mapped into > > the 405PPC data memory (the protocol commonly used here is referred to > > as "flags placed under a rock" which is a reference to one processor > > just waits for a memory location to change, which tells it that the data > > it is waiting for is all there, and ready to be read from memory...the > > transmitting processor sends all the data, and sets the flag to tell the > > receiving processor to pick up the data. > > > Lots of choices here, and not many "standards" as the task is very > > simple, and folks tend to use only what logic they need to in order to > > do the job. > > > Once you pop up to MGTs, there are many more choices, only because there > > are more complex interfaces: ethernet, fibre channel, PCIe, etc..... > > > If you don't need fibre channel, then you don't need media access > > controllers (MAC), etc.http://www.xilinx.com/products/design_resources/conn_central/solution... > > > Austin > > Thank you Austin for your reply, I found it very intresting. > I'll search something about your hints over internet and I'll post the > results (and surely other questions). > > Just another little question. Why, in your opinion, even Xilinx in its > SPI core doesn't support off-chip Master? SPI peripheral seems to fit > well to my design requrements but it has this huge limitation... I > don't understand why... Any ideas? OPB_SPI sucks because it does not support off-chip clock input. Xilinx guys, please remedy this in future versions!!! It is much easier to implement parallel interface for your case if you can afford additional pins. If the distance is not too great even single ended signals could do the job. Regarding reference designs for V4 MiniModule; search here: http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D25726%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html Cheers, GuruArticle: 119851
Hi, In the past I did some work with the Atmel FPSLIC. Eventually the project was changed and the FPSLIC was dropped. I have lots of working code still around from that project. It takes advantage of the tight FPGA + MCU symbiosis, so it's difficult to reuse on other platforms. I wonder if there are any Atmel FPSLIC users out there? I could polish up some of the code and publish it. But then again I'd only want to do it if it is of use to someone. One of the gems is an emulator for the MSP430 instruction set. It has a very small footprint, and emulates one MSP430 instruction in 6 AVR cycles. A normal (non-FPSLIC) AVR would barely be able to fetch the instruction from memory in that time. So please let me know if there's any kind of FPSLIC community out there. Regards, MarcArticle: 119852
jetm...@hotmail.com schrieb: > Hi, > > In the past I did some work with the Atmel FPSLIC. Eventually the > project was changed and the FPSLIC was dropped. > > I have lots of working code still around from that project. It takes > advantage of the tight FPGA + MCU symbiosis, so it's difficult to > reuse on other platforms. > > I wonder if there are any Atmel FPSLIC users out there? I could > polish up some of the code and publish it. But then again I'd only > want to do it if it is of use to someone. > > One of the gems is an emulator for the MSP430 instruction set. It has > a very small footprint, and emulates one MSP430 instruction in 6 AVR > cycles. A normal (non-FPSLIC) AVR would barely be able to fetch the > instruction from memory in that time. > > So please let me know if there's any kind of FPSLIC community out > there. > > Regards, > Marc possible not so many, but some still - I have the FPSLIC kit, and some FPSLIC silicon and still some plans ;) besides there does exist a commercial grade AVR IP core.. so it maybe fun to use the FPSLIC project in plain FPGA with AVR as soft IP as well.. the FPSLIC AVR-FPGA interface can easily be implemented in soft AVR core so the MSP430 AVR+FPGa solution may have its second life (with or without FPSLIC) AnttiArticle: 119853
On May 28, 4:55 am, Newman <newman5...@yahoo.com> wrote: > On May 28, 12:18 am, John Larkin > > <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > > On Sun, 27 May 2007 13:37:24 -0700, Test01 <cpan...@yahoo.com> wrote: > > >From fpga open driver to 150 ohm pull-up and then to 100 Ohm series termination close to the receiver. I used open drain is because I needed to generate 1.8V output. > > > >Can you please also respond my question about Peter's suggestion of using the top transitior until it reaches high threshold of 1.5V? My concern here is that the fpga fabric will have fair amount of prop delay before it turns off the top fpga transistor. > > > It is NOT necessary to use an open drain. It's not even a good idea. > > So Peter's trick is not needed. > > > John > > Test01, > If the VRP and VRN pins for the bank in question are unused, you > might consider adding a couple of resistors to them, changing the > buffer to LVDCI_33. Maybe you need a couple in parallel, and changing > the "series" 100 ohm resistor located at the receiver to 60 ohms > parallel and getting rid of the pull-up. > Just a thought in trying to avoid splicing a series source resistor > at the FPGA. > I think this may be another way of doing what John suggested. > > -Newman Test01, Well, maybe not because I did not consider what the transition from 1 to 0 would look like at the receiver with the parallel termination. -NewmanArticle: 119854
Hi there, I have a virtex II board (xc2v1000), unfortunately no jtag signals are routed on this board (TMS, TDI, TDO, TCK ). This really deprives me from using ChipScope pro on this board to debug my design. Is it possible somehow to tap the jtag ports internally and route them to GPIOs which are available on th board! In that case, I will insert the ChipScope Pro core in my design in the normal fashion and will put that part of the code in the design that will tap the JTAG ports internally and will map them to other GPIOs? FarhanArticle: 119855
On Mon, 28 May 2007 07:34:24 +1200, Jim Granville <no.spam@designtools.maps.co.nz> wrote: >Frank Buss wrote: ><snip> > >If this runs slower, one of my pet ideas for FPGA cores, is to design >them to run from SerialFLASH memory. Top end ones (winbond) run at >150MBd of link speed, so can feed nearly 20MB/s of streaming code. >Ideally, the core has a short-skip opcode, as the jump in such memory >has a higher cost. Or a "four address instruction" like the Pilot Ace, with SerialFlash in place of a tube full of mercury? - BrianArticle: 119856
What is the proper word that describes the total delay in a system from analog input to digital output (including phase shift time in analog and digital filters, calculations + other data transport times)? Propagation delay time, latency or other?Article: 119857
John, I am all for driving 3.3V pushpull instead of open drain from Spartan3 FPGA but ultimately yhr receiver needs to see 1.8V signal without adding any blue wires to the board. From the FPGA driver I have 150 ohm pull-up to 1.8V and then I have 100 Ohm serial resistor to the receiver. The receiver internally has resistor that varies from 400 Ohm to 700 Ohm. Keeping this termination sceheme in mind, I am trying to figure out how I can drive LVCMOSS33 Pushpull? Since this board is in production I can not add pulldown resistor and such. Thanks for your feedback.Article: 119858
Newman, Unfortunately, I do not have liberty to use the VRP and VRN pins. From the S3 FPGA output pin, I have 150 Ohm pull-up and then ohm series resistor close to the receiver. I can change the values of these resistors. I was thinking about driving the FPGA output pin 3.3V push-pull and then remove the 1.8V pull-up but increase the series terminatination value.Article: 119859
Hi, there I am designing an FPGA to DRAM interface, which uses 160MHz clock. The clock cycle is 6ns, after gate level simulation with DRAM model and FPGA netlist of my design, I realized that the propagation delay of IO pad and RAM summed up to higher than 6 ns, As a result, during reading with t_CAS set to 2, I only see data stable on the 3rd clock edge instead of 2nd. From simulation it seems to me I shall play trick by sampling data on the 3rd clock, but I don't want to go unconventional. Is that the correct way of doing things in the FPGA-DRAM design? What are the pitfalls? Thanks in advance.Article: 119860
On 24 mayo, 21:45, Duane Clark <junkm...@junkmail.com> wrote: > Pablo wrote: > > Hi everyone, I want to design a model with my Smt338. This is a > > Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16 > > as DDR memory. First of all I need to implement the hardware > > architecture, so I use edk 8.1 (or edk 8.2) to create a model with > > PowerPC and this DDR memory. In the ucf I map every port, but I have > > not any pin to DDR_CLK, that is, the feedback ddr clock. > > > This is the loc entry: Net fpga_0_GEN_DDR_CLK_FB LOC=3D; > > > What can I do?. Perhaps I could use a DCM_module but I don't know how > > could I implement it. > > One way is to put the feedback on an unused pin: > DDR_Clk_fb : inout std_logic; > > To keep the timing independent of PAR layout, drive the pin with a DDR > register: > DDR_CLK_FB_e: FDDRRSE > port map ( > Q =3D> DDR_Clk_fb_o, > C0 =3D> CLK90, > C1 =3D> CLK90n, > CE =3D> '1', > D0 =3D> '1', > D1 =3D> '0', > R =3D> '0', > S =3D> '0' > ); > > Then instantiate the io buffer: > > ddr_clk_io : IOBUF > port map ( > I =3D> DDR_Clk_fb_o, > IO =3D> DDR_Clk_fb, > O =3D> DDR_Clk_fb_i, > T =3D> '0' > ); > > And so, of course, DDR_Clk_fb_i is the input feedback signal. So the process is the following: 1=BA. I design my powerpc model with a generic memory core. This produce the CLK_DDR_FEEDBACK pin. 2=BA I don't use this pin and (in ISE) I change the system_stub.vhd like you have said. Correct me please. I am very grateful for your help, and if you could send me some file in which I could see this change. Thanks again PabloArticle: 119861
Hello, Does anyone else have problems with MPMC2 + flash bootloader in EDK v9? I started a design on the FX12 mini-module using the ethernet echo server reference design from Avnet. I then added a flash bootloader functionality by taking the flash controller from another Avnet reference design. Unfortunately this combination doesn't work for some reason. A webcase with Xilinx (opened for one month) did not offer a solution for this issue. Avnet however was quicker to respond, they acknowledged the problem, quoting : "The bootloader design in EDK 9.1.02 using the MPMC2 core has some issues.". They sent me a modified echo server design using the PLB DDR controller instead of the MPMC2 and it works. Unfortunately the perfomance suffers. I have yet to understand what the particular issue is. It is not clear if this is a flaw intrinsic to MPMC2 or if it's related to the FX12 mini-module. I'd like to know about others experiences with the MPCM2 and/or mini-module. Thanks! Patrick DuboisArticle: 119862
jetmarc@hotmail.com writes: > I wonder if there are any Atmel FPSLIC users out there? Yep. I do most of my work on the FPSLIC. http://research.cs.berkeley.edu/project/slipway/ Right now I'm working on getting Icarus' synthesis to feed my PAR tool for the FPSLIC. > So please let me know if there's any kind of FPSLIC community out > there. You came to the right place (comp.arch.fpga); I think this would be the best place to post it. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 119863
On May 27, 11:36 am, Frank Buss <f...@frank-buss.de> wrote: > I think readability is very good (ok, maybe because I know Forth and Lisp) > and power-usage should be good, too, because fewer LEs are used. My current > Forth FPGA implementation needs 319 LEs (about 5% of the small Cyclone > EP1C6Q240C8). But I expect 10 times slower than e.g. the T65, so the all in > all cycles per power would be not so good. > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de Don't worry to much about speed. You will be amazed how easy it is to optimize uCode, as soon as the processor really works. And nobody says, that you have only one execution unit in the system. (Had once something like this with 2.5 execution units, controlling a 36 bit proecessor (data width) But, excellent project !Article: 119864
On May 23, 12:07 am, nandit...@gmail.com wrote: > Hi , > > I am using Altera Quartus II version 4.0 . The EPS125 device has > 138 M4K blocks > 224 M512 blocks > 2 number of 512K Mram blocks > > has a total of 1,944,576 bits. > > (http://www.altera.com/products/devices/stratix/features/stx- > trimatrix.html ) > > the problem i am facing is i am trying to fit in 4 buffer data blocks > each of size 16384*14 bits > (total 229376*4 =917504) > plus i have additional fifo and single port Ram of sizes 8192 , and > 1500 bits > > The problem is though there is adequate RAM available , I am not able > to fit in all the memory; only 48% of the RAM is used. > > The fitter resourse summary says more M-Ram blocks are required but > most of M4K and M512 blokcs are not used. ie 40/224 M512 blocks are > used, 2/138 M4K blocks and 2-MRam blocks... > > I am fairly new to FPGAs and stuff so i would appreciate all help. > > thanks and regards. Hi, It does appear you have enough RAM in the device. You should put 2 of your buffer data blocks in M-RAMs (one M-RAM for each), and two more in M4K RAMs (56 M4Ks for each). The remaining RAMs look to be small and appear to be fitting fine. You have two options to make this happen. 1. In the altsyncram megafunction, choose the type of the memory block to be M4K for two of the buffers. The other two should use a different altsyncram instantitation that either leaves RAM type set to Auto, or chooses M-RAM. 2. Upgrade to a more recent version of Quartus II. I believe that the latest versions of Quartus II will automatically figure out that you don't have enough M-RAMs to implement all four of these data buffers, and will move two of them to use M4Ks, when you leave the RAM type set to Auto (the default). Hope this helps. Vaughn Betz AlteraArticle: 119865
maverick schrieb: > Hi there, > I have a virtex II board (xc2v1000), unfortunately no jtag signals are > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me > from using ChipScope pro on this board to debug my design. Is it > possible somehow to tap the jtag ports internally and route them to > GPIOs which are available on th board! In that case, I will insert the > ChipScope Pro core in my design in the normal fashion and will put > that part of the code in the design that will tap the JTAG ports > internally and will map them to other GPIOs? > > > Farhan sure, get it here: http://code.google.com/p/fpga-tools/downloads/list AnttiArticle: 119866
Hi everyone, I tried to figure this one out myself but it turns out not so easy for someone with this lack of experience like mine. I'm writing a PC app that will issue JTAG commands over paralell port to some unspecific FPGA at the moment, running let's say some cipher algorithm. I want to use my app to set input levels with JTAG and observe how it changes output signals. In order to impose signal levels over JTAG with my application I have to somehow "halt" the main FPGA clock if I want to do it in an exact moment and here's my question: is the FPGA clock stopped when TAP controller is in some specific state, concerning JTAG BSR operations or do I have to do it myself (how-to?) ? Thanx in advance! ChrisArticle: 119867
I've tried using the "interface" construct in a Quartus-II project, but I can't tell if it's working the way it is supposed to. I tried declaring an interface like the following: interface interface_cpu_vgachar_vga( input logic [15:0] cpu_addr, input logic cpu_write, input logic cpu_read, input logic [15:0] cpu_wdata, output logic [15:0] cpu_rdata ); endinterface // : interface_cpu_vgachar_vga interface interface_cpu_vgachar_cpu( output logic [15:0] cpu_addr, output logic cpu_write, output logic cpu_read, output logic [15:0] cpu_wdata, input logic [15:0] cpu_rdata ); endinterface // : interface_cpu_vgachar_cpu When I use either interface as a top-level port, Altera's pin-assignment menu lists them as 'bidir'. And the synthesis-logfile shows a bunch of warnings like this: Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus if_cpu.cpu_rdata[0]~15 that it feeds Warning: The bidir "if_cpu.cpu_wdata[0]" has no source; inserted an always disabled tri-state buffer. What am I doing wrong?Article: 119868
Pablo wrote: > > So the process is the following: > > 1º. I design my powerpc model with a generic memory core. This produce > the CLK_DDR_FEEDBACK pin. > 2º I don't use this pin and (in ISE) I change the system_stub.vhd like > you have said. That is the way I do it. I always use top level ISE projects, and embed EDK systems in them. I don't know how it would be done in a straight EDK top level project. The clock signal should be going off the FPGA through some PCB traces and back onto the FPGA feedback pin. If that pin does not exist on the board, the method I showed will at least run it through an output and input buffer, so the only part that is missing is the time it takes to go through the PCB traces. That should be relatively unimportant, in part because that time will be virtually a constant.Article: 119869
Brian Drummond wrote: > On Mon, 28 May 2007 07:34:24 +1200, Jim Granville > <no.spam@designtools.maps.co.nz> wrote: > > >>Frank Buss wrote: >><snip> > > >>If this runs slower, one of my pet ideas for FPGA cores, is to design >>them to run from SerialFLASH memory. Top end ones (winbond) run at >>150MBd of link speed, so can feed nearly 20MB/s of streaming code. >>Ideally, the core has a short-skip opcode, as the jump in such memory >>has a higher cost. > > > Or a "four address instruction" like the Pilot Ace, with SerialFlash in > place of a tube full of mercury? You've lost me ? -jgArticle: 119870
"Rodney Smith, a sports-car loving executive who built a startup programmable-logic company called Altera into an industry powerhouse, was killed Friday in a bicycle accident in Menlo Park. Smith, who retired four years as chairman and CEO of the FPGA company, was 67" Without Rodney, Altera wouldn't have been like it is today - my condoleances. LucArticle: 119871
More than 30 years ago, we worked together at Fairchild, and he was my best friend. My condolences to his wife Mary and to the Altera community. In sorrow, Peter AlfkeArticle: 119872
On May 28, 12:40 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Brian Drummond wrote: > > On Mon, 28 May 2007 07:34:24 +1200, Jim Granville > > <no.s...@designtools.maps.co.nz> wrote: > > >>Frank Buss wrote: > >><snip> > > >>If this runs slower, one of my pet ideas for FPGA cores, is to design > >>them to run from SerialFLASH memory. Top end ones (winbond) run at > >>150MBd of link speed, so can feed nearly 20MB/s of streaming code. > >>Ideally, the core has a short-skip opcode, as the jump in such memory > >>has a higher cost. > > > Or a "four address instruction" like the Pilot Ace, with SerialFlash in > > place of a tube full of mercury? > > You've lost me ? > -jg Me too, but this looks relevant http://research.microsoft.com/~GBell/Computer_Structures__Readings_and_Examples/00000213.htmArticle: 119873
On May 28, 3:15 am, Yrjola <yrj...@op.pl> wrote: > Hello, > > I created vhdl model of risc processor. During simulation it works > correctly, but when I programmed and run it on FPGA Cyclone device, it > didn't work. So I applied some signals in SignalTap Analyzer (without > changing vhdl code), and it started work properly. I know that problem > description is general, but maybe someone can give me some hint, what > can be wrong, or what should I look for. > > Thanks in advice. > > -- > Maciek I have been getting the same type of problems, but my target fails. What I have run into are adding signals to some test points. When I do this operations fail. When I remove them it works. I currently have a problem which I can't fix. I have some VHDL code which is an address decoder and it worked in the target. I added some more registers to decode and now I can't get it to work at all. I wonder if they are some how related? RobArticle: 119874
Rob wrote: > On May 28, 3:15 am, Yrjola <yrj...@op.pl> wrote: >> Hello, >> >> I created vhdl model of risc processor. During simulation it works >> correctly, but when I programmed and run it on FPGA Cyclone device, it >> didn't work. So I applied some signals in SignalTap Analyzer (without >> changing vhdl code), and it started work properly. I know that problem >> description is general, but maybe someone can give me some hint, what >> can be wrong, or what should I look for. >> >> Thanks in advice. >> >> -- >> Maciek > > > I have been getting the same type of problems, but my target fails. > What I have run into are adding signals to some test points. > When I do this operations fail. When I remove them it works. > I currently have a problem which I can't fix. I have some VHDL code > which is an address decoder and it worked in the target. I added some > more registers to decode and now I can't get it to work at all. > > I wonder if they are some how related? > > Rob > Both feel like timing problems. Synchronize to a single clock. Check static timing. -- Mike Treseler
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