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Hello, did my update go wrong or does also a succeeded update of Xilinx Webpack with 9_1_03i_lin.zip still display "Release Version: 9.1.01i"? Webupdate reports now : " There are no updates to display at this time"... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 117376
With the new service pack, does the build number change on any of the log file (i.e .syr .ngd. .mrp .par)? For example, I would expect the first line in the MAP report to read something like, " Release 9.1i Map J.33". I am downloading now and will test to see what happens on my end (albeit PC version). I'll post again once it finishes. -David "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:eugumh$k7b$1@lnx107.hrz.tu-darmstadt.de... > Hello, > > did my update go wrong or does also a succeeded update of Xilinx Webpack > with 9_1_03i_lin.zip still display "Release Version: 9.1.01i"? > > Webupdate reports now : " There are no updates to display at this time"... > > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 117377
On 29 Mrz., 18:53, Peter Wallace <p...@karpy.com> wrote: > On Wed, 28 Mar 2007 10:12:15 -0700, jidan1 wrote: > > Hi, > > > To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 > > XCS400) at the same time, I decided as a programmer to use the Xilinx > > Parallel Cable III. I implemented the programmer 100% the same as found > > in Xilinx's website ( > >http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html). > > The programmer worked, but not without problems. For programming the > > Atmel uC I used AVRdude, and for the FPGA, ISE9.1i. The ribbon-cable > > from the LPT port to Programmer was 20cm long and from the programmer to > > the uC/FPGA board was not more than 10 cm. The problem related with this > > programmer were verification errors, i.e the PC can't program or read > > properly from the board. The interesting thing is how these verification > > problem came up. In the morning when I turn the PC and Board on, these > > verification errors are a lot. When the code that I want to download is > > big, its impossible to program the FPGA/uC, for small codes it works but > > after many tries. After 10 tries or so, the programming works correct > > and no verification errors no matter how many times I try to download > > the code or how big the code is, and this without even touching a thing > > on the hardware!!! > > > Since this problem applies to more than one board, I assume the problem > > must lay on the programmer itself. My explanation is that maybe the > > buffer IC's get hot or something...I really don't know. I want to know > > if there is anyone who has had problems with this programmer cable. > > > Thank You, > > JJ > > I have a simple upgrade to the parallel cable III that has Schmitt > triggers on the clock, and a simple shunt regulator with an LED that > limits internal VCC to about 4V, giving TTL compatible LPT interface even > if used with 5V JTAG. > > It works reliably with 2.5V to 5V JTAG chips > > I have PCBs which I can send for free as long as its in the USA (1"x1" > card in envelope) Requires SMT assy > > Peter Wallace Thanks Peter, but if you can show us the schematics that will be more than enough. JJArticle: 117378
On Mar 28, 6:55 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > <jid...@hotmail.com> wrote in message > > news:1175098335.158323.203250@n59g2000hsh.googlegroups.com... > > The newer Xilinx programming cables (Parallel Cable IV, Platform Cable USB) > use comparators rather than simple buffers to establish proper voltage Where can I get these kind of comparators? What about multiple voltages? Any sample circuits I can use as a reference? Thanks - E.Article: 117379
John, Maybe I can add something more: The ECP2M is available in a 256fpBGA package. This is AFAIK the smallest package in the industry. If you need the more fancy stuff - you can always select the LatticeSC or LatticeSCM. These add a lot of features combined with very high speed (standard) I/O - up to 2Gbps (haven't seen such high speeds from Xilinx nor Altera) and similar power figures (100mW). This device is also available in a small footprint 256fpBGA. In my opinion this means that the silicon is very reliable - and Lattice is well in control of the design process of high speed I/O. But as you said, I haven't seen any objective comparison table yet. Luc On Wed, 28 Mar 2007 14:16:15 -0700, "John_H" <newsgroup@johnhandwork.com> wrote: >"vasile" <piclist9@gmail.com> wrote in message >news:1175110434.467891.112950@n59g2000hsh.googlegroups.com... >> Hi, >> >> I need to chose between the Altera Stratix II GX or Stratix III GX and >> some Xilinx Virtex5 FPGA for an implementation of gigabit interface >> into a multi DSP system. >> >> Could you suggest pro and cons between Altera and Xilinx (or maybe >> others) for such design ? >> If I'm trying to compare Altera with Xilinx FPGA based on those >> websites, both are telling is better than the other. >> Maybe you know and independent comparison table between those two ? >> >> thank you, >> Vasile > >Do you need the raw power and size of those devices or do you long for >something more cost effective do do generic workhorse processing at decent >speeds and sizes? If so, consider the Lattice ECP2M series as well. They >may also have the lowest power transceivers in the industry: > > Lattice: > 3.125Gbps Embedded SERDES (ECP2M only) > Low 100mW power per channel > > Xilinx: > Flexible SERDES with 100 Mbps-to-3.2 Gbps operating range supports all >popular protocols > Lowest power consumption in the industry: less than 100 mW per channel >at 3.2 Gbps > (shall we say 99.99 mW?) > >The Lattice devices may not be fancy. They are used in quads rather than >trying to divide the functionality into smaller increments. But if what you >need is the raw bandwidth without super-extreme processing in between, >consider the outsider. > >In my opinion, the ECP2M product has given Lattice a strong leg up on the >competition for a strong range of price/performance devices. > >The points that are imprtant to some may not be important to others. Are >you concerned with: > > Power? (Is >100 mW a problem?) > Speed? (Is 3.125Gb/s enough?) > Cost? (Whoa) > Flexibility? (How much granularity? # of independent channels? Channel >width?) > Device size? (How many LEs/LUTs will you need? RAM?) > Multiplier/DSPblock functionality? (Are there features that tip the >balance) > Logic speed? (Do you need 200 MHz or 500 MHz? Simple or complex paths?) > Clocking? (Do the devices support your clock source cleanly?) > >I haven't seen a good apples-to-apples comparison becasue these choices and >concerns tend to make analysis less obvious. > >- John_H >Article: 117380
<EvalXX@gmail.com> wrote in message news:1175195472.611147.280310@n59g2000hsh.googlegroups.com... > On Mar 28, 6:55 pm, "John_H" <newsgr...@johnhandwork.com> wrote: >> <jid...@hotmail.com> wrote in message >> >> news:1175098335.158323.203250@n59g2000hsh.googlegroups.com... >> >> The newer Xilinx programming cables (Parallel Cable IV, Platform Cable >> USB) >> use comparators rather than simple buffers to establish proper voltage > > > Where can I get these kind of comparators? What about multiple > voltages? Any sample circuits I can use as a reference? > > Thanks > - E. Almost any kind of comparators? Take a look at the Platform Cable USB Product Specification http://direct.xilinx.com/bvdocs/publications/ds300.pdf pages 11-12 for an idea what Xilinx does to get the voltage compliance and well-defined threshold values. If you substitute the 5V LPT buffers for the CPLD, you can pretty much cut & paste your way from a Parallel-III to a Parallel-IV style cable (though you'd still refer to it in SW as a Paralell-III). I should reiterate that having your VCC act as both a VREF and source for a DC-DC converter is a solid way to design for the 5V LPT interface and the lower-voltage JTAG interface.Article: 117381
Herbert Kleebauer wrote: > Symon wrote: > >>"Herbert Kleebauer" <klee@unibwm.de> wrote in message > > >>>Does anybody know whether there is a company which sells Spartan3 >>>chips (or any other FPGA type) already soldered to an adaptor board >>>like: >>> >>>http://www.rsonline.de/cgi-bin/bv/rswww/searchBrowseAction.do?N=0&Ntk=I18NAll&Ntt=295-4331 >>> >>>Preferable with the GND an VCC pins already connected and capacitors >>>on the adapter. >>> >> >>Hi Herbert, >>Apart from the ones John mentioned? >>http://www.enterpoint.co.uk/component_replacements/craignell.html >> >>Also, this might help. >> >>http://www.fpga-faq.com/FPGA_Boards.shtml > > > Yes I know, there are many development boards, but we don't want a > board but the chip. As there is a big difference whether you make > a design at gate level using a schematic entry or use high level > VHDL code, there also is a big difference whether you buy a CPU and > built a computer system or you buy a ready to use motherboard to built > a computer system. The same is true for FPGA's and ready to use FPGA > development boards. You have to go at least once to the low level to > understand the problems, then you can do it at a higher level. Yes, I can follow that, but then why not use a PLCC CPLD, for the hardware ? That is further to the low level, than a FPGA ? -jgArticle: 117382
Uwe, After installing service pack 3, I was not able to reproduce what you are seeing. I have occasionally seen what you are describing, but it has never been anything that indicated a bad install. Overall, I would not be too concerned as long as your report files reflect the correct build number. One peculiar item I noticed after the install was a need to reboot. I don't recall this ever being the case with previous builds. Please let me know if you or anyone else is having problems due to this. -David "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:eugumh$k7b$1@lnx107.hrz.tu-darmstadt.de... > Hello, > > did my update go wrong or does also a succeeded update of Xilinx Webpack > with 9_1_03i_lin.zip still display "Release Version: 9.1.01i"? > > Webupdate reports now : " There are no updates to display at this time"... > > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 117383
Hi,
The VHDL standards community needs feedback from VHDL users.
Currently the Accellera VHDL TSC is working on enhancements
to add classes/OO, Randomization constructs, and Functional
Coverage with a goal of giving VHDL the same verification
capability as SystemVerilog or E.
One of the VHDL simulation vendors has indicated that they
only want to implement new features if the user community
wants these features.
The questions come down to:
Do you want these features added to VHDL?
Do you want to VHDL to be capable of handling all of your
testbench needs?
This work is work in progress and below is the current status.
Keep in mind too that your interest/support of this work will
help raise the focus and inspiration of those doing the work.
Classes / OO:
Peter Ashenden submitted a class proposal last year and
provided updates to it this year at DVCon. Currently
he plans on finishing an updated draft soon.
Randomization:
I just submitted the first draft of the randomization proposal.
Functional Coverage:
I have started working on this - anyone else who is interested
is welcome to contribute as much as they would like.
With a focused effort, like the one to finish the Accellera 3.0
draft of the standard, I think we can be done with these by
September.
Although some have expressed doubt, it is clear that vendors
will do what their user community asks them to do - otherwise,
someone else will and, as a result, will earn your business.
You can post here, send your reply to me (let me know if I can use
either your name and/or company name when I tally the results
for the Accellera VHDL TSC), or join the Accellera VHDL TSC
(which you can do as a non-Accellera member by registering)
and post your reply there.
Thanks,
Jim Lewis
VHDL Evangelist
SynthWorks VHDL Training
Article: 117384> Otherwise, as your register r0 is read-only, you can do this and get > your NOP for free in terms of required opcodes. Likewise you can emulate > register moves with "ADD r_dest, r_source, r0". I am just implementing the backend of the processor and some issues came up where I am not so sure how to handle them in a proper way. Lets assume I have two Execution Units (1 cycle delay), one memory pipeline (2 cycle delay) and one multiplier(n cycle delay). Lets say I wanna have two write back ports to the register file, so normally they are occupied by the two integer execution units. If there is a load in the memory pipeline then I need in the end one of the write ports and its not possible that both EXECUTION units write a result back. In other words, I cant do an NOP with ADD r0, r0, r0 as then two entities (if the mempipe has dealt with a load instruction) try to write to one write ports. So I assume I need here two additional signals that tell me that either the output of the alu is valid and should be written into the regfile or that the load is finished and has fetch a valid value from the datacache that is ready to be written back into the regfile. Is this a good approach or complete nonsense? CheersArticle: 117385
I have a C program I'm developing for the Microblaze SOC processor.
I'm using the Xilinx Platform Studio ver. 8.2.02.
I had included in the project a particular *.c source file, then
removed it. The compiler/linker/application builder insists on trying
to compile/link this file, giving the error:
TestApp_Memory.c:10: error: `GPIO_DataReg' undeclared here (not
in a function)
" TestApp_Memory.c" is the file I've removed. I've "cleaned"
everything I can find, but the error persists.
Can anyone offer suggestions short of creating a clean app (which I've
done twice now)?
Tom J
Article: 117386Patrick, Why have a NOP instruction? If NOP is a problem, take it out. After all, it isn't exactly there to do anything. I am sure that the compiler can create a "no function" set of instructions, if these have to be supported. For example, circular shift right, then circular shift left (result is the same as before, including all flags). AustinArticle: 117387
Yes, Lattice has the industry-smallest FBGA: the 256 pin device. They also have 484, 672, and 900 ball FBGAs available as you go larger in device size. I would guess your point is that the higher-function devices aren't available in smaller sizes such as the Virtex-5 LX30T at 665 balls. I honestly haven't looked closely at the SC/SCM devices because my cost/functionality point keeps me out of the "big leagues" for anything except initial prototypes. I was very impressed by the Lattice offering that hit a niche that seems to be getting wider week by week with a product that has agressive cost targets and strong functionality that either meets or exceeds the specifications of similar (low-cost family) devices from other vendors. Some engineers might hesitate a transition to a new design and tool flow (which might not appear terribly new once they get into it) if it's a matter of choosing a different "me too" device. The ECP2M is currently without peer for some gigabit and high-memory needs, in my humble opinion. - John_H <lb.edc@telenet.be> wrote in message news:qp6o039sg885sf04d8cg4dgick2cbckhl2@4ax.com... > John, > > Maybe I can add something more: > The ECP2M is available in a 256fpBGA package. This is AFAIK the > smallest package in the industry. > If you need the more fancy stuff - you can always select the LatticeSC > or LatticeSCM. These add a lot of features combined with very high > speed (standard) I/O - up to 2Gbps (haven't seen such high speeds from > Xilinx nor Altera) and similar power figures (100mW). This device is > also available in a small footprint 256fpBGA. In my opinion this means > that the silicon is very reliable - and Lattice is well in control of > the design process of high speed I/O. > > But as you said, I haven't seen any objective comparison table yet. > > Luc > > On Wed, 28 Mar 2007 14:16:15 -0700, "John_H" > <newsgroup@johnhandwork.com> wrote: > >>"vasile" <piclist9@gmail.com> wrote in message >>news:1175110434.467891.112950@n59g2000hsh.googlegroups.com... >>> Hi, >>> >>> I need to chose between the Altera Stratix II GX or Stratix III GX and >>> some Xilinx Virtex5 FPGA for an implementation of gigabit interface >>> into a multi DSP system. >>> >>> Could you suggest pro and cons between Altera and Xilinx (or maybe >>> others) for such design ? >>> If I'm trying to compare Altera with Xilinx FPGA based on those >>> websites, both are telling is better than the other. >>> Maybe you know and independent comparison table between those two ? >>> >>> thank you, >>> Vasile >> >>Do you need the raw power and size of those devices or do you long for >>something more cost effective do do generic workhorse processing at decent >>speeds and sizes? If so, consider the Lattice ECP2M series as well. They >>may also have the lowest power transceivers in the industry: >> >> Lattice: >> 3.125Gbps Embedded SERDES (ECP2M only) >> Low 100mW power per channel >> >> Xilinx: >> Flexible SERDES with 100 Mbps-to-3.2 Gbps operating range supports all >>popular protocols >> Lowest power consumption in the industry: less than 100 mW per channel >>at 3.2 Gbps >> (shall we say 99.99 mW?) >> >>The Lattice devices may not be fancy. They are used in quads rather than >>trying to divide the functionality into smaller increments. But if what >>you >>need is the raw bandwidth without super-extreme processing in between, >>consider the outsider. >> >>In my opinion, the ECP2M product has given Lattice a strong leg up on the >>competition for a strong range of price/performance devices. >> >>The points that are imprtant to some may not be important to others. Are >>you concerned with: >> >> Power? (Is >100 mW a problem?) >> Speed? (Is 3.125Gb/s enough?) >> Cost? (Whoa) >> Flexibility? (How much granularity? # of independent channels? >> Channel >>width?) >> Device size? (How many LEs/LUTs will you need? RAM?) >> Multiplier/DSPblock functionality? (Are there features that tip the >>balance) >> Logic speed? (Do you need 200 MHz or 500 MHz? Simple or complex >> paths?) >> Clocking? (Do the devices support your clock source cleanly?) >> >>I haven't seen a good apples-to-apples comparison becasue these choices >>and >>concerns tend to make analysis less obvious. >> >>- John_H >>Article: 117388
Austin Lesea wrote: > Patrick, > > Why have a NOP instruction? If NOP is a problem, take it out. > > After all, it isn't exactly there to do anything. > > I am sure that the compiler can create a "no function" set of > instructions, if these have to be supported. > > For example, circular shift right, then circular shift left (result is > the same as before, including all flags). Yes, but commonly a NOP is one cycle, as one use is for simple timing delay patches - one could also support NOP2, NOP3, on some cores, that are more memory efficent for longer delays. You can certainly alias onto any 'do nothing single cycle opcode' which may have been what Austin was meaning ? -jgArticle: 117389
> You can certainly alias onto any 'do nothing single cycle opcode' which > may have been what Austin was meaning ? The problem is as follows: I have got two write ports to the register file. In my architecture I have two execution units, a memory access unit and a multiplier. So in the worst case scenario, it could happen that all these four units want to write to the regfile. This causes a structural hazard as I only have two write ports. My question is now whats the best way to deal with this situation? My approach was, that if OP = 0, the alu stage outputs a signal to the writeback stage that there is no meaningful outport available and I dont need the write port. So instead of having a NOP that writes in the WB stage 0 into R0 I just use an additional control signal so that the WB stage doesnt use the write port and it would be available for the memory access pipeline for instance. So either the alu output should be written back or the memory access uses the writeport. I have to make sure that not both of the units want to access the same write port in the same clock cycle. Is this okay to handle this with additional control signals or is there another way to do that? Or can I use here some kind kind of resolved signal where either the the output of the alu or the output of the memory access unit determines the value to be written?Article: 117390
Howdy, For FM/AM demod, you require a complex baseband. I am downconverting the IF from 1MHz to baseband by multiplying the input stream (12 bits) from the ADC with Sin and Cosine outputs of a DDS and therefore, generating I, Q I am using standard 18x18 signed multipliers in Xilinx to do the mixing. Is this right or should I use a complex multiplier? The reason why I am asking this question is because, I had implemented the whole datapath (Downconversion, Rate decimation, Compensating FIR) and verified it on the bench and then implemented CORDIC for getting FM, which never worked. So instead I tried to do AM demod by not using CORDIC but (Sq(I) + Sq(Q)) using standard 18x18 signed multipliers and still no AM demod which is supposed to be simple. Then I took the CIC and CFIR filters out and tried to do demod straight after the mixing, still nothing. So I'm kinda stuck here, any help will be appreciated Thanks -M p.s. I don't have access to Matlab and System generator, but I'm buying them next week. I figured, doing digital radio design without modeling tools is like digging your own grave!!!Article: 117391
On Mar 29, 5:50 pm, "Tom J" <t...@pallassystems.com> wrote: > I have a C program I'm developing for the Microblaze SOC processor. > I'm using the Xilinx Platform Studio ver. 8.2.02. > > I had included in the project a particular *.c source file, then > removed it. The compiler/linker/application builder insists on trying > to compile/link this file, giving the error: > TestApp_Memory.c:10: error: `GPIO_DataReg' undeclared here (not > in a function) > > " TestApp_Memory.c" is the file I've removed. I've "cleaned" > everything I can find, but the error persists. > > Can anyone offer suggestions short of creating a clean app (which I've > done twice now)? > > Tom J Open the .xmp file for your project and see if it still list "TestApp_Memory.c". If it does, remove it. I have not seen this paticular problem, but I have seen other stuff left in the *.xmp file after I removed it from the project. Specifically, when I removed a peripheral that I had locked the memory address assignment on, the fact that it was locked was still in the *.xmp file. If I then added the peripheral back in, I could not assign it a memory address until I edited the *.xmp file. I think that the EDK developers did the right thing by keeping almost all of the EDK files plain text. Only the Base Sysem Builder file is not plain text as far as I know. I keep all of my designs under version control with CVS, and EDK is so much better than ISE in this regard. The few sugestions I would have for EDK in this regard are to change the BSB file to text, stop rewritting the *.xmp file if it has not changed, and make sure you keep date stamps, gui settings etc segregated from the real design files. Regards, John McCaskill www.fastertechnology.comArticle: 117392
On Mar 29, 7:09 pm, "morpheus" <saurs...@gmail.com> wrote: > Howdy, > For FM/AM demod, you require a complex baseband. I am downconverting > the IF from 1MHz to baseband by multiplying the input stream (12 bits) > from the ADC with Sin and Cosine outputs of a DDS and therefore, > generating I, Q > I am using standard 18x18 signed multipliers in Xilinx to do the > mixing. Is this right or should I use a complex multiplier? > The reason why I am asking this question is because, I had implemented > the whole datapath (Downconversion, Rate decimation, Compensating FIR) > and verified it on the bench and then implemented CORDIC for getting > FM, which never worked. > So instead I tried to do AM demod by not using CORDIC but (Sq(I) + > Sq(Q)) using standard 18x18 signed multipliers and still no AM demod > which is supposed to be simple. > Then I took the CIC and CFIR filters out and tried to do demod > straight after the mixing, still nothing. > So I'm kinda stuck here, any help will be appreciated > Thanks > -M > p.s. I don't have access to Matlab and System generator, but I'm > buying them next week. I figured, doing digital radio design without > modeling tools is like digging your own grave!!! Multipling a real times a complex only needs two real multiplies, so you do not need a complex multiplier. What you do need to keep an eye on is where you centered your complex signal, and does this match what the downstream processing is expecting. Did you shift your signal to be at DC to fs/2, or from -fs/4 to fs/f? Did you filter and decimate after mixing, or leave it oversampled? There are multiple ways to do this, and if the different parts do not agree, you get garbage out. Here is a starting point for some further explanation: http://en.wikipedia.org/wiki/Analytic_signal Regards, John McCaskill www.fastertechnology.comArticle: 117393
> 1920x8bits = 15.3kbits, this is less than one BRAM... I am guessing > "data_width" and "mem_size" are generics and the actual parameters on the > instance are larger than that or there are multiple instances of it. If > those are the actual parameters and there is only one instance, this code > fails to explain the 44 extra BRAMs. Even if it was x8bytes, this would > still be only 8 BRAMs instead of 45. It seems like your posting is lacking > some critical details that make it impossible for us to make educated > guesses. Also, having a wrapper around your 'top' design for a synthesis > implementation is suspicious. > > The code you posted is a BRAM inference wrapper for a dual port RAM with > independently clocked read and write ports, the first real questions are: > how many times is this generic wrapper used, what are the instance > parameters in each case and what are they for? > > Since a very decent scaler can be achieved with five lines worth of video > data that would require 15 BRAMs for inputs and three more for output > buffering, chances are that your scaler's wrapper needs a diet unless it > does other fancy things you may not be aware of. > > > (gosh why cant I just have the mem_array just automatically use the > > dram....) > > Because DRAMs have refresh cycles, row activation, row precharge and > numerous other quirks designers have to take care of before initiating any > actual data transfers... I told you so last week. Even if Xilinx had > hardware memory controllers, you would still have to work with the variable > latency and possible read re-ordering. Well, the reference design data file did say that the purpose of the wrapper is to minimize the number of external interconnect required by the scaler so that it can fit into a realistic target device. My wrapper has instantiates 2 sequential lookup tables and 6 horizontal coefficient tables and 3 vertical coefficient tables. Hmm, I guess I will be looking at other designs which have interface with the DDR SDRAM controller and from there, try to understand the interface and I hope to be able to do the same for my video scaler design. Thanks alot for checking for me that the code is a BRAM inference wrapper for a dual port RAM. with independently clocked read and write ports. Yeh and sadly the evaluation board doesn't come with a dram interface instruction guides or somewhat. IT only comes with the pin numbers and a few brief description, alas.Article: 117394
Patrick wrote: >>You can certainly alias onto any 'do nothing single cycle opcode' which >>may have been what Austin was meaning ? > > > The problem is as follows: I have got two write ports to the register > file. In my architecture I have two execution units, a memory access > unit and > a multiplier. So in the worst case scenario, it could happen that all > these four units want to write to the regfile. This causes a > structural hazard as I only > have two write ports. My question is now whats the best way to deal > with this situation? My approach was, that if OP = 0, the alu stage > outputs a signal > to the writeback stage that there is no meaningful outport available > and I dont need the write port. So instead of having a NOP that writes > in the WB stage 0 > into R0 I just use an additional control signal so that the WB stage > doesnt use the write port and it would be available for the memory > access pipeline for instance. > So either the alu output should be written back or the memory access > uses the writeport. I have to make sure that not both of the units > want > to access the same write port in the same clock cycle. Is this okay to > handle this with additional control signals or is there another way to > do that? Or can I use > here some kind kind of resolved signal where either the the output of > the alu or the output of the memory access unit determines the value > to be written? I am a little lost, but if you are saying the ALUs share register resource, then yes, you will need protection aginst same-reg writes, - but you will need that anyway, for normal operation ? ie a NOP should usually be a simpler, special case subset of normal operations ?. -jgArticle: 117395
Hey John, I have centered the signal between DC and fs/2. My problem is that even though the I and Q channels are getting mixed correctly (verified by offsetting the carrier frequency and watching the modulation move by the offset value around DC on a spectrum analyzer), the demod is not working, sq(I) + sq(Q) seems like a dead output....i checked the synthesis report and post P&R simulation and it seems to be working in simulation. Bizarro!!! -MArticle: 117396
> I am a little lost, but if you are saying the ALUs share register > resource, then yes, you will need protection aginst same-reg writes, > - but you will need that anyway, for normal operation ? > ie a NOP should usually be a simpler, special case subset of normal > operations ?. I am talking about the backend, the problem I have is quite simple. I have 2 execution units for arithmetic and logic, 1 memory access unit (Load/Store) and a mutliply unit. Obviously all of these 4 Units would like to write data at some point to the registers. So when i only have two write ports to the register file, then I have a problem if all 4 Units wanna write data into my regfile, right? So I wonder how this is actually relised in a RISC architecture when there are more units to write to the regfile than I have writeports available. Do I use some kind of mux and control signals to forward the data that should be finally written? Or do I use a resolved input signal and this is driven by exactly one out? Hope its clearer now PatrickArticle: 117397
On Mar 29, 5:51 pm, Jim Lewis <j...@synthworks.com> wrote: > Hi, > The VHDL standards community needs feedback from VHDL users. > > Currently the Accellera VHDL TSC is working on enhancements > to add classes/OO, Randomization constructs, and Functional > Coverage with a goal of giving VHDL the same verification > capability as SystemVerilog or E. > > One of the VHDL simulation vendors has indicated that they > only want to implement new features if the user community > wants these features. > > The questions come down to: > Do you want these features added to VHDL? > Do you want to VHDL to be capable of handling all of your > testbench needs? > > This work is work in progress and below is the current status. > Keep in mind too that your interest/support of this work will > help raise the focus and inspiration of those doing the work. > > Classes / OO: > Peter Ashenden submitted a class proposal last year and > provided updates to it this year at DVCon. Currently > he plans on finishing an updated draft soon. > > Randomization: > I just submitted the first draft of the randomization proposal. > > Functional Coverage: > I have started working on this - anyone else who is interested > is welcome to contribute as much as they would like. > > With a focused effort, like the one to finish the Accellera 3.0 > draft of the standard, I think we can be done with these by > September. > > Although some have expressed doubt, it is clear that vendors > will do what their user community asks them to do - otherwise, > someone else will and, as a result, will earn your business. > > You can post here, send your reply to me (let me know if I can use > either your name and/or company name when I tally the results > for the Accellera VHDL TSC), or join the Accellera VHDL TSC > (which you can do as a non-Accellera member by registering) > and post your reply there. > > Thanks, > Jim Lewis > VHDL Evangelist > SynthWorks VHDL Training I have been a long time for Classes/OO, Randomization and Functional coverage that is already part of SystemVerilog. VHDL is my favorite HDL and I think it has always had very high-level constructs ahead of its time. The VHDL-2006 is a much needed update, but still comes short of the features that SystemVerilog boasts for verification. I think Classes/OO is great for synthesis as well and brings the language to higher abstraction level that is already enjoyed by software developers. It is a shame that (big) vendors are pushing SystemVerilog and think that there is not enough customer base for VHDL. I beg to differ and have be anxiously waiting for VHDL update and OO, verification extensions. I do not want to start language wars, but take a good look at table on page () of the following article and you would agree that VHDL has been at higher-level of abstraction than Verilog. http://www.edn.com/contents/images/376625t1.pdf Verilog is still good for gate-level descriptions and with Verilog 2001 extensions they brought it up to par with VHDL, and then SystemVerilog extensions added more features to get market share from Verisity and E supporters by pushing a supposedly standard driven language. Although we all know the big vendor influence. I hope these proposed features and the good works of Peter, Jim and other drivers of this great language is not taken for granted. -- AmalArticle: 117398
On Mar 29, 6:08 pm, "morpheus" <saurs...@gmail.com> wrote: > Hey John, > I have centered the signal between DC and fs/2. My problem is that > even though the I and Q channels are getting mixed correctly (verified > by offsetting the carrier frequency and watching the modulation move > by the offset value around DC on a spectrum analyzer), the demod is > not working, sq(I) + sq(Q) seems like a dead output....i checked the > synthesis report and post P&R simulation and it seems to be working in > simulation. > Bizarro!!! > -M When I say its "working" in simulation, I mean that through LabView I generated a FM modulated signal sampled at 50MSPS (same as my system) and used that as the input test vector to my design. I am doing functional verification using ModelSim and I can see that I*I + Q*Q outputs being computed, but they don't seem to be present in hardware. I am thinking there is something weird going on system wise that is leading to this anomaly, maybo some harmonics that are leading to cancellations or something, because I just cannot understand why the I*I multipliers are not workingArticle: 117399
Hi Jim, On 29 Mrz., 23:51, Jim Lewis <j...@synthworks.com> wrote: > The VHDL standards community needs feedback from VHDL users. > > Currently the Accellera VHDL TSC is working on enhancements > to add classes/OO, Randomization constructs, and Functional > Coverage with a goal of giving VHDL the same verification > capability as SystemVerilog or E. > > One of the VHDL simulation vendors has indicated that they > only want to implement new features if the user community > wants these features. And I guess mti won't support these features with Modelsim, to force Questa sells, like it is with SV. This might be a major issue when it comes to market usage. > The questions come down to: > Do you want these features added to VHDL? Don't know if OO-update is a good idea to a language, but we will see. C++ is not the best idea for OO IMHO because it relays to much on procedural statements. VHDL has no choice, when it comes to procedural statements. But I would realy appreciate, if vdhl would support built-in "modern" assertions like PSL or e. > Do you want to VHDL to be capable of handling all of your > testbench needs? Yes I like VHDL to be enhanced for tomorrows tb needs. I am currently working on a design, with included ADC. I have the netlist with ADC as blackbox for some purpose, the netlist with behavioral model for other purpose. In some cases I need to use another library element for a digital gate, than normal. Netlist and and one testbench are verilog and it is a pain to select the corresponding tb-gtl-library settings without configurations(is no porblem using configurations). bye Thomas
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