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On 2 Mai, 11:04, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-05-02, Antti <Antti.Luk...@xilant.com> wrote: > > > But, Impact is meant to be used to configure FPGA's, > > not to use "File Exit"... because its all that works. > > > What todo? Wait SP4? Or maybe there is a secret tactical patch > > available? > > Or some you-dont-find-it-when-you-do-not-know-the-exact-number AR? > > Have you tried to use it in batch mode? If all you need it for > is to configure FPGA:s that should be enough. (Assuming the bugs > are GUI related.) > > Cheat sheet after impact is started using -batch: (included > because I spent a lot of time yesterday using impact in > batch mode and happened to remember the necessary commands :)) > > setmode -bs > setcable -port auto > identify > assignfile -p 3 "foo.bit" > program -p 3 > > Where 3 is the position in the jtag chain of the device you are > programming. > > /Andreas Hi Andreas, thanks for suggestion - with the 100% SAME EXACT setup impact 8.2 works. so its just a fresh 9.1 bug. i have also been able to get impact 9.1 working, the issue is somehow related (again!) to configuration modes.. :( So 9.1 can be made to succeed also, whereis 8.2 always works. Antti PS its funny to see that impact 9.1 still crashes when the autogenerated bdsl file name is set to "bypass", I would have thought things like that are long time ago fixed, but no, they are not.Article: 118701
jasen wrote:
> CBFalconer <cbfalconer@yahoo.com> wrote:
>> petrus bitbyter wrote:
>>>
>> ... snip ...
>>>
>>> | | | v
>>> .------. | | .------.
>>> | | | +-------| |
>>> | 111 | | | 011 |
>>> | | | | |
>>> '------' 1| '------'
>>> ^ | | |
>>> | | v |
>>> 0| |1 .------. |1
>>> | +-------->| | |
>>> | | 110 |<------+
>>> +------------| 010 |
>>> '------'
>>> | ^
>>> 1| |
>>> +--+
>>
>> Obviously wrong.
>
> what's wrong with it?
>
> the labels on the states seem odd, but if you do this:
I looked at the labels. The 111 state can only be reached by
inputting a 0, for example.
--
<http://www.cs.auckland.ac.nz/~pgut001/pubs/vista_cost.txt>
<http://www.securityfocus.com/columnists/423>
<http://www.aaxnet.com/editor/edit043.html>
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Article: 118702
Keith Thompson wrote:
> CBFalconer <cbfalconer@yahoo.com> writes:
>> Keith Thompson wrote:
>>>
>>> So repeated requests to redirect this discussion away from
>>> comp.lang.c, where it's completely off-topic, have not worked.
>>> Does anybody have any suggestions for what *would* work?
>>
>> Set follow-ups.
>
> I did, but it didn't do any good. I could only set followups in
> my own followup; other direct replies to the original message
> retained the full cross-posting.
Your follow-up setting didn't make it to here. Did mine make it to
you? I suspect your reader.
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<http://kadaitcha.cx/vista/dogsbreakfast/index.html>
cbfalconer at maineline dot net
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Posted via a free Usenet account from http://www.teranews.com
Article: 118703On May 2, 5:45 am, Johannes Hausensteiner <johannes.hausenstei...@pcl.at> wrote: > I have a state machine design with big case statments (VHDL). When > I compile with Precision RTL it infers block ROM, which exceeds the > actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10 > chip. How can I tell Precision not to infer ROM but implement in > logic? > > Thanks, > > Johannes According to the manual you can use the "fsm_implementation" attribute to force state machine logic to infer a RAM, however it says that otherwise the FSM will encode using the "default FSM implementation for the target device", which seems to be RAM already in your case. I don't suppose you could break the case statement into smaller cases, perhaps by adding a pipeline delay? Good luck, Gabor By the way, Lattice ISE also comes with Synplify for synthesis, maybe you could get that working better?Article: 118704
On May 2, 5:15 am, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > comp.arch.fpga wrote: > > > What do you need the per pin configuration for? The pullups are > > > extremely > > week. (5uA to 200uA for Virtex-4). I can't imagine a digital > > application that > > will be disturbed by that. > > The board uses a with a Spartan-3E. The data sheet suggest the pull down > is 34K5 (Table 77 - ds312). I guess that's not too strong. > > However, I'd prefer the option to control the pull resistors on a > per-pin basis. It just seems to me a 'better' way of doing things. > > Thanks for the suggestions > Andy If you really want pullups or pulldowns and not to actively drive the pins, the tool chain will remove your instantiated pullups/pulldowns unless it determines the inputs to be used. However you can change the IOB parameters in the FPGA editor after you build the design. I haven't tried it myself, but there is a way to create a command file for the FPGA editor to make the same changes in a subsequent build. HTH, GaborArticle: 118705
Gabor wrote: > On May 2, 5:45 am, Johannes Hausensteiner > <johannes.hausenstei...@pcl.at> wrote: >> I have a state machine design with big case statments (VHDL). When >> I compile with Precision RTL it infers block ROM, which exceeds the >> actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10 >> chip. How can I tell Precision not to infer ROM but implement in >> logic? >> >> Thanks, >> >> Johannes > > > According to the manual you can use the "fsm_implementation" attribute > to > force state machine logic to infer a RAM, however it says that > otherwise > the FSM will encode using the "default FSM implementation for the > target > device", which seems to be RAM already in your case. I don't suppose > you could break the case statement into smaller cases, perhaps by > adding a pipeline delay? > > Good luck, > Gabor > > By the way, Lattice ISE also comes with Synplify for synthesis, maybe > you could get that working better? > Thanks for your answer. Maybe I can break the CASE statement, but this will certainly affect readability; so I am looking for a different solution. When reading the manuals (several PDFs, each hundreds of pages ...) I can only find how to specify that certain parts should be ROM (or RAM) blocks. When changing the logic, i.e. writing: attribute rom_block of <signal name> : signal is false; this does not help. I somewhere (in the manuals) read that the default size of a CASE statement to be implemented as ROM is 64, but not saying how to change that default. When compiling with Synplify this does not occur. But it seems that with the latest version of ispLEVER Starter only Precision is supplied. It is possible to seperately download and install Synplify, but you need an extra license. It looks to me as if they want to remove it completely in future versions. My project is a kind of development board for educational application, so I want to keep the environment simple. JohannesArticle: 118706
After giving up the search for Xilinx supplied MicroBlaze reference designs for Xilinx Spartan-3A kit, I made the reference design using BSB in EDK 9.1SP1. No problem encountered until the attempt to load the bitstream into Spartan-3A Bitstream download succeeded, Done also OK. Reading back JTAG Status from impact tells me EVERYTHING is OK! But... init LED is half-way dimmed and "AWAKE" LED is off, this behavior is the same no matter the "SUSPEND" input switch position. I have not enabled suspend in the design, so to my understanding the bitstream should come up alive? But it doesnt. Is Spartan-3A in some undocumented deep sleep mode? I was really hoping to see "Hello Spartan-3A" on the terminal, or at least the LEDs blinking. But all that happens is DONE=ON, AWAKE=OFF, INIT=30% dimmed. I will fight again tomorrow, maybe I get some bright how to wake up Spartan-3A when I sleep. AnttiArticle: 118707
look at this link : Board Verification Test Specification http://www.xilinx.com/products/boards/s3astarter/files/s3ask_test.zip (sdram directory) mig user guide, fig. 8-2 page 205 http://www.xilinx.com/support/software/memory/protected/migug.pdf I am new to design, particularly to memory interface ; but in my opinion, testbench generated by coregen mig 1.7 (vhdl_xst_bl8) should be a good starting point : of course, you have to hack vhdl_xst_bl8_ddr2_test_bench_0.vhd according your needs ... or do I miss something ? It is true it lacks some example with a soft processor (but not necessarily with microblaze / edk for those not using it ...) On May 2, 12:23 pm, Antti <Antti.Luk...@xilant.com> wrote: > On 2 Mai, 11:14, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > > > > > Antti wrote: > > > as of MicroBlaze reference designs - well USUALLY I would also just > > > make a new one, but in this case th=EDs is the VERY FIRST xilinx low > > > cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use > > > usually work. With DDR2 I have different experiences, its not always > > > working, it causes timing issues also on Virtex-5. Spartan-3A is way > > > slower than Virtex-5 so I really do not want to try the DDR2 EDK IP > > > core without the known working reference provided by Xilinx. > > > > This (and any other Microblaze ref design) is missing NOT AVAILABLE. > > > Sounds a reasonable expectation, no comment from anyone in Xilinx ? > > > It does suggest they have tried, and been unable to get this to > > actual work themselves ? > > > Do they have ANY DDR2 templates that allow a bandwidth/memory test ? > > > -jg > > Hi Jim, > > well, the only available DDR2 thingie is the default MIG coregen > autogenerated self checking test design, that should display fail-pass > on single user LED. > > the only thing what this thing is good, is to deliver a result: > "the DDR2 memory is not necessary fully dead"... for anything more > reliable evaluation the LED status is not good IMHO. > > this design does really not allow any "bandwidth" evaluation, and its > user interface is also awkward enough so that no-body wishes to mess > around with unless really forced to do that. The MIG core can not be > used without special statemachines in any design. > > As of do they have or not, well at X-Fest there was demo of some > display things, rotate the knob and look Xilinx logo to rotate, I > assume those demos use DDR2 memory (as it is the only external RAM on > this board). > > So I assume Xilinx _HAS_ useable demos and reference designs > demonstrating working DDR2 on Xilinx Spartan-3A kit. > The only issue is that NONE of those demos is currently available :( > > AnttiArticle: 118708
On 2 Mai, 15:38, rpons...@gmail.com wrote: > look at this link : > > Board Verification Test Specificationhttp://www.xilinx.com/products/boards/s3astarter/files/s3ask_test.zip > (sdram directory) > > mig user guide, fig. 8-2 page 205http://www.xilinx.com/support/software/memory/protected/migug.pdf > > I am new to design, particularly to memory interface ; but in my > opinion, testbench generated by coregen mig 1.7 (vhdl_xst_bl8) should > be a good starting point : of course, you have to hack > vhdl_xst_bl8_ddr2_test_bench_0.vhd according your needs ... or do I > miss something ? > > It is true it lacks some example with a soft processor (but not > necessarily with microblaze / edk for those not using it ...) > well I happen to disagree. I have used MIG and the generated testbench, and I can do it, if needed. But ONLY IF THAT IS LAST option. so far I was pretty calm about the DDR2 in Spartan-3A mainly as had seen the onsite demos with rotating bitmaps on the VGA display. I naturally assumed that those images come from DDR2 memory. But after looking at the PicoBlaze stuff I now understand that the VGA bitmap rotation demo was taking the Xilinx logo bitmap from NOR Flash and not from DDR2 memory. Hence there is no confirmation about the availability of MicroBlaze system with DDR2 (as the VGA demo was not using EDK) Oh, well maybe I am over-stressed, but I was hoping more to be honest. So far I am not able to even generate ANY bitstream for Spartan-3A that would get activated... only Xilinx supplied bitstreams start. Any bitstreams generated make the INIT LED dimmed and do not start :( AnttiArticle: 118709
In article <1178033628.894456.55660@p77g2000hsh.googlegroups.com>,
Quang Anh <nvqanh@gmail.com> wrote:
>> // Concise priority arbiter
>> input [26:0] req; // Bit zero is highest priority
>> wire [26:0] gnt = req & -req; // Isolate least significant set bit
>I'm so sorry that I can NOT understand your idea. Maybe, I should read
>the documents you recommend first. Anyway, it would be great for me if
>you spend your ttime explaining to me again.
Try an example: suppose (for 10 bits) req is 1101011000
The definition of '-' (2's complement negate) is to invert each bit and then
add 1, so lets see what happens:
Invert: 0010100111
Now if you AND this with req you'll get zero. But look at what happens when
you add 1: the carry propogates through all of the trailing ones until the
first zero is hit:
Negate: 0010100111 + 1 --> 0010101000
Now if you AND this with req you'll get: 0000001000
Bit 3 is the highest priority requester.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 118710Weng, 1. Learn spice 2. Use spice. Austin Weng Tianxiang wrote: > On May 2, 12:41 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: >> On 1 May 2007 18:50:32 -0700, >> >> Weng Tianxiang <wtx...@gmail.com> wrote: >>> Do you have any idea where I can get a graph of it? I just want the >>> graph showing the relationship between input and output. >> Why not simulate one in any of the free versions of SPICE? >> -- >> Jonathan Bromley, Consultant >> >> DOULOS - Developing Design Know-how >> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services >> >> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK >> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com >> >> The contents of this message may contain personal views which >> are not the views of Doulos Ltd., unless specifically stated. > > Hi Jonathan, > What I need is a graph of pass transistor's working curving that must > be available in some books or articles. I have no Spice experiences > and even don't know what proper parameters should be. > > Weng >Article: 118711
Martin, You must use 9.1 if you need V5. Austin martin+x@y.z wrote: > Starting a new design using both V2P and V5. I see with concern that > the latest Xilinx tools might have issues. We need to upgrade as the > candidate development machine is running 6.2-something (don't laugh, > it works fine and it hasn't broken any designs). > > What's the current recommendation? Can one even get a prior version > that doesn't have a personality? Time to talk to an FAE, I guess. > > -Martin >Article: 118712
Mehdi, DCI is a feedback system, so as long as it is running, it is tracking (correcting). The only time when you might reset the DCI block, would be if you don't like to see the DCI correction value noise (as the legs of the fine trims are switched in and out) and have selected to turn off the DCI tracking feedback. Generally speaking, a well designed interface should work even with a 2:1 mis-match (logic is only knowing the difference between a 1 and a 0 after all). Once the DCI has locked, changing temperature from -55C to +125C is not going to get even close to exceeding the 2:1 mis-match. AustinArticle: 118713
I understand that mig generated testbench is rather frustrating ; but that being said, my question remains : is that code (35 files, well documented, in verilog or vhdl) a good starting point for an implementation of a ddr2 controller, or not ? Is there a DDR2 better controller pattern somewhere ? and another question, why memory manufacturers (micron) didn't provide hdl wrappers for their components ?Article: 118714
Johannes Hausensteiner wrote: > I have a state machine design with big case statments (VHDL). When > I compile with Precision RTL it infers block ROM, which exceeds the > actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10 > chip. How can I tell Precision not to infer ROM but implement in > logic? > This how-to addresses this issue in Verilog, should be similar in VHDL. http://decass.dilloneng.com/documents/howto/ram_inference/ TomArticle: 118715
I'm a student in year one, and this is my first, more serious project, so bear with me. I've completed the schematics, and the timing simulations work fine too. Now, as the next step i would like to upload my design to a spartan 3 starter board, but don't know how to do it. I've connected the boar to my pc with the JTAG3 cable, but nothing happens. Shouldn't i get a "found new hardware" dialog box, or something similar? And how can i upload the bitfile generated by the "implementation" step? And how do i name my input/output pins in the design? Sorry for all these "newbie" questions, but i have to complete this project in about one week, and don't know where else i could get an answer...Article: 118716
Ok, so you made the circuit, simulations and ervything checked out - great! > I've completed the schematics, and the timing simulations work fine > too. Now, as the next step i would like to upload my design to a > spartan 3 starter board, but don't know how to do it. Indeed - you need to go a little further in the software domain to get things going. Firstly synthesise your design. You'll need a .ucf file to tell the software which pin on your Spartan 3 board matches what in your VHDL. You'll also need to specify a global clock frequency to have some basic timing analysis. At the end of this you should have a .bit file or something similar... (I can't remember what foundation 3.x had for file names) > I've connected > the boar to my pc with the JTAG3 cable, but nothing happens. Shouldn't > i get a "found new hardware" dialog box, or something similar? Ok, the PIII cable is parallel (I think), so no fancy USB auto-recognise function, you have to do things the old way - I think 3.x had "Impact"... Which is used to program devices. Can you check that you have that? You'll also need to explain to us whether your board has a PROM? I'm sure it must, you;ll have to look for its name and type... BenArticle: 118717
in "Processes" Tab Generate programing file |--- Configure device (iMPACT) On May 2, 4:53 pm, "Benjamin Todd" <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > Ok, so you made the circuit, simulations and ervything checked out - great! > > > I've completed the schematics, and the timing simulations work fine > > too. Now, as the next step i would like to upload my design to a > > spartan 3 starter board, but don't know how to do it. > > Indeed - you need to go a little further in the software domain to get > things going. Firstly synthesise your design. You'll need a .ucf file to > tell the software which pin on your Spartan 3 board matches what in your > VHDL. You'll also need to specify a global clock frequency to have some > basic timing analysis. > > At the end of this you should have a .bit file or something similar... (I > can't remember what foundation 3.x had for file names) > > > I've connected > > the boar to my pc with the JTAG3 cable, but nothing happens. Shouldn't > > i get a "found new hardware" dialog box, or something similar? > > Ok, the PIII cable is parallel (I think), so no fancy USB auto-recognise > function, you have to do things the old way - I think 3.x had "Impact"... > Which is used to program devices. > > Can you check that you have that? > > You'll also need to explain to us whether your board has a PROM? I'm sure it > must, you;ll have to look for its name and type... > > BenArticle: 118718
Benjamin Todd wrote: > Ok, so you made the circuit, simulations and ervything checked out - great! > >> I've completed the schematics, and the timing simulations work fine >> too. Now, as the next step i would like to upload my design to a >> spartan 3 starter board, but don't know how to do it. > > Indeed - you need to go a little further in the software domain to get > things going. Firstly synthesise your design. You'll need a .ucf file to > tell the software which pin on your Spartan 3 board matches what in your > VHDL. You'll also need to specify a global clock frequency to have some > basic timing analysis. Does ISE3.1i even support Spartan3-devices?? I think he needs to upgrade his ISE installation before anything else... -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 118719
Tom Dillon wrote: > Johannes Hausensteiner wrote: >> I have a state machine design with big case statments (VHDL). When >> I compile with Precision RTL it infers block ROM, which exceeds the >> actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10 >> chip. How can I tell Precision not to infer ROM but implement in >> logic? >> > > This how-to addresses this issue in Verilog, should be similar in > VHDL. > > http://decass.dilloneng.com/documents/howto/ram_inference/ > > Tom > Thanks for the link, but I ended up with the same code as given in the Precision user manual, which I tried before and which does not what I want. I think this article focuses on block RAM vs. distributed RAM. I want Precision to implement no RAM at all but normal logic (LUTs). JohannesArticle: 118720
On May 2, 5:53 pm, "Benjamin Todd" <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > Ok, so you made the circuit, simulations and ervything checked out - great! > > Indeed - you need to go a little further in the software domain to get > things going. Firstly synthesise your design. You'll need a .ucf file to > tell the software which pin on your Spartan 3 board matches what in your > VHDL. You'll also need to specify a global clock frequency to have some > basic timing analysis. I've used the schematic editor to implement my design, so no VHDL. The global clock for the project would be 50MHz. I've placed IPAD/OPAD connectors(?) but i don't know how to calibrate them. > At the end of this you should have a .bit file or something similar... (I > can't remember what foundation 3.x had for file names) I do end up with a .bit file after implementation. > Ok, the PIII cable is parallel (I think), so no fancy USB auto-recognise > function, you have to do things the old way - I think 3.x had "Impact"... > Which is used to program devices. I've looked at the Xilinx program group, but i have no Impact. For device programming i only have JTAG Programmer, Hardware debugger and PROM file formatter (non of them can detect my board) And my cable is serial. > You'll also need to explain to us whether your board has a PROM? I'm sure it > must, you;ll have to look for its name and type... Found this page with a nice photo and more details about my board: http://www.cs.colostate.edu/~cs460/spartan3.html "Xilinx XCF02S 2Mbit Configuration PROM Programs FPGA at power on or PROG button". I've also downloaded the newest ISE web pack, but i'm not sure if i'll install it for this project.Article: 118721
"Johannes Hausensteiner" <johannes.hausensteiner@pcl.at> wrote in message news:1178119117.891772@news.aic.at... > Tom Dillon wrote: >> Johannes Hausensteiner wrote: >>> I have a state machine design with big case statments (VHDL). When >>> I compile with Precision RTL it infers block ROM, which exceeds the >>> actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10 >>> chip. How can I tell Precision not to infer ROM but implement in >>> logic? >>> >> >> This how-to addresses this issue in Verilog, should be similar in >> VHDL. >> >> http://decass.dilloneng.com/documents/howto/ram_inference/ >> >> Tom >> > > Thanks for the link, but I ended up with the same code as given in the > Precision user manual, which I tried before and which does not what I > want. I think this article focuses on block RAM vs. distributed RAM. I > want Precision to implement no RAM at all but normal logic (LUTs). > > Johannes Hi Johannes, Have a look at the use_resource attribute, this might enable you to force Precision into using LUTs, alternatively, sign up for the beta release which has a very nice graphical resource manager. Just select the instance, click on the pulldown button and change the ram to LUTs. Hans www.ht-lab.comArticle: 118722
Hi Lecroy, I had a similar thing happen to me, although not related to an "immediate stop". I tried to restore the project from the backup, and it appeared to be broken, too -- just like you observe. The same backup restored fine on a different workstation, so the fault was not in the project folder but rather in some ISE cache. The solution was to do the following: - delete c:\documents and settings\Admin\Temp\* - restore the project from the backup - touch -m * in the top folder and the vhdl folder of the project - open the project in ISE, clean it, and close it - touch -m * again If the backup is dated, you should replace the restored sources with the latest copy right before doing the last step of the procedure. I found this out the hard way (took me almost a whole day). May it help you (and others). Kind regards, MarcArticle: 118723
On May 2, 11:11 am, Misi <tizenha...@gmail.com> wrote: > On May 2, 5:53 pm, "Benjamin Todd" > > <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > > Ok, so you made the circuit, simulations and ervything checked out - great! > > > Indeed - you need to go a little further in the software domain to get > > things going. Firstly synthesise your design. You'll need a .ucf file to > > tell the software which pin on your Spartan 3 board matches what in your > > VHDL. You'll also need to specify a global clock frequency to have some > > basic timing analysis. > > I've used the schematic editor to implement my design, so no VHDL. > The global clock for the project would be 50MHz. > I've placed IPAD/OPAD connectors(?) but i don't know how to calibrate > them. > > > At the end of this you should have a .bit file or something similar... (I > > can't remember what foundation 3.x had for file names) > > I do end up with a .bit file after implementation. > > > Ok, the PIII cable is parallel (I think), so no fancy USB auto-recognise > > function, you have to do things the old way - I think 3.x had "Impact"... > > Which is used to program devices. > > I've looked at the Xilinx program group, but i have no Impact. For > device programming > i only have JTAG Programmer, Hardware debugger and PROM file formatter > (non of them > can detect my board) > > And my cable is serial. > > > You'll also need to explain to us whether your board has a PROM? I'm sure it > > must, you;ll have to look for its name and type... > > Found this page with a nice photo and more details about my board:http://www.cs.colostate.edu/~cs460/spartan3.html > "Xilinx XCF02S 2Mbit Configuration PROM Programs FPGA at power on or > PROG button". > > I've also downloaded the newest ISE web pack, but i'm not sure if i'll > install it for this project. I found Digilent's web page for your board @ http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmabl >From there, you can get a PDF manual, plus the "code" that Digilent used for testing the board. Programming the board's FPGA/ configuration PROM requires a Parallel-3 cable, which only works with a parallel port on your PC. A serial port won't work! HTH -Dave Pollum (not affiliated with Digilent)Article: 118724
Misi, You have multiple problems. The first is what Sean mentioned earlier, ISE 3.1i does not support S3 devices. This tool version is going to be completely useless to you for any current Xilinx FPGA family. So your on the right track getting WebPACK. I have not checked you device specifically, but it will only support lower densities. Here is problem number two. You can not import your ISE 3.1i schematic into the WebPACK version you are now using (technically there is a way, but not worth the effort). You will have to either start a new schematic again or (better) use HDL. Once you have the project implemented and a bitfile generated, you can use iMPACT to program (iMPACT did not exist in ISE 3.1i). A good bit of advice: download the ISE tutorial and go through it. You will learn the tool flow and be much better prepared to start you own project. -David "Misi" <tizenharom@gmail.com> wrote in message news:1178122319.726994.73320@e65g2000hsc.googlegroups.com... > On May 2, 5:53 pm, "Benjamin Todd" > <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: >> Ok, so you made the circuit, simulations and ervything checked out - >> great! >> >> Indeed - you need to go a little further in the software domain to get >> things going. Firstly synthesise your design. You'll need a .ucf file >> to >> tell the software which pin on your Spartan 3 board matches what in your >> VHDL. You'll also need to specify a global clock frequency to have some >> basic timing analysis. > > I've used the schematic editor to implement my design, so no VHDL. > The global clock for the project would be 50MHz. > I've placed IPAD/OPAD connectors(?) but i don't know how to calibrate > them. > >> At the end of this you should have a .bit file or something similar... (I >> can't remember what foundation 3.x had for file names) > > I do end up with a .bit file after implementation. > >> Ok, the PIII cable is parallel (I think), so no fancy USB auto-recognise >> function, you have to do things the old way - I think 3.x had "Impact"... >> Which is used to program devices. > > I've looked at the Xilinx program group, but i have no Impact. For > device programming > i only have JTAG Programmer, Hardware debugger and PROM file formatter > (non of them > can detect my board) > > And my cable is serial. > >> You'll also need to explain to us whether your board has a PROM? I'm sure >> it >> must, you;ll have to look for its name and type... > > Found this page with a nice photo and more details about my board: > http://www.cs.colostate.edu/~cs460/spartan3.html > "Xilinx XCF02S 2Mbit Configuration PROM Programs FPGA at power on or > PROG button". > > I've also downloaded the newest ISE web pack, but i'm not sure if i'll > install it for this project. > > >
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