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Messages from 118725

Article: 118725
Subject: Re: My Dear Spartan-3A, Please Please WAKE UP! SUCCESS!!
From: Antti <Antti.Lukats@xilant.com>
Date: 2 May 2007 10:16:28 -0700
Links: << >>  << T >>  << A >>
Antti schrieb:
> After giving up the search for Xilinx supplied MicroBlaze reference
> designs for Xilinx Spartan-3A kit, I made the reference design using
> BSB in EDK 9.1SP1.
>
> No problem encountered until the attempt to load the bitstream into
> Spartan-3A
>
> Bitstream download succeeded, Done also OK.
> Reading back JTAG Status from impact tells me EVERYTHING is OK!
>
> But... init LED is half-way dimmed and "AWAKE" LED is off, this

another PC, ISE 9.1 (no service pack)

Spartan-3A is working, INIT is not dimmed (OFF)

it is possible that with 9.1SP3 the FPGA also was actually configured
ok
(just the microblaze system das 100% dead), - I was irritated by the
half-way
lit INIT LED so I assumed FPGA is either misconfured or in some sleep
state.

sorry for the confusion.

Antti


Article: 118726
Subject: Re: Read 64-bit value over PLB
From: jetmarc@hotmail.com
Date: 2 May 2007 10:28:57 -0700
Links: << >>  << T >>  << A >>
Hi Manny,

Others have pointed out already that you can either have each 32bit
word read separately, or you can have the PPC do a line read.

A line read means that 256 bits are read, although you will use only
64 of them.  If the PLB slave returns "target word first", this will
be a low-latency read.  Total bandwidth may be sub-optimal though,
when you repeatedly discard 3/4 of the data.

Doing two 32-bit transactions (mark memory as non-cachable, possibly
guarded, and disable LWL) might be faster in some special scenarios,
depending on the slave behaviour.

Regards,
Marc


Article: 118727
Subject: Re: Xilinx software quality - how low can it go ?!
From: dalai lamah <antonio12358@hotmail.com>
Date: Wed, 02 May 2007 17:44:36 GMT
Links: << >>  << T >>  << A >>
Un bel giorno Antti digitÚ:

> I really dont understand why Xilinx isnt hiring people who can develop
> and test software?
> Is the world-wide shortage of engineers really that bad?

Actually some bugs and missing features - especially in the user interface
- are quite funny, for example the editor that hangs forever if you try to
use the dead keys (i.e. http://en.wikipedia.org/wiki/Dead_key ). Or is it
just me?

-- 
emboliaschizoide.splinder.com

Article: 118728
Subject: Re: ISE 8.2 Strange cache problem? Warning...
From: "lecroy7200@chek.com" <lecroy7200@chek.com>
Date: 2 May 2007 11:22:29 -0700
Links: << >>  << T >>  << A >>
I think your right.  On Windows 2000, in the \documents and settings
\MYUSERNAME.DOMAIN\Local Settings\Temp   there are several Xilinx temp
files.   Thanks for posting!


Article: 118729
Subject: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
From: Paul <pauljbennett@gmail.com>
Date: 2 May 2007 11:36:09 -0700
Links: << >>  << T >>  << A >>
As a Recent student myself who has used this starter kit:

*The webpack editions of ISE do indeed support the xc3s200 part
*The parallel port JTAG cable that somes with that starter kit (it's
serial
on the JTAG end, as opposed to the cabler xilinx refers to as the
parallel IV
cable but plugs into the parallel port of your PC) does indeed
work with that kit, and the version of IMPACT included with any fairly
recent
webpack edition of ISE.  I assumet his is actually the cable you have,
since it's
definately what comes in the box with that starter kit.
*Never did schematic entry, so i can't speak to the version 3.1
portability
to the newer version of ISE - sorry



On May 2, 10:43 am, Misi <tizenha...@gmail.com> wrote:
> I'm a student in year one, and this is my first, more serious project,
> so bear with me.
>
> I've completed the schematics, and the timing simulations work fine
> too. Now, as the next step i would like to upload my design to a
> spartan 3 starter board, but don't know how to do it. I've connected
> the boar to my pc with the JTAG3 cable, but nothing happens. Shouldn't
> i get a "found new hardware" dialog box, or something similar? And how
> can i upload the bitfile generated by the "implementation" step? And
> how do i name my input/output pins in the design?
>
> Sorry for all these "newbie" questions, but i have to complete this
> project in about one week, and don't know where else i could get an
> answer...



Article: 118730
Subject: Re: Area constraint - trust Low Level Synthesis?
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 02 May 2007 14:56:37 -0400
Links: << >>  << T >>  << A >>
Borge wrote:
> My FPGA is getting a bit crowded. I have a huge distributed FIR in my
> Spartan3/400. When synthesising the design I get conflicting (?) area
> constraint messages from Low Level Synthesis and Final Report.
> 
> In the first message it looks like my desing doesn't fit, but in the
> second one it looks OK. Which report should I trust? The part that
> says I'm using 123% of 3584 slices or the one that says I'm using 3366
> of 3584?
> 
> The design seems to be working just fine when doing a functional test.
> But it's a tough job to verify a huge FIR filter and attached
> dithering.
> 
> Thanks for your help interpreting this stuff!

There are three reports that give resource utilization figures:
- Synthesis: basically a first-order approximation of your design's 
resource usage after your HDL has been translated to RTL netlists with some 
blocks expanded/merged/etc. by optimizations
- Map: a second-order approximation after translating the RTL into actual 
device primitives, it should not be dramatically different from synthesis 
results
- PAR: the final (and exact) resource usage for the finished implementation

Since PAR may duplicate logic and do other things depending on enabled 
optimization options, the PAR results can be significantly different from 
synthesis/map... for me, this has almost always been less than 10% but I 
have seen results be off by over 20% a few times.

Article: 118731
Subject: Re: debounce state diagram FSM
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 02 May 2007 12:01:52 -0700
Links: << >>  << T >>  << A >>
On Wed, 02 May 2007 08:07:06 +0100, Flash Gordon
<spam@flash-gordon.me.uk> wrote:

>John Larkin wrote, On 02/05/07 01:51:
>> On Tue, 01 May 2007 17:29:11 -0700, Keith Thompson <kst-u@mib.org>
>> wrote:
>> 
>>> So repeated requests to redirect this discussion away from
>>> comp.lang.c, where it's completely off-topic, have not worked.  Does
>>> anybody have any suggestions for what *would* work?
>> 
>> Programming embedded systems, things that interface to the real world,
>> are off-topic to c programmers? Why am I not surprised?
>
>I gave the best C answer, which was that it is better solved in HW.

But hardware costs money on a production basis, and code is free. So
"better solved in hardware" translates to "I'm only interested in
programming, so don't annoy me with applications."

> I 
>also stated that I have done debounce in SW, but I did not get any 
>response asking how, so obviously everyone agreed that implementing it 
>in HW was better.
>

If it's a pure bounce problem, just check the switch state 10 times a
second and use what you see... no debounce needed.

John


Article: 118732
Subject: Re: debounce state diagram FSM
From: Flash Gordon <spam@flash-gordon.me.uk>
Date: Wed, 02 May 2007 21:12:31 +0100
Links: << >>  << T >>  << A >>
John Larkin wrote, On 02/05/07 20:01:
> On Wed, 02 May 2007 08:07:06 +0100, Flash Gordon
> <spam@flash-gordon.me.uk> wrote:
> 
>> John Larkin wrote, On 02/05/07 01:51:
>>> On Tue, 01 May 2007 17:29:11 -0700, Keith Thompson <kst-u@mib.org>
>>> wrote:
>>>
>>>> So repeated requests to redirect this discussion away from
>>>> comp.lang.c, where it's completely off-topic, have not worked.  Does
>>>> anybody have any suggestions for what *would* work?
>>> Programming embedded systems, things that interface to the real world,
>>> are off-topic to c programmers? Why am I not surprised?
>> I gave the best C answer, which was that it is better solved in HW.
> 
> But hardware costs money on a production basis, and code is free. So
> "better solved in hardware" translates to "I'm only interested in
> programming, so don't annoy me with applications."

No, it translates to use the correct tool for the job. This is why 
keyboard controllers do the debounce on keyboards rather than leaving it 
to the OS.

>> I 
>> also stated that I have done debounce in SW, but I did not get any 
>> response asking how, so obviously everyone agreed that implementing it 
>> in HW was better.
> 
> If it's a pure bounce problem, just check the switch state 10 times a
> second and use what you see... no debounce needed.

Having been this route more than once because it was a one-off and 
already built, I can tell you that SW solutions do not work as well as 
properly designed HW when the SW has other things to do, one reason 
being that the HW can sample the data much faster.

Since the OP still has not commented on the possibility of a C solution 
it still seems likely that is not what the OP actually wants.
-- 
Flash Gordon

Article: 118733
Subject: Re: debounce state diagram FSM - topical
From: Jim Lewis <jim@synthworks.com>
Date: Wed, 02 May 2007 13:24:58 -0700
Links: << >>  << T >>  << A >>
Keith,
A few minutes of breathing, adopting a forgiving attitude,
and forgoing the concerned posts about the cross-posting
would reduce the net traffic by 30% (accurate yesterday -
includes replies - probably increased today).

Of course it would be nice if people did not cross-post
potentially irrelevant topics (which this may or may not
be), however, if you have a threaded news reader, close
the thread and the clutter is gone.

It seems to me that the only difference it makes is to
the people who are following the thread.  I have to flip
through the posts without content (your complaints).

Regards,
Jim


Article: 118734
Subject: Re: switched to xcf32p prom and now doesn't run
From: "cpope" <cepope@nc.rr.com>
Date: Wed, 2 May 2007 16:57:15 -0400
Links: << >>  << T >>  << A >>
Turns out I had to change the bitgen option to drive the done pin. Must have
been marginal or the pull up strength is different between the xcf08p and
xcf32p proms. Mystery solved. -Clark

"cpope" <cepope@nc.rr.com> wrote in message news:...
> I have a new board where I switched from the xcf08p to the xcf32p serial
> prom devices. The 32p programs fine and when I cycle power the current
jumps
> up and my test led lights which should mean that the fpga is configured.
> However, the PPC in the v4fx12 device is dead or not running. Running XMD
> returns all zeros for the processor ID and  I get no output from my
> bootloader code.
>
> Downloading the fpga manually works fine.
>
> One other difference is that I'm using the revision select lines on the
32p
> where I didn't on the 08p but the lines are both set correctly and it does
> appear that the fpga loads but then freezes. Any ideas what might cause
> this?
>
> Thanks,
> Clark
>
>



Article: 118735
Subject: Re: debounce state diagram FSM - topical
From: Flash Gordon <spam@flash-gordon.me.uk>
Date: Wed, 02 May 2007 22:59:08 +0100
Links: << >>  << T >>  << A >>
Jim Lewis wrote, On 02/05/07 21:24:
> Keith,
> A few minutes of breathing, adopting a forgiving attitude,
> and forgoing the concerned posts about the cross-posting
> would reduce the net traffic by 30% (accurate yesterday -
> includes replies - probably increased today).

A little consideration by those continuing to cross-post after it has 
been pointed out would reduce traffic more. After al, the requests were 
polite.

> Of course it would be nice if people did not cross-post
> potentially irrelevant topics (which this may or may not
> be),

Since no one from comp.lang.c has come in to say it is topical on 
comp.lang.c and the thread has so far had one post with C in it, from 
someone saying basically "you are complaining so here is some C" I think 
it is fairly conclusive.

 > however, if you have a threaded news reader, close
> the thread and the clutter is gone.

The additional time downloading is not, and some people are still on 
slow dial-up *and* paying per minute. Also, if it is OK for one it is OK 
for all, so we get loads more off topic cross-posting and matters become 
worse.

> It seems to me that the only difference it makes is to
> the people who are following the thread.  I have to flip
> through the posts without content (your complaints).

If people would stop the cross-posts when it was pointed out that would 
be one or two posts not lots. Therefore, the thing that will reduce it 
most is if people stop inappropriate cross-posts when it is pointed out.

Why do you think it reasonable for us to have to put up with 
inappropriate cross-posts and not for you to put up with polite requests 
to stop the cross-posts?
-- 
Flash Gordon

Article: 118736
Subject: Re: debounce state diagram FSM - topical
From: "Default User" <defaultuserbr@yahoo.com>
Date: 2 May 2007 21:59:58 GMT
Links: << >>  << T >>  << A >>
Jim Lewis wrote:


> Of course it would be nice if people did not cross-post
> potentially irrelevant topics (which this may or may not
> be), however, if you have a threaded news reader, close
> the thread and the clutter is gone.

While I'm not Keith, I'll say I can't agree with your position. The
best way to keep a newsgroup clear of clutter is to speak up when
off-topic stuff appears, not just ignore it.

That's a fairly typical reaction here in comp.lang.c. Those who don't
like it should refrain from posting off-topic messages here. The easy
way to avoid that in this thread is start removing clc from the
newsgroup list. By now, most people should have seen the complaints,
and really have very little excuse.

The original message was off-topic, and the vast majority of follow-ups
have been off-topic. There's very little question about that.




Brian

From rich@example.net Wed May 02 15:30:44 2007
Path: newssvr14.news.prodigy.net!newsdbm05.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!trnddc03.POSTED!dd653b87!not-for-mail
From: Rich Grise <rich@example.net>
Subject: Re: debounce state diagram FSM
User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table)
Message-Id: <pan.2007.05.02.23.31.21.488273@example.net>
Newsgroups: comp.lang.vhdl,comp.arch.fpga,sci.electronics.design,comp.lang.c,comp.lang.verilog
References: <1177871564.475673.53180@y80g2000hsf.googlegroups.com> <1178058355.292440.275760@l77g2000hsb.googlegroups.com> <ln647c5aqw.fsf@nuthaus.mib.org> <r2of33htqqttg5d9gmiqcnesfvo0kodcp0@4ax.com> <lnvefc3qst.fsf@nuthaus.mib.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
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Date: Wed, 02 May 2007 22:30:44 GMT
NNTP-Posting-Host: 71.103.107.248
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X-Trace: trnddc03 1178145044 71.103.107.248 (Wed, 02 May 2007 18:30:44 EDT)
NNTP-Posting-Date: Wed, 02 May 2007 18:30:44 EDT
Xref: prodigy.net comp.lang.vhdl:69921 comp.arch.fpga:130412 sci.electronics.design:802461 comp.lang.c:823751 comp.lang.verilog:36024

On Tue, 01 May 2007 19:25:22 -0700, Keith Thompson wrote:
> John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> writes:
>> On Tue, 01 May 2007 17:29:11 -0700, Keith Thompson <kst-u@mib.org>
>>
>>>So repeated requests to redirect this discussion away from
>>>comp.lang.c, where it's completely off-topic, have not worked.  Does
>>>anybody have any suggestions for what *would* work?
>>
>> Programming embedded systems, things that interface to the real world,
>> are off-topic to c programmers? Why am I not surprised?
> 
> Questions which have nothing to do with programming in C are off-topic
> in comp.lang.c.  (If the original poster had asked for a C solution,
> it might have been different, but I don't think I've seen a single
> line of C source code in this thread.)
> 
> I'm getting the impression that once someone posts an inappropriately
> cross-posted discussion, there's just no way to keep it from
> continuing on all the newsgroups to which it was originally posted,
> because most people posting followups just don't pay attention to the
> Newsgroups: header.  Oh, well.

Well, you could have removed comp.lang.c from your own followups, rather
than perpetuating it. After all, you only want to bitch at the people in
the other groups, right?

And you _do_ know how to set "followups-to", don't you?

I envision a squad of about a half-dozen people, back-to-back-to-back, etc.,
trying to fend off the onslaught of C++, perl, assembler, etc, etc,
etc...

Good Luck!
Rich


Article: 118737
Subject: Re: debounce state diagram FSM
From: "Default User" <defaultuserbr@yahoo.com>
Date: 2 May 2007 22:40:10 GMT
Links: << >>  << T >>  << A >>
Rich Grise wrote:


> Well, you could have removed comp.lang.c from your own followups,
> rather than perpetuating it. After all, you only want to bitch at the
> people in the other groups, right?
> 
> And you do know how to set "followups-to", don't you?

People keep saying this like it's some sort of magic. All that does
direct replies to THAT message to certain groups. It has jack to do
with the thread.

It's also the case that topicality IS on-topic in comp.lang.c, as in
all groups, so there's really no need to set follow-ups in those cases.
In fact, I'd argue that it's the wrong thing to do.

> I envision a squad of about a half-dozen people,
> back-to-back-to-back, etc., trying to fend off the onslaught of C++,
> perl, assembler, etc, etc, etc...

This demonstrates that you have little familiarity with C or
comp.lang.c.




Brian

Article: 118738
Subject: Re: debounce state diagram FSM
From: Flash Gordon <spam@flash-gordon.me.uk>
Date: Thu, 03 May 2007 00:13:04 +0100
Links: << >>  << T >>  << A >>
Rich Grise wrote, On 02/05/07 23:41:
> On Wed, 02 May 2007 08:02:40 +0100, Flash Gordon wrote:
> 
>> Note I've not set followups this time because discussions about 
>> topicality *are* topical.
> 
> And you're still following up to the group that you want the crosspost
> removed from.
> 
> Are you C people all that lame?
> 
> Here's a clue: Set your followups to:
> comp.lang.vhdl,comp.arch.fpga,sci.electronics.design,comp.lang.verilog
> for your whining and bellyaching - you might be surprised!

That does sod all good because the off topic posts are not in response 
to it being redirected.

> Of course, in this case, I've already repaired it.

In the wrong direction since you directed it at the one group we can all 
be reasonably sure you do not read, so I've redirected it back to the 
groups where people have been inconsiderate enough not to restring 
cross-posts after polite requests and are getting upset about some 
people not liking it.

 > And threads like
> this usually die soon anyway.

They die a lot faster when people take note when it is pointed out the 
thread is off topic in one or more groups.
-- 
Flash Gordon

Article: 118739
Subject: OPB Master Peripheral
From: chakra <narashimanc@gmail.com>
Date: 2 May 2007 16:37:23 -0700
Links: << >>  << T >>  << A >>
Hello all, I am working on a project, in which am trying to make
OV7660 camera protoboard to talk to  ML300 Xilinx FPGA board.I have a
general question regarding OPB bus.

Here is the set up:  I am building a OPB Master peripheral which
directly talks to camera (8 data, vsync, Href and Pixclk) via GPIO
pins on the ML300 board. The same master peripheral talks to OPB DDR
SDRAM which is a slave connected to the OPB Bus. the Master peripheral
acquires the data from the camera frame after frame and stores them in
the DDR(currently am overwriting the image over and over at the same
address stack in DDR)

Question:: is there a limitation in terms of "clock cycles" to hold
the M_Select/M_Buslock high when given OPB_Mgrant by the opb BUS. Like
for example "..on a particular time once the OPB gives M_Grant a
Master peripheral can hold the M_Select and M_Buslock high  only for
16 clock cycles...". is there some limitation like the above?

i am holding the M_Buslock and M_Select high till the transfer is
complete. and it takes close to 640*480*2 pixclk to collect one frame
of data from the camera to DDR SDRAM. Once the transfer is complete I
do release those signals and pull M_Dbus to ground. I read through the
Buslock operation given in the OPB manual by IBM and they seem to be
vague on this issue.

algorithm might look like this
A. Master peripheral holds M_Request high
B. OPB gives OPB_Mgrant
C. Master peripheral pulls M_Request low and holds M_select high to
assert OPB bus and take control of the bus. and once transfer is done
D. Master peripheral pulls M_Select Low

If you can help me in this regard it will be very helpful for the
success of my project.


Article: 118740
Subject: Re: debounce state diagram FSM - topical
From: CBFalconer <cbfalconer@yahoo.com>
Date: Wed, 02 May 2007 20:03:08 -0400
Links: << >>  << T >>  << A >>
Flash Gordon wrote:
> Jim Lewis wrote, On 02/05/07 21:24:
>
... snip ...
> 
>> however, if you have a threaded news reader, close
>> the thread and the clutter is gone.
> 
> The additional time downloading is not, and some people are still
> on slow dial-up *and* paying per minute. Also, if it is OK for one
> it is OK for all, so we get loads more off topic cross-posting and
> matters become worse.
> 
>> It seems to me that the only difference it makes is to
>> the people who are following the thread.  I have to flip
>> through the posts without content (your complaints).
> 
> If people would stop the cross-posts when it was pointed out that
> would be one or two posts not lots. Therefore, the thing that will
> reduce it most is if people stop inappropriate cross-posts when it
> is pointed out.
> 
> Why do you think it reasonable for us to have to put up with
> inappropriate cross-posts and not for you to put up with polite
> requests to stop the cross-posts?

What baffles me is that here is a whole list of people complaining,
and not one of them sets the follow-up marker (except me).  I am
wondering if there is something in the readers or servers involved.

-- 
 <http://www.cs.auckland.ac.nz/~pgut001/pubs/vista_cost.txt>
 <http://www.securityfocus.com/columnists/423>
 <http://www.aaxnet.com/editor/edit043.html>
 <http://kadaitcha.cx/vista/dogsbreakfast/index.html>
                        cbfalconer at maineline dot net



-- 
Posted via a free Usenet account from http://www.teranews.com


Article: 118741
Subject: Re: debounce state diagram FSM - topical
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 02 May 2007 17:09:23 -0700
Links: << >>  << T >>  << A >>
On Wed, 02 May 2007 22:59:08 +0100, Flash Gordon
<spam@flash-gordon.me.uk> wrote:

>Jim Lewis wrote, On 02/05/07 21:24:
>> Keith,
>> A few minutes of breathing, adopting a forgiving attitude,
>> and forgoing the concerned posts about the cross-posting
>> would reduce the net traffic by 30% (accurate yesterday -
>> includes replies - probably increased today).
>
>A little consideration by those continuing to cross-post after it has 
>been pointed out would reduce traffic more. After al, the requests were 
>polite.
>
>> Of course it would be nice if people did not cross-post
>> potentially irrelevant topics (which this may or may not
>> be),
>
>Since no one from comp.lang.c has come in to say it is topical on 
>comp.lang.c and the thread has so far had one post with C in it, from 
>someone saying basically "you are complaining so here is some C" I think 
>it is fairly conclusive.
>
> > however, if you have a threaded news reader, close
>> the thread and the clutter is gone.
>
>The additional time downloading is not, and some people are still on 
>slow dial-up *and* paying per minute. Also, if it is OK for one it is OK 
>for all, so we get loads more off topic cross-posting and matters become 
>worse.
>
>> It seems to me that the only difference it makes is to
>> the people who are following the thread.  I have to flip
>> through the posts without content (your complaints).
>
>If people would stop the cross-posts when it was pointed out that would 
>be one or two posts not lots. Therefore, the thing that will reduce it 
>most is if people stop inappropriate cross-posts when it is pointed out.
>
>Why do you think it reasonable for us to have to put up with 
>inappropriate cross-posts and not for you to put up with polite requests 
>to stop the cross-posts?


You're right, engineers and programmers should communicate as seldom
as possible.

John


Article: 118742
Subject: Re: Xilinx tools concern
From: "martin+x@y.z" <martin.usenet@gmail.com>
Date: 2 May 2007 17:20:20 -0700
Links: << >>  << T >>  << A >>
> You must use 9.1 if you need V5.

I do.  I do.   :-)

OK, well, that defines it.

-Martin


Article: 118743
Subject: Xilinx WebPACK 91i on vmware RHEL4
From: Stephen Williams <spamtrap@icarus.com>
Date: Wed, 02 May 2007 18:28:47 -0700
Links: << >>  << T >>  << A >>

I am trying to install the Xilinx ISE WebPACK software on a vmware
virtual machine running RHEL4-WS. I made the machine and installed
RHEL from scratch (it works that far) an now I'm trying to install
the ISE WebPACK.

The "setup" program starts up, displays the pretty banner and asks
me for the devices I want to support. I make my selections, and
click "Next". The puzzling thing is that the installer thinks there
are 0 MB available in the destination volume, and asks me if I want
to install anyhow.

Has anybody been able to install on a vmware virtual machine? I'm
trying real hard to give everybody *exactly* what they want, but
I'm not getting what *I* want:-(

P.S. I'm trying to install from the web installer. I've started
an overnight download of the big single file download, but I have
no reason to believe it will be any different?
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Article: 118744
Subject: Video scaler for Spartan 3E?
From: "Ken Soon" <csoon@xilinx.com>
Date: Thu, 3 May 2007 09:49:16 +0800
Links: << >>  << T >>  << A >>
Hi
Just want to do a feasibility study on whether it is possible to design and 
implement a video scaler on a Spartan 3E?
Well my tutor kind of came up with this proposal for a project of mine but 
then on my tutor's side, he has experience with fpga but I'm not sure 
whether he had designed video scaling so may not know the complexity of it.

So, feasible? And with which chip as well? (in the best of best case, i hope 
can use just a spartan starter kit :) ) 



Article: 118745
Subject: Re: Video scaler for Spartan 3E?
From: "Ken Soon" <csoon@xilinx.com>
Date: Thu, 3 May 2007 09:53:11 +0800
Links: << >>  << T >>  << A >>
Oh if for what images to scale..
hmm maybe videos from a camera?
or would it possible to scale video from a vcd player?


"Ken Soon" <csoon@xilinx.com> wrote in message 
news:f1bf8c$t11@cnn.xsj.xilinx.com...
> Hi
> Just want to do a feasibility study on whether it is possible to design 
> and implement a video scaler on a Spartan 3E?
> Well my tutor kind of came up with this proposal for a project of mine but 
> then on my tutor's side, he has experience with fpga but I'm not sure 
> whether he had designed video scaling so may not know the complexity of 
> it.
>
> So, feasible? And with which chip as well? (in the best of best case, i 
> hope can use just a spartan starter kit :) )
> 



Article: 118746
Subject: Re: Take verilog code from Xilinx Core generator
From: Gordon Freeman <gordonfreeman1983@gmail.com>
Date: 2 May 2007 22:01:02 -0700
Links: << >>  << T >>  << A >>
On Apr 26, 12:01 am, ghel...@lycos.com wrote:
> On Apr 24, 4:06 am, Gordon Freeman <gordonfreeman1...@gmail.com>
> wrote:
>
>
>
> > On Apr 24, 4:29 pm, FPGA <esp...@gmail.com> wrote:
>
> > > Hi Gordon,
>
> > > The core generator only generates the netlist for the IP with Verilog/
> > > VHDL wrapper file functional simulation.
> > > If you use ISE, then you can generate the core inside the ISE and you
> > > can instantiate the core in your design.
> > > Just right click on your project and select "New source" and
> > > IP(Coregen & Arch Wizard) and you can generate
> > > the same core and ISE will add the necessary files automatically.
>
> > > William
> > > On Apr 24, 12:16 am, Gordon Freeman <gordonfreeman1...@gmail.com>
> > > wrote:
>
> > > > Hi everyone!
> > > > I use Xilinx Core generator to generate DA FIR filter. Right now, I
> > > > want to take the verilog code for DA FIR filter but I don't know how
> > > > can I do it.
> > > > Can you help me?
>
> > Thank you for your reply.
> > But I can't modify it.
> > Can you show me how to take the verilog code for synthesize? I would
> > like to know how they process in this code.- Hide quoted text -
>
> > - Show quoted text -
>
> I think you do not understand:  There is no verilog code to take.
>
> It is a "black-box macro"; the verilog wrapper just sets the
> parameters (configuration) of that macro.
>
> You might be able to learn something by doing a gate level simulation,
> but that would be very tedious.
>
> GH.

Thank you very much!
I think I must design it. I have found document talk about DA for FIR
filter.


Article: 118747
Subject: Re: My Dear Spartan-3A, Please Please WAKE UP! SUCCESS!!
From: Antti <Antti.Lukats@xilant.com>
Date: 3 May 2007 00:12:28 -0700
Links: << >>  << T >>  << A >>
On 2 Mai, 19:16, Antti <Antti.Luk...@xilant.com> wrote:
> Antti schrieb:
>
> > After giving up the search for Xilinx supplied MicroBlaze reference
> > designs for Xilinx Spartan-3A kit, I made the reference design using
> > BSB in EDK 9.1SP1.
>
> > No problem encountered until the attempt to load the bitstream into
> > Spartan-3A
>
> > Bitstream download succeeded, Done also OK.
> > Reading back JTAG Status from impact tells me EVERYTHING is OK!
>
> > But... init LED is half-way dimmed and "AWAKE" LED is off, this
>
> another PC, ISE 9.1 (no service pack)
>
> Spartan-3A is working, INIT is not dimmed (OFF)
>
> it is possible that with 9.1SP3 the FPGA also was actually configured
> ok
> (just the microblaze system das 100% dead), - I was irritated by the
> half-way
> lit INIT LED so I assumed FPGA is either misconfured or in some sleep
> state.
>
> sorry for the confusion.
>
> Antti

It useally helps to sleep over a problem - the LED behaviour on Xilinx
Spartan-3A
is all explained:

with default bitgen options (unused IOB pulldown)
* INIT LED "half-on"
* AWAKE LED OFF

bitgen unused IOB pullup
* INIT LED OFF
* AWAKE LED "half-on"

bitgen unused IOB float
* INIT LED OFF
* AWAKE LED OFF

everything as it should be. I was just confused with the INIT LED
yesterday, thats all.
There was actual issue whatsoever, just my over-reacting because other
issues.

Antti


Article: 118748
Subject: Re: debounce state diagram FSM - topical
From: Flash Gordon <spam@flash-gordon.me.uk>
Date: Thu, 03 May 2007 08:41:34 +0100
Links: << >>  << T >>  << A >>
John Larkin wrote, On 03/05/07 01:09:
> On Wed, 02 May 2007 22:59:08 +0100, Flash Gordon

<snip>

>> Why do you think it reasonable for us to have to put up with 
>> inappropriate cross-posts and not for you to put up with polite requests 
>> to stop the cross-posts?
> 
> You're right, engineers and programmers should communicate as seldom
> as possible.

OK, so you are incapable of reading, understanding or answering 
questions even when those you are responding to are staying polite.

For the record, I have never said engineers and programmers should not 
communicate, and I have worked very closely with HW people in the past 
where it was appropriate. However, that still does not, and never can 
make, posting stuff in comp.lang.c about how to design the HW 
appropriate in comp.lang.c

Note that the only comment I got when asking if posting physics 
questions to the other groups was a post saying one of the groups was 
already being invaded by trolls, not a response saying that it would be 
acceptable. So you obviously only care about the topicality of YOUR 
group(s) and sod everybody else.
-- 
Flash Gordon

Article: 118749
Subject: First MicroBlaze demo design for Spartan-3A Starterkit
From: Antti <Antti.Lukats@xilant.com>
Date: 3 May 2007 01:18:48 -0700
Links: << >>  << T >>  << A >>
Hi

Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A
Starterkit so others have to fill the gap, and I am trying to make a
start, here is very simple EDK system that is tested to work on
Spartan-3A Starterkit

http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=select&id=1

Its rather basic system with UART and GPIO, but it is known to work so
can be used as quickstarter.

Antti Lukats
Xilant Technologies.




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