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Has anyone had problems with Altera FIR Compiler generated cores when using the clock enable signal? Have a look at my post at : http://www.alteraforum.com/forum/showthread.php?p=743#post743 I am trying to get a programmable coefficient filter to work with a clock enable, however I get a strange response. I have tried versions 3.3.0, 3.3.1 and 6.1 of FIR compiler. I understand that as of 6.1 the Avalon-ST controller is used which is independent of the global clock enable and is probably causing problems. However v3.3.0 and v3.3.1 are also giving problems, as I show in the post. The only FIR I can get to work with the clock enable is a fixed coefficient filter generated by v3.3.0. Unfortunately Altera support are not offering good advice on this issue.Article: 118951
On 7 May 2007 13:55:54 -0700, lagerstrom@gmail.com wrote: >On May 7, 4:41 am, Antti <Antti.Luk...@xilant.com> wrote: > >[snip] > >> I hope mch_opb_ddr2 will work, but I have been wondering >> why such demo design is not available - this could be an >> indication that the "out of the box" DDR2 IP core will not >> work onSpartan-3A, so I am in a waiting mode, hoping >> for someone to confirm the useability ofEDKDDR2 >> ipcore on XilinxSpartan-3Astarterkit board. > >Antti, I'm in the exact same spot as you are, I just got a Spartan-3A >starter kit to test DDR2 in preparation for a custom board design. > >Can you share your EDK design with the group? Please also post updates >if you manage to get DDR2 to work. > >I did a very quick test yesterday, and the place and route step >complained that it couldn't meet the timing. When creating the design >with BSB it stated that you have to run at 100MHz for the DDR2 >controller to work. I haven't gotten further than that, I hope I >missed something basic. I am now tryiong to start the DDR2 with Microblaze. It will not achieve timnog constarints with 100MHz system clock, but it will achieve them with 66.666MHz system clock! More to come... ZaraArticle: 118952
On 8 Mai, 03:49, idp2 <ian.pei...@gmail.com> wrote: > On May 7, 5:12 pm, berton <werbu...@gmx.de> wrote: > > > On 7 Mai, 22:12, idp2 <ian.pei...@gmail.com> wrote: > > > > On May 7, 1:10 pm, berton <werbu...@gmx.de> wrote: > > > > > Hi! > > > > > For a small project running Linux on a Virtex2pro, I need to write an > > > > IP-component, that recive data from portpins and can transfer data to > > > > RAM directly. > > > > I'm tring to understand DMA, generated by Xilinx EDK (8.2) wizzard. > > > > I think, I've understand some basics. Afer writing the datalength in > > > > the register, the transfer will begin. Correct? > > > > Writing datalength, source- and destinationaddress is done by the > > > > driver? > > > > But how cat I write data from the user_logic to the memory? > > > > Hi, > > > > What kind of developement board are you working with? Are you working > > > with a PCI-based dev board? I've worked with a Spartan3 dev board in > > > Linux and have managed to successfully achieve DMA transfers. > > > > Best, > > > Ian > > > thanks for answering! > > We are working with the xilinx xup v2p with a patched linux 2.6 kernel. > > Have you looked at this yet? It has a pretty good section on reading > and writing to RAM that should answer most of your questions. > > Ian sorry, what you mean exact?Article: 118953
On May 4, 2:31 am, Patrick Dubois <prdub...@gmail.com> wrote: > Hello, > > Does anyone know of an example using lwIP in RAW mode with the > Virtex-4 temac? From what I understand, the lwIP temac port seemingly > only supports lwIP in sockets mode with xilkernel. > > I don't quite understand the lack of temac support at the software > level. What are people doing when using temac on the V4? Is everyone > using lwIP in sockets mode? No one is using raw lwIP on the V4? > > Patrick Why do you need a RAW mode? Do you actually need a TCP/IP stack? If not you can write directly to TEMAC and send RAW frames at highest speed possible. GuruArticle: 118954
Hi there,
I'm approaching ISE 8.1i. Trying to Simulate Behaviour Model I get the
error message:
"HDLParsers:164 - C:/Xilinx_Projects/tri_state_test/tri_state_tbw.vhw"
Line 43. parse error, unexpected CLOSEPAR, expecting IDENTIFIER or
STRING_LITERAL.
I'm using a resolution function to solve a bus, and it seems the
resolution function is not inserted in the self-compiled .vhw file
("SIGNAL OUTPUT : := '0';", there is no signal's type).
Can anybody tell me whether I'm wrong somewhere or there is a bus?
Thanks
Article: 118955Subroto Datta schrieb: > On May 7, 9:46 am, General Schvantzkoph <schvantzk...@yahoo.com> > wrote: >> I've been trying to use Quartus 7 on Linux (I've tried three different >> RedHat/Clone distros, FC6, CentOS 5, Scientific Linux 4.4. The fitter is >> getting a license failure, >> >> Current license file does not support the EP2SGX90FF1508C4 device >> >> Quartus 6.1 runs fine and my Altera FAE thinks my license file is fine. >> Has anyone run Quartus 7 on Linux, how about on a RH clone? Is it >> possible that they put in a check for the distro to see if it's a >> supported distro? > > Hi, > > There is a bug in 7.0 which will affect the user if the license is > for 1 user only. There is a patch available for it. Quartsu II 7.0 > Patch 0.02. Please contact mysupport and ask for it. We apologize for > any inconvenience this may have caused. > > Hope this helps, > Subroto Datta > Altera Corp. > Quartus 7.x Linux runs fine on Redhat WS 4 as also the freely available Centos 4.4 clone...also remembering having it once up on Gentoo 2006.1 Linux...not sure about Stratix devices though as I don't use them (o; Only problem with byteblaster code as it is prehistoric Linux-2.4.x kernel stuff (o; cheers rickArticle: 118956
Thanks a lot all. Just got back from Switzerland. I'll dig into this matter further using the suggested pointers. Cheers, -MannyArticle: 118957
"Bob" <bob3635x@yahoo.com> wrote in message news:1178593413.685757.5860@y5g2000hsa.googlegroups.com... > > I think a better choice would be to open source iMPACT. I doubt if > it contains any strategic IP. There are six computers in the office > suite where I work, including Win-XP, Linux, and FreeBSD on x86_64; > and Win-XP and Linux on x86_32. ISE runs fine on all of them. iMPACT > runs on precisely one (Win-XP on x86_32). It fails on all the others > for various reasons. It also fails to work on VMware. These sorts > of driver and OS compatibility issues are something the OSS community > is quite good at fixing. > That's a v.good idea for a starting point. I'd also like to see ChipScope follow that. Even if it's just the UI, not the core. (Of course, if the core did go open source, I'd be happy to add a clock enable for the core's clock input, and make the thing usable at >200MHz, but that's a separate gripe...) Cheers, Syms.Article: 118958
An Open-Source suggestion for Xilinx In generic the decision about to use Open-Source strategies is very complex, but there is an easy and low risc way to at least make the first step, the portion that could be tried as Open-Source is related to programming cable support as first step the firmware for USB Platform Cable or at least the protocol information could be released to the public - the development that follows (or doesnt) could be used as indicator if there is change for success for larger parts of the tools to go Open-Source. The current programming support is bad, this both on the PC side software (impact), the host drivers and and the embedded firmaware in platform cable(s). There is already some effort done, I list it here 1) Impact TCP protocol has been reverse engineered and there is open-source cable-server 2) I have tried to make software support for Cable IV high speed mode, even made special FPGA-PCI design that emulates LPT port + Cable IV. There is no final result on that yet. 3) I have written Coolrunner disassembler in order to reverse engineer the Cable IV code 4) There is 3rd party replacement firmware for USB platform cable 5) possible more projects that we dont know about. ALL THOSE efforts have been done to improve the Support for the programming hardware manufactured by Xilinx Inc. Xilinx Cable IV - it very seldomly works in high speed mode Xilinx has not been able fix the driver issues, and I guess never will Xilinx USB Cable (and embedded USB Cable) is "kinda working" but it is only useable as download cable and XMD debug, but it can not be used as user communucation channel to user IP cores in Xilinx FPGA. Those issues (bad support for Xilinx programming hardare) could be done by "Open-Source" initiative WITHOUT Xilinx support, as the reverse engineering needed is not complicated at all. The thing is that there is not enough interest, so everybody keeps using the existing solutions the way they work, not releasing the full potential. There is lots of open-source software that supports Cable III, and NONE that would support Cable IV, or Platfrom USB Cable. just me 2 eurocents. Antti LukatsArticle: 118959
On 8 Mai, 09:56, Zara <me_z...@dea.spamcon.org> wrote: > On 7 May 2007 13:55:54 -0700, lagerst...@gmail.com wrote: > [..] > I am now tryiong to start the DDR2 with Microblaze. It will not > achieve timnog constarints with 100MHz system clock, but it will > achieve them with 66.666MHz system clock! More to come... > > Zara- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - its VERY hard to meat 100MHz timings even in V4 or V5 so I no wonder the EDK-DDR2 design in Spartan-3A doesnt want to meat 100MHz timings. also check the Spartan3A "product notification" and your PCB rev. if you have REV C you need to solder bridge 2 ferrites to get the DDR2 to work at higher clock rates. AnttiArticle: 118960
On 7 Mai, 23:05, <steve.l...@xilinx.com> wrote: > Mike, > > I'm probably the one you were looking for at ESC. I am not an expert on > open source software, but will give you my thoughts on why it won't > work for FPGAs: > - We have a fair amount of 3rd party software that we ship with ours > and we have no rights to distribute that source. > - We have about 250 people writing software. While I'm sure there are > 20 or 30 people that think FPGAs are cool enough to want to help out, I > doubt there are enough. > - Most of our time is spent doing new device support (and this in not just > within the map and par groups). How do we get these "volunteers" to > deliver new devices when we need them? > - We start the software for new devices about 2 years before the software > for that family is released. Making the details of a new architecture public > at that time is not an option. > - Going open source is like handing our source code over to our > competitors. > - I'm not exactly clear on who would support our customers as they run > into bugs, but I guess it would be us meaning we would have to have > people ready to fix someone else's code. > - The only other open source program for FPGAs failed:http://www.pldesignline.com/news/164900514 > It failed for ONE SIMPLE REASON: IT WAS NEVER STARTED OR OPENED. The project was cancelled before ANY open-source development on the project started. So please dont say the open-source project failed - because there was none. Would it have been started, chances are it would not have failed. Antti LATEST Xilinx BUG: Unable to register TclNotifier window class This application has requested the Runtime to terminate it in an unusual way. Please contact the application's support team for more information. make: *** [microblaze_i/lib/libxil.a] Error 3 Done! PRE-LATEST XILINX BUG SAME as latest but error number 66 I wonder if next one will be BUG:666 ?Article: 118961
Hi. I'm debugging an issue with my board. The issue surfaces when several components interact, and I'm not able to reproduce the problem in a pure simulation environment. I heard that Chipscope is a powerful tool for this type of debugging. However, my board has JTAG functionality through a custom interface (not a Xilinx cable). Is it possible to make Chipscope work with my custom interface? I use Windows and have C/C++ development tools available. I already made an XSVF player to program my board via the custom interface. Regards, Marc PS: My alternative is to reinvent the wheel and add a trace buffer and trigger logic to my design, and write a tiny readout tool and a visualization filter. I started with this already, but struggle because if Chipscope were compatible I would save time and get the better tool.Article: 118962
On 8 Mai, 14:14, jetm...@hotmail.com wrote: > Hi. > > I'm debugging an issue with my board. The issue surfaces when several > components interact, and I'm not able to reproduce the problem in a > pure simulation environment. > > I heard that Chipscope is a powerful tool for this type of debugging. > However, my board has JTAG functionality through a custom interface > (not a Xilinx cable). > > Is it possible to make Chipscope work with my custom interface? I use > Windows and have C/C++ development tools available. I already made an > XSVF player to program my board via the custom interface. > > Regards, > Marc > > PS: My alternative is to reinvent the wheel and add a trace buffer and > trigger logic to my design, and write a tiny readout tool and a > visualization filter. I started with this already, but struggle > because if Chipscope were compatible I would save time and get the > better tool. It *IS* possible but currently it means that you need need to reverse engineer the chipscope server protocol and implement your custome server that talks to the your cable. There is partially done impact cable server but I think chipscope needs its own server :( AnttiArticle: 118963
On 8 Mai, 13:36, Antti <Antti.Luk...@xilant.com> wrote: > On 7 Mai, 23:05, <steve.l...@xilinx.com> wrote: > LATEST Xilinx BUG: > Unable to register TclNotifier window class > > This application has requested the Runtime to terminate it in an > unusual way. > Please contact the application's support team for more information. > make: *** [microblaze_i/lib/libxil.a] Error 3 > > Done! > > PRE-LATEST XILINX BUG > SAME as latest but error number 66 > > I wonder if next one will be BUG:666 ?- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - I was wrong: the next bug (within 2 minutes was) error: 2 the next one, in EDK project "can not process edkbmm file" (this was a formerly working project pre 9.1) the next one, this time in ISE: Main Menu-> "Open Project" - NOTHING Happens! no dialog nothing. EVERY school boy can make a "File Open" dialog to appear at least. Xilinx has trouble even with this task. I know there are plenty of customers who are happy with ISE 9.1SP3 but there are also those who arent. And not all of them give feadback. So the existance of happy customers should not be treated as definitive indicator that the software is good at all. Antti who is starting another fight to force Xilinx latest and greatest software to perform the simplest tasks.Article: 118964
Antti wrote: > I know there are plenty of customers who are happy with ISE 9.1SP3 > but there are also those who arent. And not all of them give feadback. > So the existance of happy customers should not be treated as > definitive indicator that the software is good at all. > Happy is a relative term. Compared to the trainwreck that was ISE8.x, 9.1sp3 is a Godsend. 9.1sp3 is usable, which is a lot more than can be said for 8.x.Article: 118965
On 8 Mai, 14:43, Ray Andraka <r...@andraka.com> wrote: > Antti wrote: > > I know there are plenty of customers who are happy with ISE 9.1SP3 > > but there are also those who arent. And not all of them give feadback. > > So the existance of happy customers should not be treated as > > definitive indicator that the software is good at all. > > Happy is a relative term. Compared to the trainwreck that was ISE8.x, > 9.1sp3 is a Godsend. 9.1sp3 is usable, which is a lot more than can be > said for 8.x. eh, agreed the "hard things" that really matter are probabley way better in ISE 9.1SP3 just a pity that "some small things" make trouble, besides I did not comment so much on ISE 9.1, but the 9.x "complete" most of the issues are related to EDK not ISE. and here too if running all tools from commandline there are good chances that everything works fine. my latest issues - well I got a urgent project (demo needed monday) and in the attempt to use some ISE+EDK combined desing from pre 9.1, well I got maybe 6 different errors not related to the design. It is still not passsing the full flow. AnttiArticle: 118966
On the output side, I would like to use Xilinx GTP transceivers. The GTP transceivers will get connected to the LVPECL device with high common mode range of 1.2v to 2.5v and differential swing range of 300mv to 2400mv. I would like to know the Vhigh, Vlow and Vcm values of GTP transceivers in LVPECL output mode.Article: 118967
"Ray Andraka" <ray@andraka.com> wrote in message news:4640707F.9040002@andraka.com... > Antti wrote: > >> I know there are plenty of customers who are happy with ISE 9.1SP3 >> but there are also those who arent. And not all of them give feadback. >> So the existance of happy customers should not be treated as >> definitive indicator that the software is good at all. >> > Happy is a relative term. Compared to the trainwreck that was ISE8.x, > 9.1sp3 is a Godsend. 9.1sp3 is usable, which is a lot more than can be > said for 8.x. Tell me about it. I'm using 8.2. I don't normally like to change versions during a project, but I think I'm going to do so now. I've seen malicious viruses be more user friendly than this. But, I mustn't be venomous, after all I only need to use this stuff so I can earn a living. Cheers, Syms.Article: 118968
On 8 May 2007 03:34:20 -0700, Antti <Antti.Lukats@xilant.com> wrote: >An Open-Source suggestion for Xilinx > >In generic the decision about to use Open-Source strategies >is very complex, but there is an easy and low risc way to >at least make the first step, the portion that could be >tried as Open-Source is related to programming cable support >as first step the firmware for USB Platform Cable or at least >the protocol information could be released to the public - >the development that follows (or doesnt) could be used as >indicator if there is change for success for larger parts >of the tools to go Open-Source. <...skip all the rest of these magnificient speech...> > Yes Antti, that would be the solution for *lots* of problems I would enrol on such kind of efforts. Best regards, ZaraArticle: 118969
On 8 May 2007 04:24:30 -0700, Antti <Antti.Lukats@xilant.com> wrote: >On 8 Mai, 09:56, Zara <me_z...@dea.spamcon.org> wrote: >> On 7 May 2007 13:55:54 -0700, lagerst...@gmail.com wrote: >> >[..] >> I am now tryiong to start the DDR2 with Microblaze. It will not >> achieve timnog constarints with 100MHz system clock, but it will >> achieve them with 66.666MHz system clock! More to come... >> >> Zara- Zitierten Text ausblenden - >> >> - Zitierten Text anzeigen - > >its VERY hard to meat 100MHz timings even in V4 or V5 >so I no wonder the EDK-DDR2 design in Spartan-3A >doesnt want to meat 100MHz timings. > >also check the Spartan3A "product notification" and your PCB rev. >if you have REV C you need to solder bridge 2 ferrites to get the DDR2 >to work at higher clock rates. > >Antti Done it. But there is something with one of my SDK installations (the one I use to communicate with S3 Lti, so my progress has stopeed for a littel while). Hope it will restart soon! ZaraArticle: 118970
On 3 May 2007 01:18:48 -0700, Antti <Antti.Lukats@xilant.com> wrote: >Hi > >Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A >Starterkit so others have to fill the gap, and I am trying to make a >start, here is very simple EDK system that is tested to work on >Spartan-3A Starterkit > >http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=select&id=1 > >Its rather basic system with UART and GPIO, but it is known to work so >can be used as quickstarter. Well done. Heh, at least you are (rightly) one of the inner circle who has the board! Consider the situation for those in the cold outside who might happen to want one. Despite it being a "Featured Board" on http://www.xilinx.com/products/devboards/ you can't get it from the online store. The distributor links on its page http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3A-SK-UNI-G offer three alternatives (two of them, supposedly to US distributors, are out of date re-directs) the third is to the "local distributors". In my country there are apparently 3 distributors; - one doesn't list the board on their website (at least, not under "evaluation kits and boards; Xilinx", so where else should I look?) - the second's website "cannot be found" (and the contact email address is either in a different domain or a typo) - the third apparently doesn't have a website! Ahh, British customer service at its best... http://www.amazon.com/Fawlty-Towers-Complete/dp/B00005LC1H/ref=pd_bbs_sr_1/103-5337383-1843037?ie=UTF8&s=dvd&qid=1178630557&sr=8-1 back to those US distributors. One says the board is out of stock, and please call because we won't sell it online anyway. The other, fortunately, claims to have it in stock, and accepts my order, asking only a mere $75 for shipping, on what, a 1kg product? We'll see how long it takes... Hey Xilinx, I'd suggest there's a little room for improvement here. - BrianArticle: 118971
On 8 Mai, 15:32, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On 3 May 2007 01:18:48 -0700, Antti <Antti.Luk...@xilant.com> wrote: > > >Hi > > >Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A > >Starterkit so others have to fill the gap, and I am trying to make a > >start, here is very simple EDK system that is tested to work on > >Spartan-3A Starterkit > > >http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=... > > >Its rather basic system with UART and GPIO, but it is known to work so > >can be used as quickstarter. > > Well done. > > Heh, at least you are (rightly) one of the inner circle who has the > board! > > Consider the situation for those in the cold outside who might happen to > want one. > > Despite it being a "Featured Board" onhttp://www.xilinx.com/products/devboards/you can't get it from the > online store. > > The distributor links on its pagehttp://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... > offer three alternatives (two of them, supposedly to US distributors, > are out of date re-directs) the third is to the "local distributors". > > In my country there are apparently 3 distributors; > - one doesn't list the board on their website (at least, not > under "evaluation kits and boards; Xilinx", so where else > should I look?) > - the second's website "cannot be found" (and the contact email > address is either in a different domain or a typo) > - the third apparently doesn't have a website! > Ahh, British customer service at its best...http://www.amazon.com/Fawlty-Towers-Complete/dp/B00005LC1H/ref=pd_bbs... > back to those US distributors. > > One says the board is out of stock, and please call because we won't > sell it online anyway. > > The other, fortunately, claims to have it in stock, and accepts my > order, asking only a mere $75 for shipping, on what, a 1kg product? > We'll see how long it takes... > > Hey Xilinx, I'd suggest there's a little room for improvement here. > > - Brian Oh gosh - you know I asked my firend in the US to order the S3A board IMMEDIATLY when it was announced to be available. To our suprise it arrived from Avnet US very quickly (my last order from Avnet US Virtex-4 kit was delayes more then 6 months). Recenlty at X-Fest there was again special offer for 199USD (X-Fest in Munich, price in Dolloren?), and as my devkit was at that time still in transit from the US (and stuck in Frankfurt customs for no reason for 3,5 weeks), I was almost to order another board in the hope it would arrive from german disti immediatly. Well I waited another day and got my board from customs after paying 19% VAT and some other mysterious amount of tax. I wonder how long the order from Avnet germany would have taken. Well - while being happy having the board, I am also unhappy as for the most urgent task at the moment I cant use it, as there is no reference design. Usually ALL Xilinx Boards with ethernet cababiliy do come with Xilinx webserver demo as primary board demo with networking, so I of course assumed the Spartan-3A board would also have it. But, NO. Well, there is 10/100 ethernet design included. And a very clever one! It uses PicoBlaze that communicates oved MII management interface and tests the PHY using RJ45 loop back cable. So the 10/100 interface is working and tested and Xilinx can say that there is a networking demo! This remainds me the ML300 board (5000 USD value). That board had Serial ATA host and device connectors (the reason to obtain it!) - when I asked about it then Xilinx response was: Yes, it works! We have a test design that loops back the SATA connectors and tests it! Of course only later Xilinx admitted that SATA is not working on Virtex-4 as the physical layer is not fully SATA compliant. Hope it will not be the same case with DDR2 on Spartan-3A starterkit board. AnttiArticle: 118972
Symon wrote: > "Ray Andraka" <ray@andraka.com> wrote in message > news:4640707F.9040002@andraka.com... > >>Antti wrote: >> >> >>>I know there are plenty of customers who are happy with ISE 9.1SP3 >>>but there are also those who arent. And not all of them give feadback. >>>So the existance of happy customers should not be treated as >>>definitive indicator that the software is good at all. >>> >> >>Happy is a relative term. Compared to the trainwreck that was ISE8.x, >>9.1sp3 is a Godsend. 9.1sp3 is usable, which is a lot more than can be >>said for 8.x. > > > Tell me about it. I'm using 8.2. I don't normally like to change versions > during a project, but I think I'm going to do so now. I've seen malicious > viruses be more user friendly than this. But, I mustn't be venomous, after > all I only need to use this stuff so I can earn a living. > Cheers, Syms. > > I tried 8 after a few service packs, and could not get existing designs through it, so I stuck with 7.2sp4 until recently (beginning of April). 7.2sp4 was far more usable than any version of 8. That's why I was pleasantly surprised when my stuff ran through 9.1sp3 without a hitch. I too do not like changing tools mid-project unless there is a compelling reason. I also do not move up a major revision until at least the second service pack and after seeing how others have fared with it. I've spent far too many unreimbursed hours debugging major releases in the past so I avoid it like the plague.Article: 118973
As I understand the documantation for the GTPs, there IS no LVPECL "mode" but only CML from the appropriate termination voltage you choose. There should be an acceptable range for the output but I didn't find it in the quick scan of the current data sheet (preliminary information and all that). Perhaps your FAE can get more specifics on the GTP voltage values that have yet to make it into the data sheet tables. Your input is LVPECL and not CML? I thought you were talking CML in/out in the earlier threads. "Test01" <cpandya@yahoo.com> wrote in message news:eea69d6.12@webx.sUN8CHnE... > On the output side, I would like to use Xilinx GTP transceivers. The GTP > transceivers will get connected to the LVPECL device with high common mode > range of 1.2v to 2.5v and differential swing range of 300mv to 2400mv. > > I would like to know the Vhigh, Vlow and Vcm values of GTP transceivers in > LVPECL output mode.Article: 118974
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:dot043d1oc23r5mjr4uco4j24h5n7nnqn5@4ax.com... > On 3 May 2007 01:18:48 -0700, Antti <Antti.Lukats@xilant.com> wrote: > >>Hi >> >>Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A >>Starterkit so others have to fill the gap, and I am trying to make a >>start, here is very simple EDK system that is tested to work on >>Spartan-3A Starterkit >> >>http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=select&id=1 >> >>Its rather basic system with UART and GPIO, but it is known to work so >>can be used as quickstarter. > > Well done. > > Heh, at least you are (rightly) one of the inner circle who has the > board! > > Consider the situation for those in the cold outside who might happen to > want one. > > Despite it being a "Featured Board" on > http://www.xilinx.com/products/devboards/ you can't get it from the > online store. > > The distributor links on its page > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3A-SK-UNI-G > offer three alternatives (two of them, supposedly to US distributors, > are out of date re-directs) the third is to the "local distributors". > > In my country there are apparently 3 distributors; > - one doesn't list the board on their website (at least, not > under "evaluation kits and boards; Xilinx", so where else > should I look?) > - the second's website "cannot be found" (and the contact email > address is either in a different domain or a typo) > - the third apparently doesn't have a website! > Ahh, British customer service at its best... > http://www.amazon.com/Fawlty-Towers-Complete/dp/B00005LC1H/ref=pd_bbs_sr_1/103-5337383-1843037?ie=UTF8&s=dvd&qid=1178630557&sr=8-1 > back to those US distributors. > > One says the board is out of stock, and please call because we won't > sell it online anyway. > > The other, fortunately, claims to have it in stock, and accepts my > order, asking only a mere $75 for shipping, on what, a 1kg product? > We'll see how long it takes... > > Hey Xilinx, I'd suggest there's a little room for improvement here. > > - Brian If you sign up for X-Fest in Manchester, you might be offered a seminar discount for development boards such as the Spartan-3A. Heck, the X-Fest I attended even gave one away. There are a couple X-Fests in the UK, Manchester is just the first of the two at the end of May.
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