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Maybe this is homework, or it is an interview question, but I took it as a challenge. Being a minimalist, and understanding metastability fairly well, I came up with the following solution: Only one 4-input LUT plus a flip-flop clocked by the slow clock. LUT inputs are: INput pulse, slow CLK signal, its own output O, the flip-flop output Q ( set O if Qbar AND INpulse, reset O if Q AND CLKbar, otherwise keep O. O drives flip-flop D) Ah, but how about metastability? If IN and CLK both go High within a certain bulls-eye that is <1 femtosecond wide, then Q might be undefined for a few ns after the rising clock edge. Statistically, the "few ns" will not exceed 3 ns during the lifetime of the universe. The, hopefully synchronous, slow clock domain should be able to cope with that. Otherwise concatanate another flip-flop. Well, I do not know why anybody wants such a circuit, but it did exercise the grey cells... Peter Alfke On May 16, 7:09 am, Paul <pauljbenn...@gmail.com> wrote: > General rule of thumb is that you want 2 registers to cross between > clock domains, follow that rule to deal with any metastability > issues. Now you just have the problem that your first clock domain is > faster and you might not catch it with the slower domain. > > Personally, my approach here would be to "hold" the signal in your > CLK_FAST with an enabled register until you receive some sort of feed > back that you've grabbed it in CLK_SLOW, bearing in mind that those > feedback / feedforward signals should all be double registered to > prevent metastability. Also keep in mind that an enabled register > does NOT count as one of your two "synchronization" registers, because > an enabled register is actually implemented as a register with a mux > in front of it - only direct D-to-Q connections with NO combinational > logic count for clock domain crossing issues. Now, depending upon the > timing of it all, this could end you up with more than 1 clock pulse > width. Assuming that you know your input pulses are spaced far enough > apart that you KNOW it's not ACTUALLY multiple pulses, then a simple > edge detect will fix this problem for ya. > > The ideal behind the metastability stuff is that if you clock a signal > exactly at the transisition the output of the flop has some > probability of floating somewhere between 0 and 1 for some amount of > time. Adding any combinatorial logic extends that amount of time. > The idea of having 2 registers is that you reduce your probability of > a metastable event because even if you hit that .01% chance of it > remaining metastable for long enough to create a problem at the first > register, you got another .01% on your side at the second register. > (Note: .01% is much higher than it really is.. but remember, if you're > clocking signals in the MHz range, those tiny probabilities add up > REAL quick!) > > On May 16, 1:35 am, himassk <hima...@gmail.com> wrote: > > > Hi, > > > Please suggest me how to transfer a single clockwide pulse from high > > frequency clock domain and create a single clockwide pulse in a slow > > clock domain? > > What are different methods available? > > > Thanks in advance. > > > Regards, > > Himassk.Article: 119326
"Anne" <anneatkinson@yahoo.com> wrote in message news:1179331157.808046.24310@y80g2000hsf.googlegroups.com... > > An ultimate goal of this sub-project is to reduce the total number of > spare parts that must be flown on a mission by having spares that are > reconfigurable such that, for example, they could function as a DSP or > microprocessor or microcontroller at any given time (just one specific > application at any given time). > Hi Anne, Here's a thought. Imagine you make a bunch of identical thingies which can be either a dsp, a uP, whatever. Cool, you've reduced the parts inventory. You set off on your mission to Mars, and one of these things go wrong. However, it turns out this is not a random failure, but a systemic failure due to a design fault. (Perhaps the sub-contract designer mixed up imperial and metric units?!) This means, because all your replacements are identical, they'll all have the same fault. Kinda like the reason that some people think GM crops are bad, because a single disease can wipe out an entire harvest of a monoculture plant. Maybe there's an argument to have a couple (or maybe more) different designs of replacement. It's a long trip to Fry's from the red planet! Cheers, Syms.Article: 119327
In article <f2egq4$b9t5@cnn.xsj.xilinx.com>,
"Göran Bilski" <goran.bilski@xilinx.com> writes:
|> I would advice to get the latest version of EDK and ip cores.
|> There might be a bug which is fixed in the latest versions.
Already in the queue, but mostly due to some bugfixes in the Microblaze core...
I already planned to rewrite the DDR-controller from scratch, since I
need high burstrates (>100MB/s) and low latency via DMA. The current design is
only a proof-of-concept for the other parts in the FPGA.
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 119328Kevin Neilson wrote: > Jim Granville wrote: > >> Kevin Neilson wrote: >> >>> I know that an FPGA's power consumption is basically linear with >>> clock frequency, but does anybody know what happens when the maximum >>> clock frequency for the design is approached? Does power consumption >>> remain linear in this region where failures and setup violations >>> begin to occur, or would it then be expected to go up or down? Or is >>> it totally design-dependent? >> >> >> It would depend. If (eg) counters start skipping clocks, then power >> consumption would be expected to decrease, but only for the cells that >> were hitting their thresholds. ( so a small % of total Icc ) >> However, if something like a state engine starts short-cycling, then >> power consumption could increase, again slighty. >> >> Why the question - are you thinking of using changes in Icc to flag >> timing failures ? >> >> -jg >> > We had a design for which power consumption was linear up to near (but > less than) How much less than ? > the max rated frequency, and then the power consumption went > down. I don't know if it's because of a timing failure--the design > being tested has no self-checking mechanism--but I wondered if that were > a possibility. -Kevin Yes, I would be alert - certainly there is no process explanation for a decrease, it has to be caused by a change in toggling nodes. You could confirm it is a timing failure, by introducing another variable, like temperature, and seeing if the change-point moves. Simple items like counters, will fail with lower frequencies, and often with some 'noise' It is not a bad to overclock a design in test, to make sure you really DO have a timing margin. -jgArticle: 119329
michel.talon@gmail.com wrote: > First, thank for all your answers, > in facts, I'm designing an emulator for an hardware microcontroler. So > I've to embed microcontroler sources ( originaly coded for hardware IC > design ) in my virtex FPGA. > One of the goal of the project is to preserve microcontroleur > functionality and mechanisms ( to obtain a real emulation ), this why > I can't use a clock to delay my signal. > This signal must be delayed by about 50ns. I know this is a large time > without use of clock, and that's all my problem.. > > best regards, Michel Talon. FPGAs themselves are not designed to give time-delays. If this is an important emulation detail (and there may be others, too ) I'd suggest you add an external delay block. An LVC14 Schmitt, and R/C elements, which can be series, or shunt, connected. Depends on the nature of the delay. Another approach would be to start with a much faster clock than the core needs : Divide it down for the core, and use the finer granularity for clocked delays on the pins that need the 'emulation patches'. eg 100Mhz will allow you 10ns IO granularity, and 100Mhz local clock speed is lowish for modern FPGAs. This will also simulate correctly. -jgArticle: 119330
michel.talon@gmail.com wrote: > > First, thank for all your answer, > In fact I'm designing an emulator for an onchip microcontroler. The > goal of the project is to obtain the same mecanisms and functionality > for the emulator to reach a real emulation. > I've to carry microcontroler IC design sources to virtex FPGA without > modify them or just a little. > The signal I've to delay is embedded in one of the lowest hierarchical > module and I can't input a clock to this module. > The signal must be delayed by 20ns minimum, but accuracy is not > required. > > I know this is not a good thing for FPGA, but I've not better > solution, and this all my problem.. If this is a 'don't touch' exercise, then you will need the external delay patch I mentioned in my other post. You probably should also try and get similar-process external IO buffers if you are looking for accurate emulation. -jgArticle: 119331
On May 16, 6:28 am, Test01 <cpan...@yahoo.com> wrote: > As per my understanding, Virtex5 GTP output supports CML standard. May I know the Common mode voltage and differential voltage from the Xilinx FPGA? Here is a simplified description: Each output pin has a fixed resistor of 50 Ohm to its supply voltage Vcc. There is also a ~ 10 mA constant-current pull-down generator, common to the two differential pins. Each pin has a transistor that connects or disconnects the constant pull-down current to the pin. That means, the output voltage per pin swings between Vcc and Vcc minus about 500 mV, which thus creates a differential output voltage of about 1000 mV peak to peak, with a common mode voltage of about Vcc minus 250 mV. Peter AlfkeArticle: 119332
The Actel Family that i'm using is FUSION, the chip is AFS600, the problem is when i use a macro to use the internal clock, synplify can syhthesize the architecture but when i do the place and route step the compiler detect an error of extra global ressources. i need just two clocks as global ressources and there two reset signals that are detected as global rssources which is right but synplify is autodetecting other signals as global ressources (i used the default configuration of synplify, in libero environment) here the error message i m receiving: Error: CMP601: This design has a CLKSRC instance 'Clock_div_inst/ CLK_inferred_clock/U_CLKSRC' driven by a clock net which is not needed. i know that in the message it mentioned that "is not needed" but it it is needed!!!! if yes i can configure synplify to not consider some signal as global ressources and some others as essential global ressources, how can i do it? Regards, On 16 mai, 04:37, Alan Myler <amy...@eircom.net> wrote: > Amine.Mi...@gmail.com wrote: > > Hi > > > i'm developping an architecture using Libero and Actel FPGA, i had a > > problem with global ressources, I had 8 global ressources and the > > FPGA contains only 6, is there any way to oblige the compiler to not > > consider some signals as global ressources, > > synthesysing tool used: Synplify, > > > regards, > > A. > > The simply answer is yes. But first perhaps you can expalin what you > want to use the global resources for? If you want 8 clocks for exampe > then you will need to consider what Synplify will synthesise instead of > a global buffer. > > What Actel family are you using? > > AlanArticle: 119333
Hi Anne, Anne wrote: > I am currently working on a NASA program focused on the development of > Radiation-Hardened Electronics for Space Environments (RHESE). One > portion of the sub-project I am working in support of is aimed at > developing reconfigurable modular spare electronic parts for avionics > systems. Are you aware of the Reconfigurable Scalable Computing (RSC) project being run out of NASA Langley? A few web references below, but feel free to contact me directly if you'd like more info. http://linuxdevices.com/news/NS9415221766.html http://www.klabs.org/mapld05/presento/130_hodson_p.ppt http://www.klabs.org/mapld05/presento/125_somervill_p.ppt http://www.klabs.org/mapld05/presento/1001_williams_p.ppt Regards, JohnArticle: 119334
"comp.arch.fpga" <ksulimma@googlemail.com> wrote in message news:1179219540.483073.253330@o5g2000hsb.googlegroups.com... > On 8 Mai, 23:12, <steve.l...@xilinx.com> wrote: >> There are a few programs that we could open-source, but they >> only have a few engineers working on them, so it would not save >> resources since we have to manage the open-source projects. > > No necessarily. Besides opening and supporting your tools there > are three other options: > > 1) Opening interfaces, file formats, APIs, etc > This allows people to create tools that are completely independant of > your software. > Xilinx did that with XNF and JBits and there was quite a lot of > activity > in academia using these. XNF is a simple netlist format. We got rid of the proprietary format and went to EDIF which anybody can read and write. I'll have to look into what happend with Jbits, but I seem to remember the issue was keeping up with all the new families. So if we made Jbits open-source, the issue would be publishing all of the bitsteam info for each architecture. > For the configuration tools issue this is likely to solve most of the > problems. > > 2) Open Source your Code without managing the project > You can release code for less important projects like Impact without > taking care of the open source development process. The main complaints we get on Impact have to do with people using the many variants of Linux. Our current plan is to look into using the Linux USB driver to address this. Steve > The community can create a > fork that > competes with your implementation. You can formulate the license in a > way that > allows you to port back any code into your closed source branch. There > is no need > for you to provide any support at all to the open source brach. > This is similar to the old days of Star Office. > > 3) Open source abandoned projects > This is what IBM did with OpenDX. IBM was still actively using this > tool internally but > decided that it was not successfull as a product. By opening it up > thay made sure that > it continued to be maintained to some extend. > How about the source code for JBits, JINI, etc.? > > Kolja Sulimma >Article: 119335
<Amine.Miled@gmail.com> wrote in message news:1179355690.593620.280300@q75g2000hsh.googlegroups.com... > The Actel Family that i'm using is FUSION, the chip is AFS600, the > problem is when i use a macro to use the internal clock, synplify can > syhthesize the architecture but when i do the place and route step the > compiler detect an error of extra global ressources. > > i need just two clocks as global ressources and there two reset > signals that are detected as global rssources which is right but > synplify is autodetecting other signals as global ressources (i used > the default configuration of synplify, in libero environment) > > here the error message i m receiving: > Error: CMP601: This design has a CLKSRC instance 'Clock_div_inst/ > CLK_inferred_clock/U_CLKSRC' driven by a clock net which is not > needed. > > i know that in the message it mentioned that "is not needed" but it it > is needed!!!! > > if yes i can configure synplify to not consider some signal as global > ressources and some others as essential global ressources, how can i > do it? > > Regards, <snip> Have you looked at the Synplicity FPGA Synthesis Reference Manual section entitled "Designing with Actel?" Specifically, the "Actel Attribute and Directive Summary." possibly helpful: synthesis syn_global_buffers synthesis syn_noclockbuf synthesis syn_insert_bufferArticle: 119336
On May 14, 12:29 pm, v...@altera.com wrote: > On May 8, 1:53 am, Wilhelm.Kl...@gmail.com wrote: > > > Has anyone had problems withAlteraFIRCompiler generated cores when > > using theclock enablesignal? > > > Have a look at my post at :http://www.alteraforum.com/forum/showthread.php?p=743#post743 > > > I am trying to get a programmable coefficient filter to work with a > >clock enable, however I get a strange response. I have tried versions > > 3.3.0, 3.3.1 and 6.1 ofFIRcompiler. I understand that as of 6.1 the > > Avalon-ST controller is used which is independent of the globalclock> enableand is probably causing problems. However v3.3.0 and v3.3.1 > > are also giving problems, as I show in the post. The onlyFIRI can > > get to work with theclock enableis a fixed coefficient filter > > generated by v3.3.0. UnfortunatelyAlterasupport are not offering > > good advice on this issue. > > Hi Wilhelm, > > There was a bug in earlier versions of theFIRcompiler in that it > relied onclock enablebeing high immediately after reset. Ifclockenablewas low, the coefficient address logic would run anyway for a > clock cycle, with the result that all coefficients were misaligned to > the samples. With Avalon ST,clock enablewould be held low until > enough input samples were available, which could therefore exercise > this bug. > > Our IP group strongly recommends upgrading to version 7.1 of theFIR > compiler, which has a more robust coefficient reload. You can > download it from herehttps://www.altera.com/support/software/download/sof-download_center..... > > Hope this helps. > > Regards, > > Vaughn BetzAltera The problem exists for both programmable and fixed coefficient filters in version 7.1 of the FIR compiler.Article: 119337
Oh dear smoke is bad huh... Hmm it is the chip that burned, on the outer casing. I cant really see any hole on the chip so I kind of hope (hope) that everything is fine and that only because it got too hot for the casing that it burnt and gave off smoke. well I could program successfully into using IMpact though...right? "Antti" <Antti.Lukats@googlemail.com> wrote in message news:1179307626.982562.103320@n59g2000hsh.googlegroups.com... > On 16 Mai, 11:10, "Ken Soon" <c...@xilinx.com> wrote: >> ok... I guess i better start small anyway since I really new to this. >> Well I'm going to take a DSP module in school soon so it will definitely >> help me along. > [] >> Oh by the way, can I ask if that once i kind of burn the chip and little >> smoke came off, is the chip spoilt? The board's power indicators are fine >> and I programmed successfully into the chip through a parallel IV cable >> but >> nothing was displayed though. No self-test or whatsoever is available >> though...so scared... >> >> "Paul" <pauljbenn...@gmail.com> wrote in message >> >> news:1178889638.696406.114280@h2g2000hsg.googlegroups.com... > > yes, smoke is rather bad usually :( > > when really visible smoke comes, its usually really some dead things > on board already, possible plastic housing cracked or some trace > burned. > sometimes before smoke comes you can feel with the nose, that > something smells like hot, in that case the damage may be not fatal. > real smoke is usually fatal. > > the only hope that the damage is reversible is if there was some PCB > trace burned (and all chips are ok), but the PCB trace burn doesnt > make smoke, only some bad smell and sometimes visible light for short > time. oh well depend on PCB and power supply, I guess PCB tracks can > make smoke also.. > > as soon as something burns, better take immediate visual and smell > observation, to see what burned, if PCB looks burnt, or if some IC has > plastic cracked on top (reverse volcano where waporized silicium comes > out).. > > Antti > http://code.google.com/p/s3astarter/ >Article: 119338
I'm using Fusion Family and the chip is AFS600,
the message provided by the compiler after synplify synthsized the
architecture is
ERROR: CMP601: this design has a CLKSRC instance 'clock_dif_inst/
CLK_inferred_clock/U_CLKSRC' driven by a clock net wich is not needed.
Befor compiling this design, this macro
must be removed from the design.
i need this macro so i can t remove it!!!
So if synplify can be reconfigured to consider some signals as
essential and others not, how can i do it?
PS: I'm using libero environment with synplify 8.4 i m using default
setting,
Regards,
Amine.
On 16 mai, 04:37, Alan Myler <amy...@eircom.net> wrote:
> Amine.Mi...@gmail.com wrote:
> > Hi
>
> > i'm developping an architecture using Libero and Actel FPGA, i had a
> > problem with global ressources, I had 8 global ressources and the
> > FPGA contains only 6, is there any way to oblige the compiler to not
> > consider some signals as global ressources,
> > synthesysing tool used: Synplify,
>
> > regards,
> > A.
>
> The simply answer is yes. But first perhaps you can expalin what you
> want to use the global resources for? If you want 8 clocks for exampe
> then you will need to consider what Synplify will synthesise instead of
> a global buffer.
>
> What Actel family are you using?
>
> Alan
Article: 119339Currently using this board. however I kind of feel that the documentation in using the board is abit too brief http://www.inrevium.jp/eng/x-fpga-board/index.html For example, I do not know how to set the clock frequency based on the PLL set switches. not to mention the user set, spi set Furthermore, the DVI RX option board also do not have any documention on the 4 Jumper settings (OCK,STAG...) so is it just me or they need to provide more information? KenArticle: 119340
Each pin has a fixed 50 Ohm resistor to its Vcc. Each differential pair shares a common constant current sinking circuit of ~10 mA A transistor connects the pin to the constant current, and the two pins in a complementary pair are driven in counter-phase, only one is on at any time. The swing per pin is thus 500 mV (down from Vcc), the differential swing is 1000 mV peak to peak, and the common mode voltage is (Vcc minus 250 mV). Peter Alfke, from home On May 16, 6:28 am, Test01 <cpan...@yahoo.com> wrote: > As per my understanding, Virtex5 GTP output supports CML standard. May I know the Common mode voltage and differential voltage from the Xilinx FPGA? > > Test01Article: 119341
On May 16, 6:11 pm, Gabor <g...@alacron.com> wrote: > On May 16, 6:57 am, mohan <kulka...@math.net> wrote: > > > I am using max 7000s series cpld.i am using altera byte blaster cable. > > i am getting error as "unable to scan device chain .cann't scan jtag > > chain". > > what is meaning of this error? > > what i need to do,to programme CPLD > > This message indicates that the byte blaster hardware is unable > to determine the devices in your chain. The chain is a loop > going from the byte-blaster to TDI of the first device, > through that device to its TDO to TDI of the next device ... > finally back to the byte-blaster from the last TDO. Usually > the message means there is a mis-connection somewhere > or a device that is missing power. The mis-connection > may also be in one of the bused signals, TMS, TCK. > > I'm not familiar with the byte blaster as I generally work > with Xilinx or Lattice, but there could also be an issue > of power getting to the byte-blaster itself or an issue > with its connection to your computer. The error > message is not very specific. > > HTH > Gabor I am having a doubt,if the altera cpld is jtag compatible,can i use xilinx parallel IV cable to programme altera device using quartus II tool?Article: 119342
On May 16, 6:28 am, Test01 <cpan...@yahoo.com> wrote: > As per my understanding, Virtex5 GTP output supports CML standard. May I know the Common mode voltage and differential voltage from the Xilinx FPGA? This is my third attempt to post the answer: Each pin has a 50 Ohm resistor to its Vcc Each pin has a transistor connecting the pin to a 10 mA constant- current pull-down. The two complementary pins share a common constant current, and the two transistors are alternatingly driven on or off. Result: 500 mV swing per pin, 1000 mV peak to peak for the pair Common mode voltage is (Vcc minus 250 mV) Peter Alfke, from homeArticle: 119343
i am using altera cpld.using quartus 2 tool to programme it through byte blaster cable. I have installed drivers for the cable.made connections intact. i am getting error as "Unable to scan device." My assusmption was may be because of loose contacts this error was coming.but connections are intact.supply are proper,still i cann't programme cpld. is there any possibility of jtag port of cpld being damaged? i had programmed the cpld through the same method.but today i am not able to programme it,nor erase cpld.what the functionality cpld do have stored in it,still there. waiting for some suggestions. Thanks MohanArticle: 119344
Hey everyone, As an assignment for a course in my CS degree, I have to build a D latch, a D flip flop and a 1 bit register with VHDL. I have been given the "process" versions of those and I have to rewrite them using elementary gates and feedback connections. My teachers are not really profficient in the topic (sadly) but we are going through hoops to get stuff working. I have read on several pages that because of limitations in VHDL simulations, basic sequential circuits such as the latch/ff should not be implemented with gates but using processes instead. We are sure that the circuits we described using the component-based approach in VHDL correctly mimic the hardware versions of those. Still, behaviours are erratic and GHDL is giving away cryptic "stop- delta" compilation errors that we can't fix. This appears to be somewhat confirmed by the fact that this page (the only one I've been able to find that provides a gate-based implementation of latches and ffs) does it with some obscure library reference that I have not available (lsi_10k) and a complicated definitions instead of usual signaling and port mapping with and's and not's. http://esd.cs.ucr.edu/labs/tutorial/dff_gate.vhd Feel free to browse through the code by checking out with anonymous SVN: $ svn checkout http://orga1-2007.googlecode.com/svn/trunk/tp1/ orga1-2007 You can then run "make tb_reg1bit" and examine the resulting VCD to see what's going on. I am using this version at home, but the same problems arise with the debian etch versions at my college: GHDL 0.26 (20070408) [Sokcho edition] Compiled with GNAT Version: 4.1.220061115prerelease My knowledge of VHDL is very close to nil and documentation appears very sparse on the web. I could really use some help, so thanks in advance for reading. GonzaloArticle: 119345
On Wed, 16 May 2007 16:19:40 +0000 (UTC), Matthew Hicks <mdhicks2@uiuc.edu> wrote: >Regenerate the linker script and try again. > > >---Matthew Hicks > > <...> >> >> Is there any constraint regarding the number of Ethernet MAC that you >> can place on the OPB Bus? I have attempting to put 2 MACs on the Bus, >> but as soon as a instantiate the second MAC and attempt to generate >> bitstream, I get the following error: address space overlap! This >> error is generated by PlatGen >> >> I am certain address overlap that this is not the problem , because I >> have gone through the entire address map of my system. No two >> peripherals are assigned the same address space. >> <..> I don't think regenerating the linker script will work, it has nothing to do with PlatGen! I have tried it, and the problem seems to lie within the opb_ethernet core itself. It will not allow me to instantiate neither one nor two of them. In fact, every core instantiated has an address overlap with itself! The problem arises when connecting both MSOPB and SOPB, i f you only connect SOPB *or* MSOPB there is no address overlap. I had the same misunderstanding the firts time I tried: I thought MSOPB was only the master part, but it is both parts of the bus at the same time! Best regards, ZaraArticle: 119346
On 2007-05-16, <steve.lass@xilinx.com> <steve.lass@xilinx.com> wrote: > The main complaints we get on Impact have to do with people using the > many variants of Linux. Our current plan is to look into using the Linux > USB driver to address this. That is a great initiative and will solve quite a lot of problems I think. Anyway, you might also want to consider getting rid of WinDriver in Windows since having WinDriver installed probably leaves a wide security hole open. (If you have WinDriver installed a normal user is able to read/write to I/O space. If a malicious user had the necessary skill he could write a program which used DMA to read and write kernel memory and therefore do basically whatever he would want to. To be fair, I have only tested this in Linux, not Windows. If you want someone at your side to look into this for Windows there are more details available in an old posting on comp.arch.fpga: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/c945923560a4f980/5e6f642056b3f0fb?lnk=st&q=group%3Acomp.arch.fpga+windriver+security+hole&rnum=1#5e6f642056b3f0fb ) /AndreasArticle: 119347
Hi to all ............ Now i am in to developing DDR2 memory contoller with STRATIX II EP2S 180 . Is there mega core which can support burst length 8 ?I found only burst lenth 4 controllers. So i have written and no problem with code. I am using DDIO bidirectional mega function for data path to send and receive data on both edges . But problem is so many set up and Hold time violations with this mega function . Has any body developed own memory controller for BURST LENTH 8 . please help me regarding this .......... thanks and regrads sudhakarArticle: 119348
austin wrote: > Yes, to get the right amount of smoke into each transistor is incredibly > difficult! When discussing the way semiconductors *really* work (magic smoke) with friends years ago, the question arose: What is the difference between a 3.3V 1A regulator and a 3.3V 2A regulator? Almost everyone guessed that it was how much smoke is inside the regulator, but that is not correct.Article: 119349
"Peter Alfke" <peter@xilinx.com> wrote in message
news:1179338672.962130.258540@h2g2000hsg.googlegroups.com...
> Maybe this is a homework question, but I took it as a challenge.
>
> I can solve it with one 4-input LUT driving a flip-flop, clocked in
> the slow domain.
> The LUT inputs are: the incoming pulse, the slow clock, the LUT
> output, and the flip-flop output.
Nice - although this pre-supposes that the source clock domain is faster
than the destination clock domain. So the next exercise is to generalise the
circuit to cope with any arbitrary clock ratio. :-)
> Well, I do not know why anybody wants such a circuit, but it
> did exercise the grey cells...
I've found this sort of circuit useful when a circuit in one clock domain
needs to tell a circuit in another clock domain to start (or stop) doing
something, but only infrequently. For example, the pixel-generating portion
of a video circuit might want to inform the frame-buffer reader of the start
and end of a line or a frame. In such a situation, asynchronous FIFOs and
complicated synchronization logic are usually overkill.
-Ben-
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