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Hi everyone, I want to design a model with my Smt338. This is a Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16 as DDR memory. First of all I need to implement the hardware architecture, so I use edk 8.1 (or edk 8.2) to create a model with PowerPC and this DDR memory. In the ucf I map every port, but I have not any pin to DDR_CLK, that is, the feedback ddr clock. This is the loc entry: Net fpga_0_GEN_DDR_CLK_FB LOC=; What can I do?. Perhaps I could use a DCM_module but I don't know how could I implement it. RegardsArticle: 119651
Frank Buss wrote: > Jim Granville wrote: > > >>What sort of core are you looking at doing ? > > > Needs not to be fast, 8 bit registers and 16 bit address space is enough. > Should be possible to use internal block RAM and to memory map special > locations for accessing hardware, but should be small. It will be used in > an FPGA, which is mounted as an extension board to another system, > connected by I2C, which has some more VHDL code for accessing some other > chips. The core should implement the control logic for interpreting I2C > commands for accessing the other chips and providing the result. > > >>Why not look at the Mico8 and Mico32 from lattice, and contribute to >>that. That is fully opensource, and legal problem free. >>You could do a MicoFB, with your pet features... ? > > > I would like to have a C compiler for it, too. The cc65 compiler for the > 6502 looks very mature and feature rich and I already know the 6502 > instruction set very well (as an old C64 demo programmer :-) , if I need to > implement something in inline assembler, so this was the reason why I think > it would be a good choice. > > I didn't found a C compiler on the mico8 page: > > http://www.latticesemi.com/products/intellectualproperty/referencedesigns/8bitmicrocontrollermico8.cfm Yes, 6502 is mature and well supported. Have you compared the FPGA resource usage of the 6502 core, and the Mico32 ? Also, look up the PicoBlaze C compiler - recently moved I think ? -jgArticle: 119652
Hi,
I was hoping that someone could point me at a useful document or other
link.
Our FPGA build flow is currently scripted for a single iteration P&R.
Unfortunately, we are now starting to get some hold violations.
If I run a multipass P&R, approximately 50% of the iterations will
yeild successful timing (Timing Score = 0).
Ideally, what I want is a method of saying : Iterate until timing met,
with a maximum of n
What I get is n P&R'ed design files. Is there a simple method of
identifying which of these designs met timing (via a CSH script).
FYI, the (CSH) command line I am using is:
par -intstyle xflow -n $Num_Iterations -w -xe c -ol high -ub
des.ncd des.dir des.pcf
Any suggestions ?
Thanks in advance,
Steven
Article: 119653On 23 May 2007 22:57:24 -0700, sudhakarmvs@gmail.com wrote: >Hi to all > >I am currently working on DDR2 controller for Burst Lenth 8. >My own code is giving good results when i verified with memory model >from MICRON. >Now my problem is memory on the board is not sending 4 DQS clock >pulses. it seems to be sending for burst lenth 4. > What are you writing to the DDR's mode registers? - BrianArticle: 119654
aftr par also u rgetting the same ??? let me think.... ok put it this way..... 64 bit + 1 bit -> needs one 64 bit carry propagation network.... Above result + 1bit -> needs one more 64 bit carry propagation network. like that.... but suppose.... 1bit + 1bit -> needs only two bit carry propagation network 64 bit + 2bit -> needs 63 bit carry propagtion network.... so second one is more efficient..... i am neglecting all the additions since its all two or 1 bit additions..... Any way i did not felt the power of this grouping neither do i carefully read the johnH first reply.... Sorry..... so i think in a single strecth addition the evaluation is from left to right.... ur case (in1+in2+in3+in4) ==> ((2bit + 2bit) + 64bit) + 1bit...... need two 64 bit carry chains........ try to change that order to in1 + in2 + in4 + in3; ..... also dont forget to test in3+ in4 + in2 + in1;.......... i think tht will give the maximum value.... pls test it and pls let me know... as u knw its been more than two months since i last touched the ISE.... one mre thing.... Where r u using this concepts.....???Article: 119655
I think you can monitor the des.par file created next to the des.dir
directory.
It gives you something like:
Constraints file: ../map/rmpl_4.pcf.
Level/ Design Timing Number Run NCD
Cost [ncd] Score Score Unrouted Time Status
---------- ------ -------- -------- -----
------------
H_S_2 * 215636 262882 0 31:23
Complete
H_S_3 * 265943 228477 0 40:51
Complete
...
* : Design saved.
It seems to be updated after each run. I think I was using ISE 7.1 at
the time.
Once you find "design score" or "timing score" (see xilinx AN3749)
equal to zero
you can kill the par process and use the working one.
I also tried to run multipar with high placer effort (-pl high) but
lower routing effort (-rl std)
to find the best place result, then reroute (par -k) this with higher
routing effort (-rl high).
I used this script to parse the .par file (hope it still works):
# This script returns the path to the "best" result from mppr. Lower
Design score is better.
# Only look at files which have a "*" (design saved) and NCD status
complete.
# $1 is the mppr.par file to parse, $2 is the ranking to use, default
is 1 (i.e. best)
# $1 also hints about the directory due to xilinx's naming convension.
file=$1
result_dir=$(echo $file | sed -e "s/\.par/\.dir/")
if [ "$2" = "" ]; then
rank=1
else
rank=$2
fi
best_result=$(cat $file | grep "\\*" | grep "Complete" | sort -n -k3 |
sed -ne "${rank}p" | sed -e "s/[ \t].*$//")
echo "${result_dir}/${best_result}.ncd"
#last line
Article: 119656Patents is not just about how to implement things but also methods and ideas on how to solve things. You can do patent without ever implementing anything. So just doing a clean-room implementation is not something that will get you free from any patents violations. I doubt that you can patent ISA but you can patent ideas that prohibit others from doing something that will execute the same machine code. MIPS had their patent on how to handle unaligned memory accesses which was tied into instructions. I think they used it when they went after MIPS clones. ARM has the shadow register handling during interrupts patent which makes it hard to do an usable ARM clone without violating that patent. I think ARM also have some other patents, I never bother to investigate what patent they have and when they expire. There should be some patents from the early 80s when Acorn(ARM) did the first ARM1 core that should expire soon. Since most of the stuff in ARM7 is coming from the early version of ARM cores. But there is nothing to stop them from suing you even if you don't violate any patents since an free ARM clone would be something that they want off the market. Just that you are under a lawsuit would tied you down so you in the end will remove the clone from the market. I remember meeting one of the 6502 architecture guys in 2000 and he claim to me that he had legal rights to 6502 and that he could sue 6502 clone makers. I have no idea how valid his claim was or if the patents has expired. In most cases if you do something for yourself and keep it for yourself, I think you are "free" to do anything you like since nobody will bother to sue you. If you start doing products with it and the revenue is starting to come in then I think you better be sure that you not violating anything. Göran Bilski "Frank Buss" <fb@frank-buss.de> wrote in message news:aa9l1v670c7t$.p4ydabe8duh4.dlg@40tude.net... > I've found a 6502 core at http://www.sprow.co.uk/fpgas/free6502.htm , > which > is based on a version from free-ip.com, which looks like it turned into an > advertising site, but I've found the original page at > > http://web.archive.org/web/20040603222048/www.free-ip.com/6502/index.html > > Under "Legal Stuff" it says "Currently, there are no known patents or > copyrights that cover this implementation of the 6502 CPU.". > > But I wonder if MOS Technology or the successor companies has some > copyrights for the 6502 architecture and if it is allowed to use it, > without licence fees, in own designs. > > What are the general licensing issues for CPU cores? Is it possible to > require licence fees for a CPU architecture or only for a CPU core, e.g. > for a EDIF netlist? Can I create and use a cleanroom implemenation of a > CPU > architecture without legal problems? > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.deArticle: 119657
Thank you for providing this information. Test01Article: 119658
Although Altera's Quartus II is officially only supported on (by now) rather old Linux releases (SUSE Enterprise Linux 9, Red Hat Enterprise Linux 3 and 4), up to Quartus 7.0, it also used to work quite well in practice on more recent distributions (openSUSE 10.2, Fedora Core 6, etc.). However, the new Quartus 7.1 fails badly on both openSUSE 10.2 and Fedora Core 6. It only opens (after the brief splash message) its main window and then immediately aborts with this "Internal Error" pop-up: *** Fatal Error: Segment Violation at 0x28, Module: quartus 0xFDA8D : FontDrawCharset::bInit(tagLOGFONTA*) + 0x22D (gdiuser32) 0xFF0AF : fontcache::GetNewFontDraw(tagLOGFONTA*, tagXFORM*, int, unsigned long, unsigned long) + 0x21F (gdiuser32) 0xFF347 : fontcache::FindOrCreateFontDraw(tagXFORM*, CW_DC*, tagLOGFONTA*) + 0x197 (gdiuser32) 0xFF50F : fontcache::FindOrCreateFontDraw(CW_DC*, tagLOGFONTA*) + 0xBF (gdiuser32) 0x101DD2 : fontcache::EnumFontsA(CW_DC*, tagLOGFONTA*, int (*)(tagLOGFONTA const*, tagTEXTMETRICA const*, unsigned long, long), long, int) + 0x432 (gdiuser32) 0x103353 : MwEnumFontsTT + 0x43 (gdiuser32) 0xC4562 : EnumFontFamiliesExA + 0x132 (gdiuser32) 0x26AFDE : GX_FONT_STATE::GX_FONT_STATE() + 0x2CE (og903as) 0xDD285 : GX_APP_STATE::GX_APP_STATE() + 0xD5 (og903as) 0xDE290 : GXGetAppState() + 0x90 (og903as) 0x11C3C1 : GXInit(unsigned int, CGXAbstractControlFactory*, char const*, char const*) + 0x21 (og903as) 0xDF4C6 : GXInit(unsigned int, char const*, char const*) + 0x46 (og903as) 0x3CD36 : resr_oaw_DllMain + 0x194 (resr_oaw) 0xB48E7 : Mw___resr_5foaw_wrapDllMain + 0x2B (resr_oaw) 0xE8EC1 : MwDllInPostConstruct + 0x71 (kernel32) 0xB4D2C : _Initializerresr_5foaw::construct() + 0x22 (resr_oaw) 0xB4A7E : _Initializerresr_5foaw::_Initializerresr_5foaw() + 0x9A (resr_oaw) 0xB4DCF : (resr_oaw) 0xB4E16 : (resr_oaw) 0xB4F45 : (resr_oaw) 0x375D9 : (resr_oaw) 0xE3E3 : (ld-linux.so.2) 0xE4F3 : (ld-linux.so.2) 0x11FF6 : (ld-linux.so.2) 0xE026 : (ld-linux.so.2) 0x11929 : (ld-linux.so.2) 0xD2D : (dl.so.2) 0xE026 : (ld-linux.so.2) 0x11DC : (dl.so.2) 0xC64 : dlopen + 0x44 (dl.so.2) 0xEB6BE : UnixLoadLibrary(CW_Instance*) + 0x5E (kernel32) 0xEA720 : (kernel32) 0xEA885 : LoadLibraryA + 0x35 (kernel32) 0xB1C0E : AfxLoadLibrary(char const*) + 0x2E (mfc400s) 0x181C8AB : afc_load_library + 0x1D (quartus) 0x73AE : thr_drl_native_load + 0x43 (ccl_thr_win32) 0x800A : thr_drl_load_internal + 0x76 (ccl_thr_win32) 0x8299 : thr_drl_load + 0xBA (ccl_thr_win32) 0x1806211 : AFC_TEMPLATE_MANAGER::load_template(AFC_DOC_INFO const*) + 0x62B (quartus) 0x10702ED : PJM_MAIN_FRAME::on_open_oaw(unsigned int) + 0xD5 (quartus) 0x111958 : _AfxDispatchCmdMsg(CCmdTarget*, unsigned int, int, void (CCmdTarget::*)(), void*, unsigned int, AFX_CMDHANDLERINFO*) + 0x218 (mfc400s) 0x111A77 : CCmdTarget::OnCmdMsg(unsigned int, int, void*, AFX_CMDHANDLERINFO*) + 0xC7 (mfc400s) 0xD21CB : CFrameWnd::OnCmdMsg(unsigned int, int, void*, AFX_CMDHANDLERINFO*) + 0x8B (mfc400s) 0x26836E : SECMDIFrameWnd::OnCmdMsg(unsigned int, int, void*, AFX_CMDHANDLERINFO*) + 0x16E (ot803as) 0xCE8E5 : CWnd::OnCommand(unsigned int, long) + 0xB5 (mfc400s) 0xD0DF9 : CFrameWnd::OnCommand(unsigned int, long) + 0x69 (mfc400s) 0x26816F : SECMDIFrameWnd::OnCommand(unsigned int, long) + 0x6F (ot803as) 0x1829D52 : AFC_MDI_FRAME::OnCommand(unsigned int, long) + 0x42 (quartus) 0xCB3CF : CWnd::OnWndMsg(unsigned int, unsigned int, long, long*) + 0x2CF (mfc400s) 0x108277F : PJM_MAIN_FRAME::OnWndMsg(unsigned int, unsigned int, long, long*) + 0x85 (quartus) 0xCAD59 : CWnd::WindowProc(unsigned int, unsigned int, long) + 0x39 (mfc400s) 0x269014 : SECMDIFrameWnd::WindowProc(unsigned int, unsigned int, long) + 0x64 (ot803as) 0xCF623 : AfxCallWndProc(CWnd*, HWND__*, unsigned int, unsigned int, long) + 0xC3 (mfc400s) 0xD00C3 : AfxWndProc(HWND__*, unsigned int, unsigned int, long) + 0x53 (mfc400s) 0xC7E9B : AfxWndProcBase(HWND__*, unsigned int, unsigned int, long) + 0x5B (mfc400s) 0x1809F1 : MwCallCallWndProc + 0x171 (gdiuser32) 0x18C57A : MwICallWindowProc + 0x7A (gdiuser32) 0x1989B6 : CallWindowProcA + 0x66 (gdiuser32) 0x10956EB : CSubclassWnd::WindowProc(unsigned int, unsigned int, long) + 0x9F (quartus) 0x1092FDF : CCoolMenuManager::WindowProc(unsigned int, unsigned int, long) + 0x199 (quartus) 0x1095829 : HookWndProc(HWND__*, unsigned int, unsigned int, long) + 0xF1 (quartus) 0x1809F1 : MwCallCallWndProc + 0x171 (gdiuser32) 0x18D841 : MwIDispatchMessage + 0xA1 (gdiuser32) 0x18D9FA : DispatchMessageA + 0x4A (gdiuser32) 0x12BFED : CWinThread::PumpMessage() + 0x7D (mfc400s) 0x12BAEA : CWinThread::Run() + 0x8A (mfc400s) 0x12DB59 : CWinApp::Run() + 0x29 (mfc400s) 0x182300A : AFC_APP::Run() + 0x160 (quartus) 0xDC2ED : AfxWinMain(HINSTANCE__*, HINSTANCE__*, char*, int) + 0xAD (mfc400s) 0x4496B83 : WinMain + 0x53 (quartus) 0x10C5DEF : main + 0x9D (quartus) 0x15F9C : __libc_start_main + 0xDC (c.so.6) 0x101F311 : (quartus) End-trace Has anyone already found a workaround (other than using an older OS, e.g. CentOS 4.5 works fine)? Markus -- Markus Kuhn, Computer Laboratory, University of Cambridge http://www.cl.cam.ac.uk/~mgk25/ || CB3 0FD, Great BritainArticle: 119659
Antti <Antti.Lukats@googlemail.com> writes: |> I wonder a bit that the 100 USD target price goal have not met - as I heard |> there is serious project to develop a mobile phone with sub 10 USD |> manufacturing costs ! Perhaps because that project might in the end also not get below 15 USD?Article: 119660
vssumesh wrote: > and subin i didnt observed the last question...... > what should be the real approch to write in HDL to get most optimised > result. > How can one suggest a general method or guideline for coding.... i > think we can classify it as two separate class.... > 1) general functionalities.... like addition,multiplication,muxing > etc... i think here we need to code them as direct as u done in the > first code.... all the synthesizers i hope will have algos to deal > with that... so no ponit in creating something like 2nd or 3rd coding > style.... tht looks nt good in the HDL itself.... > 2) The other things are unconventional functionalities... like what we > implemented in the source formatin switching logic.... we know what to > do but no machine can translate direct to the optimized HW... so what > we do we also think abt it and find a way to implement it and code it > that way..... > I think when we are coding somrthing we need to differentiate between > these two class... You appear to be responding to posts and not asking questions so the ability for others to read your message is less important, perhaps. Do you want others to actually read what you say? I read through your previous post and had sincere trouble following along due to the abbreviations and lack of sentence/paragraph structure. Since you're not asking a question here, I'm just not reading the post. If you don't care if your messages are read, you don't need to do anything at all. If you'd like to be part of the grand conversation, you will get more people to see what you're saying if you stick to a good written style. Scanning this message that I didn't read, it looks like there are fewer texting-style abbreviations. Great start. Avoid all the dots in your thoughts trailing off and instead use solid sentence structure and formatted paragraphs and your message will be inherently more readable. I appreciate the interaction from most of the folks on this board (I only have one author on my kill list at this point - so much nicer that way) and would like to see the conversation open and not ignored. I'm just making a recommendation here, no demands. Your posts today are simply the most difficult to read in the last several months. Otherwise, thanks for the contributions.Article: 119661
On May 24, 8:11 am, pontus.stenst...@gmail.com wrote:
> I think you can monitor the des.par file created next to the des.dir
> directory.
> It gives you something like:
> Constraints file: ../map/rmpl_4.pcf.
>
> Level/ Design Timing Number Run NCD
> Cost [ncd] Score Score Unrouted Time Status
> ---------- ------ -------- -------- -----
> ------------
> H_S_2 * 215636 262882 0 31:23
> Complete
> H_S_3 * 265943 228477 0 40:51
> Complete
> ...
> * : Design saved.
>
> It seems to be updated after each run. I think I was using ISE 7.1 at
> the time.
> Once you find "design score" or "timing score" (see xilinx AN3749)
> equal to zero
> you can kill the par process and use the working one.
>
> I also tried to run multipar with high placer effort (-pl high) but
> lower routing effort (-rl std)
> to find the best place result, then reroute (par -k) this with higher
> routing effort (-rl high).
>
> I used this script to parse the .par file (hope it still works):
>
> # This script returns the path to the "best" result from mppr. Lower
> Design score is better.
> # Only look at files which have a "*" (design saved) and NCD status
> complete.
> # $1 is the mppr.par file to parse, $2 is the ranking to use, default
> is 1 (i.e. best)
> # $1 also hints about the directory due to xilinx's naming convension.
> file=$1
> result_dir=$(echo $file | sed -e "s/\.par/\.dir/")
>
> if [ "$2" = "" ]; then
> rank=1
> else
> rank=$2
> fi
>
> best_result=$(cat $file | grep "\\*" | grep "Complete" | sort -n -k3 |
> sed -ne "${rank}p" | sed -e "s/[ \t].*$//")
>
> echo "${result_dir}/${best_result}.ncd"
>
> #last line
I'm not sure if they fixed the bug in 8.2, but in older versions
of ISE, the results for multipass place & route did not necessarily
correspond to the single-pass results for the same cost table entry.
In any case if you're using a script to run place&route, why not let
the script handle multipass using the -t command line argument to
set the cost table entry on each pass. Also many times you get better
results by using the timing option for map. In this case you'll
find that multipass place&route doesn't help much because it starts
from a more completely mapped design. A script could re-run map
and place&route with a new cost table entry each pass, then look
at the report file as mentioned to decide when to stop.
HTH,
Gabor
Article: 119662subint wrote: > Thanks for all of the replies, > John you are completely right.. it was because of the grouping > of the adders making the difference.But how?... > why the out=a+b+c+d is not equal to out = (a+b+c)+d; <snip> The grouping was once (back in the early 90s, at least by some tools) specifically order-dependent. Since the language became a standard and more synthesizers got better optimizations, the order of operations and the implied grouping with parenthesis no longer make the impact on synthesis one might hope in trying to optimize the code. Since the synthesizers believe they can do a better job by looking at the entire logic cone, the synthesis results *should* be the same independent of order. The arithmetic elements are one example where it appears the synthesizer optimizations are "a little behind" where we'd want them to be. I *often* have syn_keep attributes around the adders in my code to make sure the proper "minimum" amount of logic goes into my adder and the register-to-register flow doesn't get broken up improperly. Because the synthesis is based on the logic cone and not the way the equations are grouped, the use of parenthesis or additional temp wires will often affect the result little. Some, but little. Knowing the silicon and checking slow or "large" simulation results (with the timing analysis and area reports, respectively) you can often find where the synthesis "goes wrong" and focus on the syn_keeps to reign the synthesizer back in. Often if you don't hit a time or area problem, these sub-optimal results are fine: the results are the same with just a little more power wasted in a part that still isn't full. I like to optimize things so I can reuse my code later in different target systems and still get decent performance so I see a bunch of the missteps from synthesis. Luckily I haven't spent much time outside the one synthesizer so I haven't had to deal with the different moods of different tools. Some days it can feel like a challenge, but who are we to step down from a challenge?Article: 119663
On May 24, 6:56 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > Patents is not just about how to implement things but also methods and id= eas > on how to solve things. > You can do patent without ever implementing anything. > So just doing a clean-room implementation is not something that will get = you > free from any patents violations. > > I doubt that you can patent ISA but you can patent ideas that prohibit > others from doing something that will execute the same machine code. > MIPS had their patent on how to handle unaligned memory accesses which was > tied into instructions. > I think they used it when they went after MIPS clones. > ARM has the shadow register handling during interrupts patent which makes= it > hard to do an usable ARM clone without violating that patent. > I think ARM also have some other patents, I never bother to investigate w= hat > patent they have and when they expire. > There should be some patents from the early 80s when Acorn(ARM) did the > first ARM1 core that should expire soon. > Since most of the stuff in ARM7 is coming from the early version of ARM > cores. > But there is nothing to stop them from suing you even if you don't violate > any patents since an free ARM clone would be something that they want off > the market. > Just that you are under a lawsuit would tied you down so you in the end w= ill > remove the clone from the market. > > I remember meeting one of the 6502 architecture guys in 2000 and he claim= to > me that he had legal rights to 6502 and that he could sue 6502 clone make= rs. > I have no idea how valid his claim was or if the patents has expired. > > In most cases if you do something for yourself and keep it for yourself, I > think you are "free" to do anything you like since nobody will bother to = sue > you. > If you start doing products with it and the revenue is starting to come in > then I think you better be sure that you not violating anything. > > G=F6ran Bilski > > "Frank Buss" <f...@frank-buss.de> wrote in message > > news:aa9l1v670c7t$.p4ydabe8duh4.dlg@40tude.net... > > > > > I've found a 6502 core athttp://www.sprow.co.uk/fpgas/free6502.htm, > > which > > is based on a version from free-ip.com, which looks like it turned into= an > > advertising site, but I've found the original page at > > >http://web.archive.org/web/20040603222048/www.free-ip.com/6502/index.... > > > Under "Legal Stuff" it says "Currently, there are no known patents or > > copyrights that cover this implementation of the 6502 CPU.". > > > But I wonder if MOS Technology or the successor companies has some > > copyrights for the 6502 architecture and if it is allowed to use it, > > without licence fees, in own designs. > > > What are the general licensing issues for CPU cores? Is it possible to > > require licence fees for a CPU architecture or only for a CPU core, e.g. > > for a EDIF netlist? Can I create and use a cleanroom implemenation of a > > CPU > > architecture without legal problems? > > > -- > > Frank Buss, f...@frank-buss.de > >http://www.frank-buss.de,http://www.it4-systems.de- Hide quoted text - > > - Show quoted text - I doubt you have much to worry about regarding patents on the 6502 core architecture. First of all, as has already been pointed out, the patent applies only to the implementation, specifically, HDL, netlists, etc. Since they used no hdl back in '74//'75, I believe you're on sound footing. However, the free-IP implementation of 6502 was (a) incomplete and (b) not very much like the physical implementation of the 6502. Further, you'd probably want to implement something that actually implemented the R65C02 instruction set, as that was the richest and most powerful. In order to make it both physically small and fast, you'll probably want to implement it such that it uses the ALU for both data and address arithmetic and uses transparent latches rather than clocked registers. It would use RAM instead of flipflops for those registers, and probably would implement its BCD operations by means of redundant registers rather than a deeper (and therefore slower) ALU. That way you avoid all the delays associated with wide synchronous counters. That way you can focus on an efficient 8-bit ALU rather than wide counters, since the 650x core always allowed two cycles for instructions that incremented the PCH. Take a close look at that 'C' compiler, BTW, as you'll find it not very simple to implement independently of its console/video-related requirements. Richard Erlacher Erlacher Associates Denver, COArticle: 119664
stefan.elmsted@gmail.com wrote: > Hi > > I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat) > cable with a characteristic impedance of 173R balanced (103R > unbalanced). > I have tried xilinx webcase to answer on the termination requirements > of LVDS for spartan 3 withhout much luck. I got 2 different answers. > > My questions are: > > 1) Can I use a ribbon cable with 173R balanced characteristic > impedance? I have read that it should be 100R. The transmission is > rather short, 300mm and relative slow in lvds terms. I would rather > not switch the cable since it have other good properities that I rely > on. > > 2) With the above cable should the receiver end termination still be > 100R > > 3) With the above cable is a source resistor network necessary to > match the impedance on the transmitter side and lower reflections? > This is the point where xilinx tend to confuse itself in its > datasheets for spartan 3. My dirty solution with adding 150R series > resisor tend to give nicer signals. > > Hope someone could help me on this. > > Thanks in advance The receiver should be the differential impedance of the cable and of the transmitter - they should all (roughly) match. If you have an external termination at the receiver, change it to the 173 ohm value if that's the true differential impedance. If the termination is internal at 100 ohms, add two 36 ohm resistors (or thereabouts) to get the impedance match, albeit at a reduced signal amplitude. On the transmitter, you want a 100 ohm to 173 ohm impedance match so the transmitter sees 100 ohm but the transmission line sees 173 ohm. You'll need a differential termination on the transmitter side of this network and two series resistors to the ribbon cable. The signal amplitude will again be reduced. If the doubly-reduced signal amplitude is a problem, your slower speed will allow a different approach. Rather than using the native 100 ohm LVDS transmitter, step back a couple years and use a three-resistor network to match 2.5V differential outputs to the LVDS levels and impedances you need. If you analyze the resistor networks used by the Bus-LVDS Xilinx I/O level or some of the older "LVDS" drivers in the various families, you'll find simple 3-resistor networks that make the rail-to-rail drivers look like a transmitter with 100 ohm differential impedance with the right voltage swing. You can alter the network to give you 173 ohms with a voltage swing appropriate to your receiver termination. 173 ohms all the way through make the signal clean at the receiver.Article: 119665
Hi all, is it possible to use Spartan 3 BRAM (on my xc3s1000 it should be 432K) as a ROM memory for data storage or folder mounting under PetaLinux? How to do this under EDK 8.1? Thanks Regards LancerArticle: 119666
All, I suppose suggesting that the question could be answered in less than 10 minutes using a SIGNAL INTEGRITY simulator would just be silly? I am absolutely amazed at how much time, money, and energy is wasted just because a SI simulator is "expensive." One respin of a pcb is MORE $$$ than buying the SI simulator tool. Mentor's Hyperlynx(tm) simulator is my favorite, but Cadence has their tool which might be more to some folks liking (it is integrated with the PCB layout stuff). So, how about it? Invest in something that will save you enough money to pay for it the first time you do not screw up. Submit a hotline webcase, and ask for a "what if" SI simulation. That way you will get a free example of (one) solution to your problem. One comment: matching the transmitter impedance is a good idea, as a perfect match at the receiver is impossible (perfect may happen in textbooks, but not in real life). AustinArticle: 119667
"John_H" <newsgroup@johnhandwork.com> wrote in message news:cUg5i.9206$ix.312@trndny01... > stefan.elmsted@gmail.com wrote: >> Hi > > On the transmitter, you want a 100 ohm to 173 ohm impedance match so the > transmitter sees 100 ohm but the transmission line sees 173 ohm. You'll > need a differential termination on the transmitter side of this network > and two series resistors to the ribbon cable. The signal amplitude will > again be reduced. > You don't _need_ to match both transmitter and receiver. One or the other is good enough, provided the path between the driver and the cable has the same impedance as the cable, or this path is short. Cf. ECL logic, low output impedance, but can drive a properly terminated diff. pair. LVDS outputs are matched to the line to get a belt 'n' braces approach to reduce reflections, but it's not necessary to match the transmitter to the line. Here's an app note which describes the output structures. http://www.maxim-ic.com/appnotes.cfm/an_pk/291 HTH, Syms.Article: 119668
On 24 May, 15:44, Gabor <g...@alacron.com> wrote: > I'm not sure if they fixed the bug in 8.2, but in older versions > of ISE, the results for multipass place & route did not necessarily > correspond to the single-pass results for the same cost table entry. > > In any case if you're using a script to run place&route, why not let > the script handle multipass using the -t command line argument to > set the cost table entry on each pass. Also many times you get better > results by using the timing option for map. In this case you'll > find that multipass place&route doesn't help much because it starts > from a more completely mapped design. A script could re-run map > and place&route with a new cost table entry each pass, then look > at the report file as mentioned to decide when to stop. > > HTH, > Gabor- Hide quoted text - > > - Show quoted text - Hi Gabor, I'm afraid that your post goes beyond the level of my knowledge :-( Can you please clarify what a "Cost Table Entry" is, and how do you select one. Thanks, StevenArticle: 119669
On 24 May, 14:11, pontus.stenst...@gmail.com wrote:
> I think you can monitor the des.par file created next to the des.dir
> directory.
> It gives you something like:
> Constraints file: ../map/rmpl_4.pcf.
>
> Level/ Design Timing Number Run NCD
> Cost [ncd] Score Score Unrouted Time Status
> ---------- ------ -------- -------- -----
> ------------
> H_S_2 * 215636 262882 0 31:23
> Complete
> H_S_3 * 265943 228477 0 40:51
> Complete
> ...
> * : Design saved.
>
> It seems to be updated after each run. I think I was using ISE 7.1 at
> the time.
> Once you find "design score" or "timing score" (see xilinx AN3749)
> equal to zero
> you can kill the par process and use the working one.
>
> I also tried to run multipar with high placer effort (-pl high) but
> lower routing effort (-rl std)
> to find the best place result, then reroute (par -k) this with higher
> routing effort (-rl high).
>
> I used this script to parse the .par file (hope it still works):
>
> # This script returns the path to the "best" result from mppr. Lower
> Design score is better.
> # Only look at files which have a "*" (design saved) and NCD status
> complete.
> # $1 is the mppr.par file to parse, $2 is the ranking to use, default
> is 1 (i.e. best)
> # $1 also hints about the directory due to xilinx's naming convension.
> file=$1
> result_dir=$(echo $file | sed -e "s/\.par/\.dir/")
>
> if [ "$2" = "" ]; then
> rank=1
> else
> rank=$2
> fi
>
> best_result=$(cat $file | grep "\\*" | grep "Complete" | sort -n -k3 |
> sed -ne "${rank}p" | sed -e "s/[ \t].*$//")
>
> echo "${result_dir}/${best_result}.ncd"
>
> #last line
Thanks. This is just the information I was after.
Steven
Article: 119670You can define the BRAM content through configuration, and you can then use the BRAM as a ROM, just by never writing new information into it. But remember: Reading from a BRAM is a synchronous operation. You must supply a clock, and the Data output changes only after the rising edge of the clock. Also, in order to guarantee the integrity of the ROM content, you should not change the addresses during the set-up time window before the clock, while CE is active. (WE inactive is not sufficient to protect against all address set-up time violations). This is not intuitively obvious. Peter Alfke, Xilinx ======================= On May 24, 7:07 am, Lancer <peppe...@gmail.com> wrote: > Hi all, > is it possible to use Spartan 3 BRAM (on my xc3s1000 it should be > 432K) as a ROM memory for data storage or folder mounting under > PetaLinux? > How to do this under EDK 8.1? > > Thanks > > Regards > > LancerArticle: 119671
Symon, Xilinx must recommend the standard, tried and true, solution, we are not allowed to cut corners, as that leads to unhappy customers and lowers our sales figures while customers are trying to fix something they should have gotten right the first time. LVDS is a standard. The transmitter is 100 ohms, the line is 100 ohms, the receiver is 100 ohms. They didn't do it this way because they were stupid: they did it this way for the reason I stated. If you want to do SLVDS (Symon's Low Voltage Differential Signalling) be my guest. Will SLVDS work? Most of the time, probably. The advantage of a standard is "set it and forget it" as there will be no problems unless you have done something wrong (like ignore the transmit match). Should simulate it, though. Another example of this is where customers discover that simple LVCMOS works faster, and with less power to DDR SDRAM chips located close to the FPGA. Do we recommend it? No. Do people make a robust interface, that works just fine in production? Yes. But they have to do more work, to make sure they will be safe across all corners (silicon, voltage, temperature). AustinArticle: 119672
On May 24, 10:26 am, moo...@yahoo.co.uk wrote: > On 24 May, 15:44, Gabor <g...@alacron.com> wrote: > > > > > I'm not sure if they fixed the bug in 8.2, but in older versions > > of ISE, the results for multipass place & route did not necessarily > > correspond to the single-pass results for the same cost table entry. > > > In any case if you're using a script to run place&route, why not let > > the script handle multipass using the -t command line argument to > > set the cost table entry on each pass. Also many times you get better > > results by using the timing option for map. In this case you'll > > find that multipass place&route doesn't help much because it starts > > from a more completely mapped design. A script could re-run map > > and place&route with a new cost table entry each pass, then look > > at the report file as mentioned to decide when to stop. > > > HTH, > > Gabor- Hide quoted text - > > > - Show quoted text - > > Hi Gabor, > > I'm afraid that your post goes beyond the level of my knowledge :-( > > Can you please clarify what a "Cost Table Entry" is, and how do you > select one. > > Thanks, > > Steven If you look in the Development System Reference Guide, it lists all of the command line options for "par" (place&route). The -t option sets the starting "Placer Cost Table". I'm not sure why they call it that (maybe someone from NeoCad can give a hint?) but it is essentially a seed for initial placement. This is the number that is incremented on each pass of multipass place and route. If you don't specify a number it defaults to 1. So in your case: par -intstyle xflow -n $Num_Iterations -w -xe c -ol high -ub is similar to for $iteration = 1 to $Num_Iterations par -intstyle xflow -t $iteration -w -xe c -ol high -ub This runs one place and route pass per loop rather than letting par.exe determine the number of loops. Map, when timing mode is enabled, also allows you to specify the starting placer cost table. This is a newer feature than the 6.1i that I normally work with. I know it's in 9.1i anyway. If you use the GUI, look at the properties for Map and make sure you have advanced properties displayed. The first item is "Perform timing driven packing and placement". If you check this box the settings for effort level and starting placer cost table will be enabled. You'll need to look at the Development System Reference Guide to see how to do this from the command line, or you can run map from the GUI and see the command in the log file. HTH, GaborArticle: 119673
"austin" <austin@xilinx.com> wrote in message news:f34740$6dj2@cnn.xilinx.com... > > One comment: matching the transmitter impedance is a good idea, as a > perfect match at the receiver is impossible (perfect may happen in > textbooks, but not in real life). > > Austin > It is possible to match even Xilinx's hideous 10pF receiver pins. Here's an example from Xilinx's own consultant's website:- http://sigcon.com/Pubs/edn/ConstantRTermination.htm HTH, Syms.Article: 119674
"austin" <austin@xilinx.com> wrote in message news:f348ds$6dj3@cnn.xilinx.com... > Symon, > > Xilinx must recommend the standard, tried and true, solution, we are not > allowed to cut corners, as that leads to unhappy customers and lowers our > sales figures while customers are trying to fix something they should have > gotten right the first time. > > LVDS is a standard. The transmitter is 100 ohms, the line is 100 ohms, > the receiver is 100 ohms. They didn't do it this way because they were > stupid: they did it this way for the reason I stated. > > If you want to do SLVDS (Symon's Low Voltage Differential Signalling) be > my guest. > > Will SLVDS work? Most of the time, probably. The advantage of a standard > is "set it and forget it" as there will be no problems unless you have > done something wrong (like ignore the transmit match). Should simulate > it, though. > > Austin > Did you read the OP's requirement? He's not driving a 100R transmission line, he's driving something with a different charactaristic impedance, 173R. So, the LVDS 'standard' won't work. Terminating the output will reduce his output swing. Are you sure in this application matching the output impedance is more important than a large signal swing? Cheers, Syms. p.s. Simulation is a good plan, I wonder where can you get a decent model for ribbon cable?
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