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"Symon" <symon_brewer@hotmail.com> wrote in message news:f364ua$6pj$1@aioe.org... > "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in > message news:u4pb535aii2c97o28bpi2812ljapqmh9pb@4ax.com... >> > Hi John, > Have a look at the link I posted yesterday. This one:- > http://www.maxim-ic.com/appnotes.cfm/an_pk/291 > It shows the output structure for LVDS. The (12mA) current source has high > impedance, so the output impedance is determined by the resistors show. I > think the LVDS transmitters you mention must have some other type of > structure. Can you post what they were? > HTH, Syms. > > Whoops, forget that, I just read the rest of the thread. Cheers, Syms.Article: 119726
Niv (KP) wrote: > On 24 May, 21:16, Alan Myler <amy...@eircom.net> wrote: > >>Niv (KP) wrote: >> >>>I need to write some timing constraints for an ProAsic device. The >>>Designer tool doesn't seem to cater for what I need; as follows: >>> >>>FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) >>>captures data on the clk falling edge (Same clock with very low skew >>>to both devices) >>>Similarly Actel outputs data on clk falling edge & Xilinx capture on >>>rising edge. >>>I have the Xilinx input & output delays and the clock period is 30 ns. >>>The clock M/S ratio is 40/60 though, so the total allowed time from >>>one device clocking out to the other device clocking in is therefore >>>12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. >>> >>>So how do I apply the constraints to my Actel chip; I've never used an >>>SDC file, so some tips or pointers to examples would be useful. >>> >>>TIA, Niv >>> >>You need the "set_output_delay" constraint I think. Designer "help" menu >>will tell you how to use it. >> >>Alternatively use the Timing Analyser GUI in Designer to set the >>constraints. >> >>Alan- Hide quoted text - >> >>- Show quoted text - >> > > I find the timing analyser GUI (or "Smartime") confusing. I know > exactly what I want to say, but I just can't understand how to apply > my requirements using the Actel GUI. I've even asked the Actel FAE > and he couldn't tell me how to do it, so what chance do I have! > > I think a script is a far better method anyway, as it's fully > repeatable without having to remember what boxes were/were not ticked > etc. > > Niv. > > Hi Niv, I agree, the GUI is a little confusing, and yes scripts are better. However, as a learning exercise it's not wasted time to enter the requirements via the GUI and see what results you achieve. (Perhaps double check the results using back-annotated gate-level simulation, just to be sure that you're getting what you hope you've specified.) BTW you can export the GUI contraints to an SDC file from Designer File->Export->ConstraintFiles Best of luck. AlanArticle: 119727
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:qjkc539kqeipvuab80a6u3ad9vl2aan2sr@4ax.com... > On Thu, 24 May 2007 12:54:13 -0700, "John_H" > <newsgroup@johnhandwork.com> wrote: > > > But if the receiver terminates properly, there will be no reflections. > > John > > Hi John, Right. My point exactly. Also, many thanks for those links, looks like I found, and posted a link to, the only manufacturer that shows LVDS outputs including the resistors. However, if you revisit the pictures in your links, I think you'll see that they paint a simplified picture. If you go to the National link you posted, it's clear that the lower MOSFET isn't just a short to ground when it's on. Otherwise the device would not be meeting the output common mode voltage spec. There's maybe(?) a resistor in there somewhere, and this provides the required output impedance. The Analog device links show a current source top & bottom, which would suggest the Vcm could be anywhere. So, I think we need to view these diagrams as not the full picture. However, I agree with you that it seems most manufacturers aren't all that concerned with output impedance, which is interesting. Cheers, Syms.Article: 119728
On 25 Mai, 04:23, futz...@gmail.com wrote: > I think I have a problem with my Cyclone II FPGA and wanted to do a > boundary scan check on the device to see if it is working ok. I looked > for options to perform a boundary scan check using the Quartus > programmer tool and couldn't find anything useful. I have used this > feature on the Xilinx ISE tools and wanted to know if this can be done > on the Altera FPGAs. > > Any suggestions will help. > Thanks > Anup just write your own STAPL file for the boundary test and execute it with quartus programmer AnttiArticle: 119729
"Mark McDougall" <markm@vl.com.au> wrote in message news:465659ec$0$17960$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > checo wrote: > >> I own a Spartan 3E Starter Kit, which I plan to use for crowd- >> entertainment purposes. Since the 3-bit VGA output is way too limiting >> for my project, I am planning to add a 12-bit VGA port to my Starter >> Kit. > > Since MikeJ must be napping... ;) > > <http://home.freeuk.com/fpgaarcade/displaytest.htm> > > Regards, > > -- > Mark McDougall, Engineer Hi Guys, I wonder if you could improve the colour depth by just increasing the dot rate. So, instead of just on or off for each pixel, you could have 0, 1/2, 1. Probably good enough for "crowd entertainment"? Cheers, Syms.Article: 119730
Hi, To address the question of memory: 2GB should be plenty for almost any design you will do with Quartus. Most Stratix III designs up to a EP3S200 should compile on 32-bit Windows (<=2.0 GB of RAM), and all Cyclone III designs should fit. For the largest designs (EP3S340), you will usually need 3.5 GB of RAM and occasionally up to 4.0 GB. At that point, your options are to run 32-bit Quartus on 32-bit Linux, or run 32-bit Quartus under 64-bit Windows/Linux -- Windows XP-32 maxes out at 2GB per application, but linux and 64-bit OSes provide close to the full 4GB of virtual memory for a 32-bit process. See http://www.altera.com/products/software/products/quartus2/memory/qts-memory.html for more details. As for dual-core vs. quad-core: You will see 10-15% compile time improvements with 2 processors, and an additional ~5% improvement going to 4 processors with the current version of Quartus II. With each release of the software, the advantage of multiple processors will increase as we parallelize more algorithms. One other consideration is that your computer will be more responsive for other tasks (web surfing, etc.) with more processors; the above performance numbers also don't consider performance "tax" on your system from such applications as anti-virus software, which in a quad-core system will not compete with Quartus II for CPU time. See http://www.altera.com/products/software/products/quartus2/multi-processor/qts-multi-processor.html for more (well, a little) details. BTW, one nice thing is how upgradable the Core 2 platform is. You can buy yourself a dual-core chip today and upgrade to a quad-core in the future. Intel's quad-core Q6600 processors are supposed to drop down to $266 later this year. So you could buy yourself a E6600 today ($244?) and Q6600 later in the year ($266) for less than it will cost you to get a Q6600 today ($530). I'm using slightly out-of-date data from http://www.guru3d.com/newsitem.php?id=5086. Regards, Paul Leventis Altera Corp.Article: 119731
Hi John, You're right about the importance of memory sub-system performance -- CAD tools have large working sets, so lower memory latency and higher caches are quite important. Intel's quad-core processors are all essentially two dual-core chips slapped into one package, so they possess 2x the L2 cache. Based on the architecture of these chips, I doubt that running a 2-cpu load on a quad-core processor will have a noticeable difference in performance as compared to running the same load on a dual-core processor. Things will get more interesting when AMD releases their quad-core entry. It supposedly will have independent L2 caches per core, with a shared L3 cache. Also, the integrated memory controller and lower memory latency on the AMD platforms help out Quartus a lot. But then, Intel's 45um offering will also have integrated memory controllers. Isn't competition great? Regards, PaulArticle: 119732
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:5bm6jkF2r60qvU1@mid.individual.net... > Fed wrote: >> What are the rules for coding a bidirectional databus in VHDL? >> I must be able to connect several different entities to the same bus, and >> all entities but one has its outputs as 'Z'. > > That's the rule. > >> Should the bus signals be declared as inout? > > I would prefer to use separate data_in and data_out buses. > There are no real tri-state nodes inside the fpga. > > -- Mike Treseler That's good advice from Mike. The tools will translate your 'Z's and stuff into muxes anyway, so by having the seperate busses, things will be clearer. HTH, Syms.Article: 119733
On 25 mei, 08:26, "Xilinx user" <xilinx_u...@nowhere.net> wrote: > I'm a longtime Xilinx user, and I've recently switched over to the dark side > :) > > Anyway, I'm new to Quartus-II Web Edition, and I'm trying to port a > project from my Xess XSA-3S1000 board to a Altera Cyclone-II > Starter Kit. > I've run into a problem where I have bidi I/Os which need a PULLUP. > The Xilinx Spartan-3's I/Os supported a PULLUP constraint, > specified in Xilinx's *.UCF file. I searched Altera's website, > but I can't find how to specify a pullup on the Cyclone-II's I/Os? > Can someone give me a quick pointer? Welcome to the dark side ! Use "Weak Pull-Up Resistor" in the Assignment Editor. The Fitter - Resource - Output Pins section of the Compilation report should tell you if your assignment was succesfull. Grt, Karl.Article: 119734
> Hi Guys, > I wonder if you could improve the colour depth by just increasing the dot > rate. So, instead of just on or off for each pixel, you could have 0, 1/2, > 1. Probably good enough for "crowd entertainment"? > Cheers, Syms. Hi, this could work on an old crt monitor. If you use a tft screen, the vga signal will be captured one time per pixel, so you will not get the avarage over one pixel. GüntherArticle: 119735
"Symon" <symon_brewer@hotmail.com> wrote in message
news:f367up$elm$1@aioe.org...
>>> I own a Spartan 3E Starter Kit, which I plan to use for crowd-
>>> entertainment purposes. Since the 3-bit VGA output is way too limiting
>>> for my project, I am planning to add a 12-bit VGA port to my Starter
>>> Kit.
>
> I wonder if you could improve the colour depth by just increasing the dot
> rate. So, instead of just on or off for each pixel, you could have 0, 1/2,
> 1. Probably good enough for "crowd entertainment"?
Haha, that's evil :-)
I'd say overclock the DAC by 4x, leaving the rest of the sync signals as
they were, and then you have five colour levels (2.322-bit colour) at the
same resolution. I don't think there's a VGA DAC on the market that can't
cope with 100MHz operation.
Use some temporal dithering to very the bit-pattern that's sent, e.g. for
half-brightness you want to alternately send 0101 and 1010; for
three-quarters swap between 1110, 1101, 1011 and 0111, etc. etc.
I'm almost tempted to try this myself, just to prove that it can be done :o)
-Ben-
Article: 119736I have a SMT338 board. This is a FPGA module and now I want to add a DDR SDRAM to my system. I have the ucf file provided by the company but in this file I don't find ddr_feedback clock. What it means?. I suppose that this pin is neccesary, but there is no pin called "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" y "ckn" but these signals are used by the fpga to the ddr. Has anyone the solution?. RegardsArticle: 119737
On 25 Mai, 12:20, Pablo <pbantu...@gmail.com> wrote: > I have a SMT338 board. This is a FPGA module and now I want to add a > DDR SDRAM to my system. I have the ucf file provided by the company > but in this file I don't find ddr_feedback clock. What it means?. I > suppose that this pin is neccesary, but there is no pin called > "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" > y "ckn" but these signals are used by the fpga to the ddr. > > Has anyone the solution?. > > Regards there are different IP cores, some use the extra feedback pin some dont. boards that have the extra pin are better as they are easier to work with. if you happen to have a board with no feedback pin then you need either use IP core that does not utilize the feedback, or make some workaround to the existing IP core so you can still use it. AnttiArticle: 119738
hi, I've just bought the ML505 and I am looking for some examples of VHDL code that I can start to play around with and edit. All I can find are ACE files, which are not that much help to me. I did find the UCF file that I need, <http://www.xilinx.com/products/boards/ml505/docs/ml50x_U1_fpga.ucf> but I am wondering about the other setup parts. I guess this ML505 board isn't really for people with 0 experience ? regards, ClaireArticle: 119739
On 25 Mai, 13:36, "Claire Murphy" <clairemurphs...@hotmail.com> wrote: > hi, > > I've just bought the ML505 and I am looking for some examples of VHDL code that I can start to play around with and edit. All I can find are ACE files, which are not that much help to me. I did find the UCF file that I need, <http://www.xilinx.com/products/boards/ml505/docs/ml50x_U1_fpga.ucf> but I am wondering about the other setup parts. > > I guess this ML505 board isn't really for people with 0 experience ? > > regards, Claire please begin learning to finf info just go http://www.xilinx.com/ml505 and start from there AArticle: 119740
>> Fed wrote: > That's good advice from Mike. The tools will translate your 'Z's and stuff > into muxes anyway, so by having the seperate busses, things will be > clearer. > HTH, Syms. > Isn't that going to make it more difficult to maintain if new entities are added in the future?Article: 119741
On 2007-05-25, Brian Drummond <brian_drummond@btconnect.com> wrote: > Consider a shell script which launches PARs one at a time ( for bonus > points, n at a time on a multi-core machine!), each with a separate cost > table entry (-t nn). You might also be able to improve your results by varying your timing constraints slightly instead of using a separate cost table. (I've recently played with a design which would meet timing with a cycle time constraint of 4.8 ns, fail at 4.9 ns and succeed again at 5.0 ns. ) /AndreasArticle: 119742
On 25 May 2007 00:46:49 -0700, sudhakarmvs@gmail.com wrote: >On May 24, 4:57 pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On 23 May 2007 22:57:24 -0700, sudhakar...@gmail.com wrote: >> >> >Hi to all >> >> >I am currently working on DDR2 controller for Burst Lenth 8. >> >My own code is giving good results when i verified with memory model >> >from MICRON. >> >Now my problem is memory on the board is not sending 4 DQS clock >> >pulses. it seems to be sending for burst lenth 4. >> >> What are you writing to the DDR's mode registers? >> >> - Brian > >Hi Brian >thanks for ur response > It's difficult to follow the disconnected bits of code you have posted, but please explain what this line does. > s_ddram_address <= "0010000110010"; -- >mrdll normal operation(mrdll with out reset) Because, according to the Micron datasheet I have handy http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf (see p. 25) it appears to set the burst length to 4; > and when I simulated with MICRON memory model the following is >displyed. What exactly is displaying this, and why does it seem to disagree with the value you are writing above? - BrianArticle: 119743
On May 25, 6:09 am, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "Symon" <symon_bre...@hotmail.com> wrote in message > > news:f367up$elm$1@aioe.org... > > >>> I own a Spartan 3E Starter Kit, which I plan to use for crowd- > >>> entertainment purposes. Since the 3-bit VGA output is way too limiting > >>> for my project, I am planning to add a 12-bit VGA port to my Starter > >>> Kit. > > > I wonder if you could improve the colour depth by just increasing the dot > > rate. So, instead of just on or off for each pixel, you could have 0, 1/2, > > 1. Probably good enough for "crowd entertainment"? > > Haha, that's evil :-) > > I'd say overclock the DAC by 4x, leaving the rest of the sync signals as > they were, and then you have five colour levels (2.322-bit colour) at the > same resolution. I don't think there's a VGA DAC on the market that can't > cope with 100MHz operation. > > Use some temporal dithering to very the bit-pattern that's sent, e.g. for > half-brightness you want to alternately send 0101 and 1010; for > three-quarters swap between 1110, 1101, 1011 and 0111, etc. etc. > > I'm almost tempted to try this myself, just to prove that it can be done :o) > > -Ben- I think the point is that the OP doesn't have a DAC, just three 1 or 0 outputs from the FPGA, one to each color signal, possibly through an external buffer. Or you could say he has "one bit" DAC's. Dithering will work with a low-pass filter, but if there are additional pins available it would be better to use a resistor ladder to make a simple DAC. TFT VGA displays generally have a very narrow sampling window (see the Analog Devices AD9888 datasheet for instance) which is centered in the pixel time slot. This system works best when there is no low-pass filter smearing out the beautiful contrast of the original image. By the way, the video AC bandwidth is significantly higher than the pixel rate in order to give the sharp edges between pixels and flat voltage mid pixel. Generally it's important to match the cable impedance from the DAC output to the board connector, or if this isn't possible to reduce the length of the mis-matched portion as much as possible, preferably to much less than a pixel time in terms of propagation.Article: 119744
"Fed" <Fed@bill.com> wrote in message news:4656d3bc$0$90267$14726298@news.sunsite.dk... >>> Fed wrote: >> That's good advice from Mike. The tools will translate your 'Z's and >> stuff into muxes anyway, so by having the seperate busses, things will be >> clearer. >> HTH, Syms. >> > Isn't that going to make it more difficult to maintain if new entities are > added in the future? > I don't think it need be more difficult, just different! If you plan it right from the start, I think you'll be just fine. You also won't be tearing your hair out trying to find signals in Chipscope that've been turned from tristates into muxes. But, YMMV, either way will work. HTH, Syms.Article: 119745
vssumesh wrote: > Hi John, > Sorry for the trouble. I also wanted to be part of this discussion > as i used to be part of this group for the last two years. This group > actually helped me to learn a lot in the FPGA based HW modeling. Sorry > for the wrongly formated message i sent. The sentance structure may be > some times wrong as i am not that strong in english. But last time > what happend is; i was little bit excited to see my old collegue to > write something on this group. It remind me about the old times when > we both were actively participated in these discussions. Thats what > happend. Sorry for that. Anyway my actual intention is only to be a > part of all these discussions. Sorry for every thing else. > Thanks for your suggestion. > regards > Sumesh V S And *thank you* for becoming an active part of this board. - John_HArticle: 119746
On 24 May 2007 04:35:28 -0700, moogyd@yahoo.co.uk wrote: >Hi, > >I was hoping that someone could point me at a useful document or other >link. >Our FPGA build flow is currently scripted for a single iteration P&R. >Unfortunately, we are now starting to get some hold violations. >If I run a multipass P&R, approximately 50% of the iterations will >yeild successful timing (Timing Score = 0). > >Ideally, what I want is a method of saying : Iterate until timing met, >with a maximum of n MPPR may not be the best idea here; (a) because you have to "kill" it when done, and handle the resulting file renamings yourself, and (b) because when a PAR aborts with the famous "portability errors", it also kills MPPR instead of starting the next pass at PAR. So you find out next morning, MPPR stopped about ten minutes after you left the office. Unless PAR has become 100% reliable since 7.1... Consider a shell script which launches PARs one at a time ( for bonus points, n at a time on a multi-core machine!), each with a separate cost table entry (-t nn). The script will have to look at each .PAR file (once the PAR has completed) and search for "all constraints were met" or the appropriate phase. - BrianArticle: 119747
"Gabor" <gabor@alacron.com> wrote in message
news:1180097090.950740.115520@k79g2000hse.googlegroups.com...
>
> I think the point is that the OP doesn't have a DAC, just three 1 or 0
> outputs from the FPGA, one to each color signal, possibly through an
> external buffer.
Ah, OK. That would admittedly make more sense than having a 3-channel 8-bit
video DAC and just wiring all the input pins together :-)
> TFT VGA displays generally have a very narrow sampling window (see
> the Analog Devices AD9888 datasheet for instance) which
> is centered in the pixel time slot.
True; as someone else pointed out this is not true of CRT displays. Not sure
about overhead projection technology, which is probably what the OP has.
Entertaining crowds using LCD panels is probably going to blow the budget...
:)
Cheers,
-Ben-
Article: 119748> Hi John, > You're right about the importance of memory sub-system performance -- > CAD tools have large working sets, so lower memory latency and higher > caches are quite important. Confirmed by an upgrade I did last night from an AMD Althlon 64 3500 to an Athlon 64 X2 4400. Before the change I rebuilt a design I've been working on recently. It's not that big, Quartus was finished in 4mins 56sec. When I ran it with the new processor it took.......4mins 56secs, pretty much confirming this is memory bound. I was a bit disappointed, but at least was able to run Modelsim at full speed in the background at the same time. I also noticed that when my virus scanner kicked off it's weekly scan I was able to keep working at full speed so I allowed it to finish for a change :-) Nial.Article: 119749
On May 25, 12:11 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 24 Mai, 16:35, Peter Alfke <a...@sbcglobal.net> wrote: > > > You can define the BRAM content through configuration, and you can > > then use the BRAM as a ROM, just by never writing new information into > > it. > > But remember: > > Reading from a BRAM is a synchronous operation. You must supply a > > clock, and the Data output changes only after the rising edge of the > > clock. > > Also, in order to guarantee the integrity of the ROM content, you > > should not change the addresses during the set-up time window before > > the clock, while CE is active. (WE inactive is not sufficient to > > protect against all address set-up time violations). This is not > > intuitively obvious. > > Peter Alfke, Xilinx > > ======================= > > On May 24, 7:07 am, Lancer <peppe...@gmail.com> wrote: > > Hi Peter, > > isnt that address setup time requirement only there for Virtex-4 > because of silicon errata? > or can the memory corruption occour on other Xilinx FPGA's as well? > > Antti Antti - As I recall, V2Pro has a similar corruption "feature" for the BRAMS. John Providenza
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