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Hans posted in news:Ybj9i.4930$sM1.2868@newsfe4-win.ntli.net :
"[..]
Using SystemC for your project is a great suggestion since [..]
you can really put your teeth into issue like [..]
concurrency [..]
[..]"
In news:1181080157.909291.81940@p47g2000hsd.googlegroups.com
timestamped Tue, 05 Jun 2007 14:49:17 -0700, ARH <haghdoost@gmail.com>
posted:
"Hans,
Thank you very much for your useful explanations.
I agree with you about systemC abilities [..]
[..]"
Then perhaps you are in trouble because you have not noticed yet that
the SystemC(R) standard is actually explicitly written in a way which
does not use concurrency.
Good luck in your project whatever you choose to do.
Regards,
Colin Paul Gloster
Article: 120376Hi ARH, On Jun 5, 10:49 pm, ARH <haghdo...@gmail.com> wrote: > Hans, > > Thank you very much for your useful explanations. > > I agree with you about systemC abilities and have to know C++ didn't > change my idea about this language because I learned C++ as the first > programming language. > > Also I have no problem with learning any new language in my project > and I think this would be a good chance for me, for this reason I > mention SystemC and SoC design because I think these are new area in > Hardware Design that have shiny future. > > I have seen your website ,www.ht-lab.comand I want to congratulate > you for your effort. I am one of the interest person in your CPU86 > project. I involved to this project several days, last week and have > three question/offer about it : > > 1. Did you ever think to system level description ? there are several > IP-core from Ht-lab and Opencores.org that could be together in a > system level design. Yes, I combined the core with 2 UARTs from opencores an 8254 timer, a simple RTC and 2 cascading 8259 interrupt controllers from another project (not free ip). The next step was to port some OS like ELKS/ FreeDOS/etc but I totally underestimated the amount of free time required to do that port so the project was put into hibernation mode :-) > > 2. what is the advantages of x86 CPU IP-core vs. other CPU IP that use > ordinary in SoCs (like embedded PowerPC cores) Very little, the only reason I would suggest the CPU86 is if you have to run some 8086 legacy code, you want to build your own IBM PC/XT from the ground up and/or you simple like the clean consistent processor architecture :-). If you have to start from scratch than a Nios/MicroBlaze/Mico8/Leon/etc softcore is a much better choice since you not only get all the software development tools like gcc and gdb but the vendors also provides you with a nice environment for adding peripherals. This is one lessen I learned, writing a CPU in VHDL/ Verilog is straight forward but the software support is a different story. > > 3. in which places in this project you need contributor (especially in > Verilog version wrote by Antti Lucas because I prefer Verilog rather > VHDL) As I mentioned above, what is lacking is software support but converting the processor to Verilog or finishing off Antti's one would also be an interesting exercise. The other area which would be interesting is taking the processor and building a proper verification environment around it using SystemC, PSL and Mentor's AVM. But this requires expensive tools like Questa.... If you need any help just send me an email, Regards, Hans www.ht-lab.com > ARHArticle: 120377
> And one technique that Xilinx recommends for lessening > effects of ground bounce is to drive unused adjacent IO > to GND on the PWB, and drive these as outputs on the > FPGA. ie tie the input to the obuf to logic 0. > Regards, > John Retta > Retta Technical Consulting Inc. > Colorado Based Xilinx Consultant Hi John, Yes, I have done this before on the bigger packages - any spare pins get nailed low. This is a ff668 device and sadly I haven't got the spare pins. All IOs are HSTL class I and the tools say I am within the SSO limits .. Investigating the PDS and layer stackup but it looks pretty good to be honest. Cheers, /MikeArticle: 120378
On Wed, 06 Jun 2007 00:47:44 -0700, Pablo <pbantunez@gmail.com> wrote: >Is it possible to install two diferent versions of EDK/ISE, that is, >one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the >first one for simulink, but my custom board uses the second one (for >the drivers). I suppose that the problem is the "Path Variable". > >Has anyone some experience in this?. > >I will post my results as soon as possible. > >Regards, Pablo You only need to create some littel batch files around the calls to porject navigated and edk, setting the corresponding variables: this is my batch file for EDK 8.2: set LMC_HOME=c:\Xilinx8.2\smartmodel\nt\installed_nt set XILINX=c:\Xilinx8.2 set XILINX_EDK=C:\EDK8.2 set PATH=%XILINX_EDK%\bin\nt;%XILINX%\bin\nt;%PATH% bin\nt\xps_sdk.exe It works nice. Regards, ZaraArticle: 120379
"MikeJ" <mikej@fpgaarcade.nospam.com> wrote in message news:Rui9i.1428$ZA.885@newsb.telia.net... > > I am about to do a board update and am considering adding a linear 2V5 > regulator to feed just the VCCAUX pins ??? > Linear regulators get rid of noise below c.100kHz. Above that frequency, the only attenuation you get is the resistive loss with the bypass caps. I imagine your jitter is somewhat higher than 100kHz, so you might get more joy (and save $£€¥) using passive filtering. Certainly, you must keep VCCAUX separate from the Vcco 2.5V. HTH, Syms.Article: 120380
Hi Brian, thanks for your tips. > > A) Try to distinguish whether the DCM input clock is > affected when the I/O switches; or, if the DCM > itself is being affected; or, if both are > Measurements at the clock input balls show no significant increase in jitter. > - clock your DDR clock forwarding flop directly from > the input clock, with no DCM: does it still get > the jitters when the QDR I/O switching starts? > > i.e. 100 Mhz input clock -> BUFG -> DDR output > > ( IIRC, you don't need to fiddle with DIFF_OUT buffers > for global clock forwarding in V4 due to the already > differential global clock distribution ) > > - if you have another clock input ( esp. in a quiet bank ), > temporarily clock the QDR logic from that ( with and > without DCM ) and see if the jitter changes > Good idea. I tried this before and I will need to repeat it to be sure. I fed in a 200MHz single ended clock of the correct phase into a spare input pin and fed this through the same path minus the DCM. It looked ok which pointed me at the DCM but I need to go back to this. Also interesting is the other outputs (Address, data etc) show a much smaller jitter increase. > B) DCM Duct Tape > > - LOC the DCM to the other DCM sites on the chip; > see if that affects the jitter good idea. > <snip> > > - change FACTORY_JF as described in Answer Record 13756 > > If decide to try CLKFX, see AR 21594 and AR 18181 > ( V2/S3 era advice, not sure how it applies to V4 ) > Tried both of these. CLKFX looks about the same, but the "shape" of the jitter is slightly different. Austin assures me that in V4 the DCM is much less susceptible to noise than in the V2 days - I've been through this before :) > > - change DCM DESKEW_ADJUST to SOURCE_SYNCHRONOUS to turn off > the internal DCM feedback delay element (more V2 era advice) > ( see pages 4-5 of XAPP259 ) > > Other questions: > > - Do you have any spare LVDS input/outputs elsewhere > on the chip ? ( handy for clock troubleshooting ) I have an unused bank with 2V5 IO actually so I could possibly get some clocks in and out here. > > - If you run a 'hammer' test 0000 <=> FFFF instead of > pseudorandom patterns on the QDR address/data lines, > does the jitter get much worse and/or the DCM unlock ? > ( also try changing the toggle rate, 1,2..N clocks ) mmm. The chip actually has a max switching test as well which works (so no DCM unlock). I will make some measurements. > > - Is the QDR interface bandwidth sufficient to allow for > Asteroids vector generator emulation at 1080p resolution? > I usually try and keep work and the games separate, but it would make an excellent platform and save me finishing the DDR controller !! I have a broadcast serial digital 720P output module somewhere, but what I need to make is a DVI output I think .... Thanks for all the tips people, I will get some more measurements over the next week or two. Thanks also to Xilinx for the support. My gut feeling is it must be a weakness in the PDS which is effecting the DCM particularly, but measuring these things is certainly tricky. Cheers, Mike.Article: 120381
There is a single VCCIO 2V5 bank on the device but it is totally unused. My thoughts on the regulator were to isolate the VCCAUX from possible noise elsewhere on the board. (I remember linear regs were recommended on the SerDes 2v5 supplies on Virtex2pro) I will improve the layout and filter the VCCAUX supply and have a small well bypassed area fill for it. Regards, Mike "Symon" <symon_brewer@hotmail.com> wrote in message news:f45u24$1jd$1@aioe.org... > "MikeJ" <mikej@fpgaarcade.nospam.com> wrote in message > news:Rui9i.1428$ZA.885@newsb.telia.net... >> >> I am about to do a board update and am considering adding a linear 2V5 >> regulator to feed just the VCCAUX pins ??? >> > Linear regulators get rid of noise below c.100kHz. Above that frequency, > the only attenuation you get is the resistive loss with the bypass caps. I > imagine your jitter is somewhat higher than 100kHz, so you might get more > joy (and save $£?¥) using passive filtering. Certainly, you must keep > VCCAUX separate from the Vcco 2.5V. > HTH, Syms. > >Article: 120382
is anybody here who can guide me about asynchronous CAD tools. is any such CAD tool available. which asynchronous design methodology is used nowadays.plz help me.Article: 120383
Hi experts,
Hi all i need a help,I am using the spartan
FPGA.I am using the DCM to scale the input clock frequency
to 72Mhz.This clock signal is feed to the sram in the
board,which is also the system cock.When i analyse the timing report
the clock to pad
delay for the port sram_clk[clk output from DCM to SRAM]
is not mentioned in the report.
Could any one help me in finding the clock to pad delay in the timing
report.
Article: 120384"Pablo" <pbantunez@gmail.com> wrote in message news:1181116064.178069.323750@p77g2000hsh.googlegroups.com... > Is it possible to install two diferent versions of EDK/ISE, that is, > one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the > first one for simulink, but my custom board uses the second one (for > the drivers). I suppose that the problem is the "Path Variable". > > Has anyone some experience in this?. > > I will post my results as soon as possible. > > Regards, Pablo > I have several directories, c:\xilinx8.1, c:\xilinx8.2 etc. I just rename the one I want to use to c:\xilinx . HTH, Syms.Article: 120385
On Jun 2, 8:39 pm, morphiend <morphi...@gmail.com> wrote: > On Jun 2, 6:45 pm, "MM" <m...@yahoo.com> wrote: > > > Mike, > > > BTW, did you write the adapter layer LL_TEMAC driver for linux yourself? > > > Thanks, > > /Mikhail > > Yes and no. It was modified from the MontaVista 2.4 GEMAC adapter. I > bridged that with the MV 2.6TEMACdriver to get a driver together. > The 2.4 GEMAC driver was previously using the CDMAC. This problem is actually a result of the data buffer not being 32-bit aligned. For some reason this is only affecting TCP messages and not UDP or ICMP messages. I have used ChipScope to verify that the data provided to the LL_TEMAC is actually being corrupted by the CDMAC before it reaches the LL_TEMAC. For now a workaround is to force alignment of the data buffer in the LL_TEMAC driver only for TCP messages. This is basically a memcpy (byte by byte) to force alignment, which could be optimized. This is allows TCP messaging to not have a corrupted Ethernet header. A better solution will be to two buffer descriptors for the message, one for the Ethernet header and one for the payload data.Article: 120386
On 6 juin, 07:02, "Symon" <symon_bre...@hotmail.com> wrote: > I have several directories, c:\xilinx8.1, c:\xilinx8.2 etc. I just rename > the one I want to use to c:\xilinx . > HTH, Syms. I also recommend Symon's method. _Usually_ the method that Zara mentions works well but I once had a problem when Xilinx had not been installed in C:\Xilinx. Better stick to the default directory. PatrickArticle: 120387
On Jun 5, 12:10 pm, Amal <akhailt...@gmail.com> wrote: > Anyone has a good pointer to a portable (Windows, *nix) TCP/IP socket > library that can be used with VHDL FLI, Verilog PLI/VPI, SystemC, or > SystemVerilog DPI? Amal, Try this link: http://www.sutherland-hdl.com/pli_book_examples.html "David Roberts, of Cadence Design Systems, has provided a great example using sockets to communicate between a PLI application and an independently running C program. David has provided this example with no restrictions on usage, under the GNU freeware license agreement." Allegedly it works on Linux and Windows. Enjoy, /EdArticle: 120388
First of all, thanks for your advices. I am agree with Patrick. For me I choose the Symon's method, but at finally I will make the Zara scripts because this computer has to be programmed by most of people. Regards, PabloArticle: 120389
On Jun 6, 9:17 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > Hans posted innews:Ybj9i.4930$sM1.2868@newsfe4-win.ntli.net: ..snip.. > Then perhaps you are in trouble because you have not noticed yet that > the SystemC(R) standard is actually explicitly written in a way which > does not use concurrency. Why is he in trouble? Are you hinting to the fact that thread synchronisation by events is not ideal and can lead to deadlocks and race conditions if you are not careful? I have no idea how big of a problem this is in concurrent model development. However, lets be realistic, a lot of big companies like ARM and ST use SystemC for their models, do you think they would spend all this effort on a language that is flawed in terms of concurrency support? I am no expert (not even a novice) so perhaps one of the Doulos guys can shed some light on this? Hans. www.ht-lab.com > > Good luck in your project whatever you choose to do. > > Regards, > Colin Paul GlosterArticle: 120390
Did someone have a realistic gate count for jbig on an fgpa?Article: 120391
Nobody has a clue ? "sjulhes" <t@aol.fr> a écrit dans le message de news: 466404fb$0$10866$426a34cc@news.free.fr... > Hi all, > > I have a SOC with a Power PC running on a Virtex II pro. > On FPGA configuration, the PPC firmware runs correctly, heap reservation > on firmware initialisation is correct. > When I reset the SOC with the reset controller, the PPC restarts > correctly, but when it tries to use the heap to initialize some dynamic > variables, I get a fail on the malloc. > > It seem that on the reset the power PC context is not reinitialized. > I guess we have to add something in the boot sequence of the PPC to reset > the heap pointer. > > I'm I right ? > It is something that must be standard in the power PC world, does someone > have an exemple how to do this ?? > > Thanks. > > Stéphane. >Article: 120392
"MM" <mbmsv@yahoo.com> wrote in message
news:5clujiF31e3g1U1@mid.individual.net...
> If you used wizard to build the design or if it is one of the reference
> designs, then the most likely problem is DCM not being locked for whatever
> reason (bad/wrong external clock, DCM frequency range is wrong for the
> frequency, etc.)
Or my personal favourite, DCM reset polarity is inverted because you forgot
to change the parameter setting from the default :)
<how many times have I done that...>
-Ben-
Article: 120393mk, Well, you may have whatever opinion of yourself you desire, and I can't control that. I just had a series of questions and comments, and the poster had emailed me directly, so I offered him the courtesy of a personal reply. His issue is IO switching, and it isn't a question of not working, it works just fine. He has customers who are nervous when they see jitter (seems a redundant sentence?), so he needs to find his margin, prove he is OK, or reduce the jitter (again, only for cosmetic reasons). The extra pins to ground isn't go to do anything for him (use of IOs as ground), as he is already in an excellent package in V4, and we are looking at his bypassing solution. He used all one value for Vcco bypass, 0402 1.0uF, and I am working on showing him that there can be anti-resonant peaks (right around 200 MHz), where the use of all one value is a bad choice. "Chopped liver?" I wonder where that came from? AustinArticle: 120394
On 6 jun, 16:10, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "MM" <m...@yahoo.com> wrote in message > > news:5clujiF31e3g1U1@mid.individual.net... > > > If you used wizard to build the design or if it is one of the reference > > designs, then the most likely problem is DCM not being locked for whatever > > reason (bad/wrong external clock, DCM frequency range is wrong for the > > frequency, etc.) > > Or my personal favourite, DCM reset polarity is inverted because you forgot > to change the parameter setting from the default :) > > <how many times have I done that...> > > -Ben- I use the wizard to create a model for custom board. In which I configure clock (100->125), add leds and ddr. I don't change anymore. Where is this parameter?. How is it configured?Article: 120395
Hello, I use Altera's Quartus II software for my FPGA development and in the software package they have the following Advisors: Timing, Power, Resource Optimization, Increment Compilation. I usually open the Timing Advisor and make the suggested changes that are easy to make. Usually these are the configuration settings and are easy to change. The other suggestions in the Timing Advisor are a little more involved and I don't do. I want to know from those of you that use Quartus and the Advisors if you make the suggestions that require a little more work. For example: Optimize specific clock domains for speed. Usually you must open the Assignment Editor and add some changes. If you feel that making these changes are beneficial then I take the time to learn how to implement their suggestions. thanks, joeArticle: 120396
"austin" <austin@xilinx.com> wrote in message news:f46gmp$ra02@cnn.xilinx.com... > > He used all one value for Vcco bypass, 0402 1.0uF, and I am working on > showing him that there can be anti-resonant peaks (right around 200 MHz), > where the use of all one value is a bad choice. > Hi Austin, Anti-resonant peaks? Right around 200MHz? With a 1uF cap? Wow, I'm sure looking forward to you posting what your advice is. You sure you've not been spending too much time in the Gaslamp Quarter? ;-) Cheers, Syms.Article: 120397
On Jun 6, 11:32 am, han...@ht-lab.com wrote: > As I mentioned above, what is lacking is software support but > converting the processor to Verilog or finishing off Antti's one would > also be an interesting exercise. The other area which would be > interesting is taking the processor and building a proper verification > environment around it using SystemC, PSL and Mentor's AVM. But this > requires expensive tools like Questa.... Hans, Thank you for contribution suggestions. I want to work on a project that have some thing new to develop and document it in some internal or international conferences, when I see CPU86 project an initiative idea take place in my mind to contribute with you to develop various aspect of it specially in the system level description. But when you say that x86 soft IP core have no main advantage versus other useful CPU IP-core , I think that there are no thing new in this work and after all no one interest it. What is your idea about it? Are there any rooms in HT-Lab projects that have a valuable academic tent? Of course I am a novice student in hardware engineering and I can't judge about the academic value of project. Best regards --ARHArticle: 120398
VIPS wrote: > We have been knowing the false path and its nature but i am confused > as to how to identify a false path in a design having say 100 modules. > We know that false path as defination that it is the path that is > never executed or sanitisized henceforth it is not included in the > STA . But the million dollar question is if the design is really big > the how can one it so as to name it in the synthesis. I want to know > the steps followed in the industry. I use separate modules for each clock domain and run STA on those. I use "known good" synchronization techniques between the modules. -- Mike TreselerArticle: 120399
sanju wrote:
> is anybody here who can guide me about asynchronous CAD tools. is any
> such CAD tool available. which asynchronous design methodology is used
> nowadays.plz help me.
>
I use many instances of that minimal
asynchronous circuit called a D-flop :)
-- Mike Treseler
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