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Hi the sysmon is really available in ALL Virtex-5 devices below is voltage and temperature monitoring log screenshot from Chipscope http://www.xilant.com/downloads/cs82_sysmon.jpg the temperature drops seen in the log are my finger pressed to the top of the Virtex-5 package AnttiArticle: 110451
Is it possible to have a connection between two seperate user peripherals inside
a Nios 2 system? Or do I have to route the signals outside the Nios 2 system and
connect them at toplevel (like below)?
nios_system : entity work.nios_system
port map (
clk => sys_clk,
reset_n => locked,
out_port_from_the_usr_peripheral_1 => usr_peripheral_shared,
in_port_from_the_usr_peripheral_2 => usr_peripheral_shared
);
BTW, is it possible to give ports from a user peripheral your own names in the
generated nios_system.vhd file? (instead of out_port_from_the_... and
in_port_from_the_...)
TIA,
Frank
Article: 110452Wow, that's quite a challenging beginners project... What kind of level do you have in electronics? antenna <-> phy ASIC <-> FPGA is how i'd start. Dig out the 802 standard to get to grips with wifi, then look around for some Phy ASICs to get some feel for the implementation you could realise. Ben "Token" <ramukumban@gmail.com> wrote in message news:1160983718.255657.65840@m7g2000cwm.googlegroups.com... >I just started learning about fpga technology, I am looking for a > solution to this minor problem. > I'm supposed to build a physical layer repeater for a Wi-Fi signal > using any of the xilinx products.this is actually a simulation project > for school. the intial part is just a physical layer repeater. then > i'll have to add the data link layer components for the final part of > the project. Any assistance, suggestions will be appreciated. >Article: 110453
Antti wrote: > Hi > > the sysmon is really available in ALL Virtex-5 devices > below is voltage and temperature monitoring log screenshot from > Chipscope > > http://www.xilant.com/downloads/cs82_sysmon.jpg > > the temperature drops seen in the log are my finger pressed to the top > of the Virtex-5 package So, was this doing anything, or is that just self-heating gets it to +28'C above ambient ? -jgArticle: 110454
Hans wrote: > Hi Davy, > > The AVM cookbook from Mentor describes these terms, you can download a free > copy from: > > http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm [snip] Hi Hans, Can I use base class mentioned in Mentor's AVM cookbook in other simulator like Cadence's NCSim? Best regards, Davy > > Hans > www.ht-lab.com > > > "Davy" <zhushenli@gmail.com> wrote in message > news:1160799509.696951.204680@b28g2000cwb.googlegroups.com... > > Hi all, > > > > IMHO, there is something compare the golden output and DUT output in > > testbench (I call it Checker). But in verification book, there is both > > Scoreboard and Checker. Are they similar? > > > > Please recommend some reading on it.Thanks! > > > > Best regards, > > Davy > >Article: 110455
devices <me@home> wrote: >Is it possible to grab video or still frames directly into a NAND flash? Is >it a common practise or are such devices still too slow? Consider that many digital cameras use flash "discs" and handle 640x480 @ 30fps (2MiB/s mjpg canon s2is). So it is possible.Article: 110456
Antti, thanks for sharing this schematic. A little too late for me although. I connected FX2 to external connector of s3esk - better option. If I used the platform cable HW instead I would loose on-board JTAG and there are not any IO pins connected to Spartan. Courious: why the FX2 on the schematics does not have any external EPROM? Cheers, Guru Antti wrote: > > > Antti, > > > > > > I'm really shocked you would post a URL like this > > > to this newsgroup. I urge everyone to avoid > > > visiting this ridiculous site. > > > > > > -Dave > > > > On the contrary, this is not spam. It is on topic (fpga's) and isn't > > selling anything. > > > > I am curious. Do you object to: > > 1. Posting schematics for download? > > 2. Charging a fee for downloads (there is a free option)? > > 3. A website that just sells disk space and bandwidth? > > 4. The advertisement on the website? > > 5. Reverse engineering? > > > > Alan Nishioka > > Hi Alan, > > first :) - tnx. > I am very technical person, so the SPAM thing didnt even occour on my > mind. really. I had found something that I think is of interest - the > schematic is essentially what is missing in the Spartan3e starterkit > schematics, e.g. it is what belongs on that empty page there. > To what i know that is of interest to several people who want to use > the FX2 on s3esk board. > > There is some reasoning for the style of initial posting, and secondly > I was really busy today with tasks like scarving ships out of skin of > wood and making panncakes. So i had not much time. The children are in > listening mode now (evning fairy tale reading) so here is the direct > and hassle free download link to the same schematic. > > http://www.antti-brain.com/xil_jtag.pdf > > Antti > PS the link referenced in the original posting is auto-deleting in 30 > days last download.Article: 110457
Guru schrieb: > Antti, thanks for sharing this schematic. > A little too late for me although. I connected FX2 to external > connector of s3esk - better option. If I used the platform cable HW > instead I would loose on-board JTAG and there are not any IO pins > connected to Spartan. > Courious: why the FX2 on the schematics does not have any external > EPROM? > > Cheers, > > Guru I suppose only the relevant FX2 <> CPLD wires are included, e.g. the standard stuff is not drawn (this is my guess) the schematic is not intended to be full schematic AnttiArticle: 110458
Thanks for responding Rickman, I was begining to wonder about my sanity. To answer John_H, Austin has replied in a new thread :) that I should only boundary scan post config :- -When configuration cannot be prevented -When differential signaling standards are used" I had seen this before but SSTL is not differential. In fact Coolrunner II use standard IO pins to become the vref inputs, needing to use one IO for vref for every 6 SSTL inputs. Also the vast majority of Xilinx cocumentation is FPGA centric without expressely saying so. Rickman, the vast majority of webcases are hand holding of new users. It doesn't matter how loudly Xilinx shout RTFM that is what the user has not done. I allways expect to spend a few days getting Xilinx support to understand that my question is not trivial and your not going to change human nature which is not Xilinx induced. Allthough perhaps changing a usenet thread title to something that is ultimately embarrassing is a lesson that might not be forgotten. Colin On Rickmans other note, rickman wrote: > John_H wrote: > > rickman wrote: > > > Funny, I think I understood what you were asking by your second post > > > here. I don't know why Xilinx does not understand. They seem to want > > > to answer the wrong question and then when you tell them they answered > > > the wrong question they seem to think *you* are the one that > > > misunderstands. > > > > > > I have seen this more than once and with more than one person at > > > Xilinx. I don't know if it is a corporate culture thing to not be > > > willing to reexamine their thinking or if it is just the individual > > > people, but I have seen this on numerous occasions. > > > > > > Perhaps if you asked in an extremely detailed way that left no room for > > > misunderstanding? Specify the pin number of the signal you are using > > > to keep them from thinking you are using SSTL on the JTAG pins. Ask > > > specifically what the threshold level will be on that pin during > > > boundary scan after you have loaded the configuration. *Do not mention > > > any other information that you may think will be helpful if it is not > > > required!!!* Any stray info can result in misinterpretation. I have > > > seen many times that the mention of a piece of information that should > > > help to clarify your thinking actually results in alarm bells going off > > > on the other side and the discussion goes way off course. > > > > > > Good luck! > > > > > > rickman - I give you kudos for understanding what colin is trying to > > achieve. I've watched this thread and I'm still confused. My > > engineering career started in manufacturing where I had extreme interest > > in boundary scan. Yet, I'm stymied. > > > > The issue of IO standard is external to any registers in an internal > > scan chain. I couldn't figure out if there was a need to interface to > > the jtag chain in SSTL logic or if there was a perceived internal need > > for the jtag chain to be driven by SSTL to scan SSTL I/O cells. > > > > If the scan was 1) desired before configuration, 2) designed to drive, > > receive, or tristate signals based on the scan chain, or 3) use the > > existing configured design, this casual observer still has no clue. > > > > It seems there are assumptions that aren't discussed in setting up the > > problem that needs to be solved. Often, assumptions can be determined > > from the context. If these underlying assumptions are guessed > > incorrectly, the wrong question is answered. > > > > So - any idea what's really needed? > > I will explain what I think is going on and Colin can correct me if I > am wrong. > > They are using a Coolrunner II to interface to an SSTL device. The > CPLD is first configured, then they want to run boundary scan to test > the board. In order to assure their customers that boundary scan will > properly verify the connection to the SSTL device, they want to verify > that during boundary scan the CPLD will be using SSTL voltage levels on > the pin that connects to the SSTL device. This is not one of the JTAG > pins, it is just a general IO pin. > > So the question is, will this pin use SSTL signaling during boundary > scan if it is first setup as an SSTL IO during configuration? > > Is that clear? > > I fully expect the answer is that the pin will be using SSTL voltage > levels during boundary scan. But I can see where the OP would want to > ask to make sure. You can never be too sure how chips work internally > regardless of what seems obvious.Article: 110459
Hi all, I'm trying to run the ADC chip LTC1407a on the spartan 3e starter kit. Both the function and timing simulation is validated and the signal AD_CONV and SPI_SCK is just as wanted when I use an oscilloscope to observed the board signal. In other words, 34 SPI_SCK after 1 clock period of AD_CONV. However, the data output is always 0x3FFF when a 10kHz sine wave is applied on both channel. Firstly I used a 50M clock and as it can't work properly, I lower the clock using the internal DCM to 10MHz and use the chipscope to get the signals out. I found the signal SPI_MISO, which is the output serial data from the ADC, is always '1'. But the signal on board observed by oscilloscope keeps changing '0'/'1'. Any suggestions? Thanks, JJ From news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk Mon Oct 16 02:35:39 2006 Path: newssvr25.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newsfeed.telusplanet.net!newsfeed2.telusplanet.net!newsfeed.telus.net!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!newspeer1.nwr.nac.net!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!iris.uk.clara.net From: "Tom Lucas" <news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk> Newsgroups: comp.arch.embedded,comp.arch.fpga References: <1160699190.331142.218980@k70g2000cwa.googlegroups.com> <1160706620.222029.291920@m7g2000cwm.googlegroups.com> <1160712667.864828.182490@b28g2000cwb.googlegroups.com> <0NQXg.11232$vJ2.5824@newssvr12.news.prodigy.com> Subject: Re: OT: Internships? Date: Mon, 16 Oct 2006 10:35:39 +0100 Lines: 42 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-RFC2646: Format=Flowed; Response X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 1253419420c866a3526d7c016967656804f30c2866f767c15096521545335235 NNTP-Posting-Date: Mon, 16 Oct 2006 10:34:45 +0100 Message-Id: <1160991285.68608.0@iris.uk.clara.net> Xref: prodigy.net comp.arch.embedded:239497 comp.arch.fpga:121403 "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:0NQXg.11232$vJ2.5824@newssvr12.news.prodigy.com... >> Any companys you know of in Toronto? > > > Just a suggestion: Post again under the subject "Looking for > internship near Toronto". And also post in sci.electronics.design. > There are a few Canadians who know the industry up there. Monster > might be another avenue (though I don't know if that one is free). I signed up on the UK Monster which is free but it does take a long time to get all your details into it. However, of all the agencies I gave my details to Monster generated by far the most calls. Admittedly many of them were completely unsuitable but agents tend to cast their nets wide when trying to fill a position. I'm happy with my current job but I still get calls despite taking my details down from Monster now - I guess some agents don't keep very up-to-date records but it shows that they are keeping people on their files. > Relocation: I wouldn't exclude other places. All my vacation jobs > during my university time were actually in other countries. Sometimes > I pooled my available rent money with a few others and then we found > we were able to rent a nice big house. Almost cost me less than my > apartment near the university. And you don't have to live off cans and > ramen noodles. It is amazing what you can cook out of fresh > ingredients, from scratch, if you have critical mass (enough cash > contributing eaters). We took turns shopping and usually cooked > together. Pizzas, casseroles and what not, all from scratch and for > little money. Yep, we made our own dough. I never ate any fast food > from the first day at the university until they handed me my masters. > Still don't :-) Joerg is totally right on this - the more of you there are the cheaper everything gets. However, you do need to get on well with your commune because everyone has to eat the same thing, use the same shampoo, share the same phone etc if it is going to work. You can make a big vat of spaghetti bolognese for well under $10 that will feed 4 people for days. Splash out on fresh basil though (or grow your own) because it makes all the difference.Article: 110460
Dear i done with Keep hirarchy "Yes" but again ILA Core of Chip Scope Pro not implement in design. Any other suggesion.Article: 110461
colin wrote: > Thanks for responding Rickman, I was begining to wonder about my > sanity. > > To answer John_H, Austin has replied in a new thread :) that I should > only boundary scan post config :- > -When configuration cannot be prevented > -When differential signaling standards are used" > > I had seen this before but SSTL is not differential. In fact Coolrunner > II use standard IO pins to become the vref inputs, needing to use one > IO for vref for every 6 SSTL inputs. Also the vast majority of Xilinx > cocumentation is FPGA centric without expressely saying so. > > > Rickman, the vast majority of webcases are hand holding of new users. > It doesn't matter how loudly Xilinx shout RTFM that is what the user > has not done. I allways expect to spend a few days getting Xilinx > support to understand that my question is not trivial and your not > going to change human nature which is not Xilinx induced. Allthough > perhaps changing a usenet thread title to something that is ultimately > embarrassing is a lesson that might not be forgotten. I don't think there is much you can say in this newsgroup that will have an impact on what Xilinx does. What you have seen so far is the typical response when they don't understand what you are saying. Rather than admit they don't get it, you get the sort of undignified responses you have seen. The hotline is not terribly good in many respects. The first person you get is typically a newbie, that's why their on the hotline, they can't do a lot else. You have to convince that person that the question is over thier head before you can move to the next level, and repeat the process. My experience has been that the first two levels of support can only provide info that Xilinx has published somewhere. To get an answer to a unique question like you are asking, you need to reach the third level of support. Think of it as a video game! If you really want a surprise, the person who has been replying without understanding what you are asking, is the person who is over the support group. Does that make you feel any better?Article: 110462
Davy wrote: > Hi all, > > I want to use SystemVerilog to construct next generation of my > testbench. > > And I found Synopsys provide VMM while Mentor provide AVM. Anyone can > give some comment on these two methodology? Or are they similar? > > I don't know if Synopsys's VMM is open document and open source code. > > The AVM cookbook/source code, you can download a free copy from: > http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm > > Best regards, > Davy Davy, sorry for the non-answer, but you may get better results with that question at http://www.verificationguild.com/ /EdArticle: 110463
"Frank van Eijkelenburg" <someone@work.com.invalid> wrote in message
news:45333f2e$0$11183$bf4948fe@news.tele2.nl...
> Is it possible to have a connection between two seperate user peripherals
> inside a Nios 2 system?
Yes...but more properly this would be called an SOPC Builder system....you
don't need to have Nios in there at all.
> Or do I have to route the signals outside the Nios 2 system and connect
> them at toplevel (like below)?
>
> nios_system : entity work.nios_system
> port map (
> clk => sys_clk,
> reset_n => locked,
> out_port_from_the_usr_peripheral_1 => usr_peripheral_shared,
> in_port_from_the_usr_peripheral_2 => usr_peripheral_shared
> );
The connections between the two user peripherals will need to be between two
Avalon interfaces not just a signal. In other words if you want to connect
just the single 'usr_peripheral_shared' signal between the two peripherals
you'll need to bring them out to the top level and connect them yourself as
you've mentioned.
If you want to keep it within the SOPC Builder system, the two user
peripherals then will each need an Avalon interface set of signals so the
two would look something like....
entity Peripheral1 is port(
.... -- Here you would have the existing Avalon interface signals to talk to
your Nios
read: out std_logic;
address: out std_logic_vector(1 downto 0);
read_data: in std_logic_vector(7 downto 0);
wait_request: in std_logic);
end Peripheral1;
entity Peripheral2 is port(
.... -- Here you would have the existing Avalon interface signals to talk to
your Nios
chip_select: in std_logic;
read: in std_logic;
read_data: in std_logic_vector(7 downto 0));
end Peripheral2;
Here I'm assuming that signal 'usr_peripheral_shared' is an output of
Peripheral2 that needs to go to Peripheral1. It would do so via one of the
'read_data' signals. I've also somewhat arbitrarily defined Peripheral1 to
be the Avalon master, Peripheral2 to be the Avalon slave which implies that
#1 needs to do a read from #2. You could also just as easily make #2 be the
master and #1 be the slave in which case change 'read' to 'write' and
'read_data' to 'write_data'. Within the two architectures you would then
have....
architecture RTL of Peripheral1 is
begin
read <= '1';
address <= (others => '0');
end RTL;
architecture RTL of Peripheral2 is
begin
read_data(7 downto 1) <= '-';
read_dta(0) <= usr_peripheral_shared;
end RTL;
In addition to whatever interfaces already exist on these interfaces
(presumably they each have at least one to talk to your Nios), each of these
components would also have this new interface and the signals in the entity
would then get mapped to the Avalon signal interface names (do this in
Altera's Component Editor).
It seems like a bit of overkill just to send one signal from one block to
another if you're really only talking about one signal but generally I find
that two components need to share much more than just one signal in which
case having a standardized way for them to talk is quite handy.
>
> BTW, is it possible to give ports from a user peripheral your own names in
> the generated nios_system.vhd file? (instead of out_port_from_the_... and
> in_port_from_the_...)
I think you're talking about the names as they exit the top level built by
SOPC Builder. If so, then I don't think so, but you can name them whatever
you want above that and hook up your signals via the port map. In other
words, don't use the SOPC Builder generated VHDL file as your top level. In
fact, if you do bring out your 'usr_peripheral_shared' signal and wrap it
back around you'll have to have such a wrapper anyway.
KJ
Article: 110464On 15 Oct 2006 11:24:46 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >> > Antti, >> > >> > I'm really shocked you would post a URL like this >> > to this newsgroup. I urge everyone to avoid >> > visiting this ridiculous site. >> On the contrary, this is not spam. It is on topic (fpga's) and isn't >> selling anything. >Hi Alan, > >first :) - tnx. ... >so here is the direct >and hassle free download link to the same schematic. > >http://www.antti-brain.com/xil_jtag.pdf > >Antti >PS the link referenced in the original posting is auto-deleting in 30 >days last download. Hi Antti, I agree the original post wasn't SPAM, but that website is simply NASTY! and though I went through its rigmarole five or six times, it kept on saying the download session was invalid... Perhaps it only works with Internet Explorer or something. so... Thanks for the direct link! And thanks for all your generous contributions to comp.arch.fpga. - BrianArticle: 110465
i already have starter board for xilinix spartan 3, which i bought directly from digilent (so i did't receive EDK CD). im planning to buy started kit for spartan 3E from xilinx this time, which include EDK evaluation CD. Is this worth? are there any other freely available packages similar to MacroBlaze / EDK/ platform studio combination? thanksArticle: 110466
http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm already pricing given for 1000qty not bad at all. unfortunatly the LXT related user guides ug194 EMAC ug196 GTP ug197 PCIe are all deadlinks at the moment but hopefully those documents become available shortly. new eval boards (besides ML501) are ML505 - allows PCIe testing ML523 - GTP characterization board ML555 - 8x PCIe card GTP has OOB support for PCIe/SATA and supports spread spectrum clocking as well. AnttiArticle: 110467
Antti schrieb: > http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm > > already pricing given for 1000qty not bad at all. > > unfortunatly the LXT related user guides > ug194 EMAC > ug196 GTP > ug197 PCIe > > are all deadlinks at the moment but hopefully those documents become > available shortly. > > new eval boards (besides ML501) are > > ML505 - allows PCIe testing > ML523 - GTP characterization board > ML555 - 8x PCIe card > > GTP has OOB support for PCIe/SATA and supports spread spectrum clocking > as well. > > Antti correction ug194 and ug196 are already available (appearead 6 minutes after the post), so the only missing one is the PCIe UG myselfArticle: 110468
Colin, With regards to being the longest webcase, if you don't see the "record overflow" message in the Webcase viewer, you've still got a ways to go :) I've hit 3-4 months, without ever getting definitive answers, and CR's and documentation errors still unresolved 3.5 years later. Answer Record 15346 states that the I/O behavior changes post configuration to match the I/O standard for 'most' families- perhaps you should point Xilinx at that Answer Record and ask them to explicity define if 'most' applies to CoolRunner-II : " " For most Xilinx device families, the boundary scan architecture " changes after the device is configured because the boundary scan " registers sit behind the I/O buffer and sense amplifier: " " BSCAN Register -> IO buffer/sense amp -> PAD " " The hardware is arranged in this way so that the boundary scan " logic operates at the I/O standard specified by the design. This " allows boundary scan testing across the entire range of available " I/O standards " Also from 15346, re. the I/O behavior of pins post-config: " " Pins configured as outputs are described as "inout" because the " input boundary scan cell remains connected even when the pin is " used only as an output. Describing the output as an "inout" reflects " the actual boundary scan capability of the device and allows for " greater test coverage. " colin wrote: > > Austin has replied in a new thread :) that I should > only boundary scan post config :- > -When configuration cannot be prevented > -When differential signaling standards are used" > Austin's selective quoting of that page would read quite differently had he also included the surrounding text: " " Whenever possible, boundary scan tests should be performed on an " unconfigured Xilinx device.Unconfigured devices allow for better test " coverage, since all IOs are available for bidirectional scan vectors. " " Boundary Scan tests on Xilinx devices should only be performed after " configuration under the following circumstances: " -When configuration cannot be prevented " -When differential signaling standards are used " " Mandatory modifications " If a post-configuration BSCAN test is required then the BSDL file " must be changed. Currently the user will have to manually modify " the BSDL file as per answer record 6664 . " BrianArticle: 110469
Hi Davy, Sorry, can't answer your question since I don't know SystemVerilog and I use Modelsim (VHDL+SystemC). I believe the examples are written in generic SystemVerilog/SystemC so I would suggest to just try it out, Hans. www.ht-lab.com "Davy" <zhushenli@gmail.com> wrote in message news:1160989035.881120.256220@f16g2000cwb.googlegroups.com... > > Hans wrote: >> Hi Davy, >> >> The AVM cookbook from Mentor describes these terms, you can download a >> free >> copy from: >> >> http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm > [snip] > Hi Hans, > > Can I use base class mentioned in Mentor's AVM cookbook in other > simulator like Cadence's NCSim? > > Best regards, > Davy >> >> Hans >> www.ht-lab.com >> >> >> "Davy" <zhushenli@gmail.com> wrote in message >> news:1160799509.696951.204680@b28g2000cwb.googlegroups.com... >> > Hi all, >> > >> > IMHO, there is something compare the golden output and DUT output in >> > testbench (I call it Checker). But in verification book, there is both >> > Scoreboard and Checker. Are they similar? >> > >> > Please recommend some reading on it.Thanks! >> > >> > Best regards, >> > Davy >> > >Article: 110470
Hi, alessandro basili schrieb: > Daniel Leu wrote: > > > > Routing depends on your design structure. Even with high device > > utilization, Designer usually is successful. If routing fails or you > > can't get timing closure, you can try place&route with the "Multiple > > Passes" option. > > I will try it, thanks. Does it have any drawback? It cost only time by doing effectly several runs and using the best result (you could even have the results from all runs saved on HD) I think, that timing critical layout gets a bigger problem if your utilisation is >>95% (YMMV I had only one A54SX72 design exceeding 95% sequential resources). > I thought that this is what the back-annotate does, am I wrong? > I usually do the back-annotate and then do the post-layout simulation > with Model-Sim (unfortunately by the mean of Libero IDE, that I > personally hate, but still didn't have time to make rid of it). > What do you mean by "gate-level simulation"? I never used the IDE, what causes your pain? The export of netlist and sdf from designer tool is very simple (I wish all Vendors would allow such a simple export of data in their tools). bye ThomasArticle: 110471
jacko wrote: > Henry Wong wrote: >> jacko wrote: >>> hi >>> >>> got the tester of model sim from altera, but it seem even though i set >>> the environment var from the system control panel, it don't appear >>> hence con not find file. this is both quartus II which has other >>> methods so no problem, and modelsim which does not find any environment >>> variable. >>> >>> don't work from command.exe either. >>> >>> any help would be appreciated. >>> >>> cheers >>> >> If this is on Windows, I believe the syntax is >> >> echo %LM_LICENSE_FILE% >> >> Also note that at least on my system, it's spelled "licenSe". >> >> Not sure if this helps. > > got the echo working using % but still no luck finding it even with the > S. it's definatly there. > Use "set" from a command prompt to view all the environment variables in windows. Also note that if you change an environment variable in the control panel, it only affects programs started after the change. If you open a command prompt, then make the change, you will not see the effect in the opened prompt - you need to open a new prompt.Article: 110472
If you just need to repeat the packets on a different frequency (not demodulate and remodulate) then you can probably use the gnu radio USRP with the flex2400 transceiver. Just google "gnu radio". -Clark "Token" <ramukumban@gmail.com> wrote in message news:1160983718.255657.65840@m7g2000cwm.googlegroups.com... > I just started learning about fpga technology, I am looking for a > solution to this minor problem. > I'm supposed to build a physical layer repeater for a Wi-Fi signal > using any of the xilinx products.this is actually a simulation project > for school. the intial part is just a physical layer repeater. then > i'll have to add the data link layer components for the final part of > the project. Any assistance, suggestions will be appreciated. >Article: 110473
David Ashley schrieb: > u_stadler@yahoo.de wrote: >> hi >> >> well thanks for all the answers so far. >> i 'm still trying to get some more speed out of edk. >> well as said before i'm not doing anything fancy. just straight forward >> stuff and i was wondering what good the ethernet core is if i can't get >> it to synthesize with more than 59 MHz. i have also tried to export it >> to ise. i mean there must be a trick somewhere or has nobody used >> microblaze with ethernet in a spartan 3e yet? >> any suggestions would be very helpful >> >> thanks >> urban >> > > I was pretty sure someone recently had just that running > on the spartan-3e starter board. Uclinux with networking > and I think it was microblaze. Look in the archives, like > in the last 1-2 months. uClinux does run on the Spartan-3e starter board. If the design doesn't reach at least 65 MHz you can still use the Ethernet core at 10 MBit - 6.5 MHz bus clock is sufficient. Make sure half-/full-duplex and speed is set correctly, because auto negotiation doesn't seem to work reliably. Regards, AndreasArticle: 110474
Andreas Hofmann schrieb: > David Ashley schrieb: > > u_stadler@yahoo.de wrote: > >> hi > >> > >> well thanks for all the answers so far. > >> i 'm still trying to get some more speed out of edk. > >> well as said before i'm not doing anything fancy. just straight forward > >> stuff and i was wondering what good the ethernet core is if i can't get > >> it to synthesize with more than 59 MHz. i have also tried to export it > >> to ise. i mean there must be a trick somewhere or has nobody used > >> microblaze with ethernet in a spartan 3e yet? > >> any suggestions would be very helpful > >> > >> thanks > >> urban > >> > > > > I was pretty sure someone recently had just that running > > on the spartan-3e starter board. Uclinux with networking > > and I think it was microblaze. Look in the archives, like > > in the last 1-2 months. > > uClinux does run on the Spartan-3e starter board. If the design doesn't > reach at least 65 MHz you can still use the Ethernet core at 10 MBit - > 6.5 MHz bus clock is sufficient. Make sure half-/full-duplex and speed > is set correctly, because auto negotiation doesn't seem to work reliably. > > Regards, > Andreas actually the ethernetlite uclinux driver was submitted to cvs yesterday, so its also possible to use the ethernet lite with 100M (and 50MHz system clock) Antti
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