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Austin Lesea wrote: > ralphie, > > Perhaps I am missing something? > > Rick mentioned "significant" penalty for reconfiguring, and I pointed > out that a few hundred mA (at the most) is all we are talking about. > > It is up to the engineer to decide if a few hundred mA is significant, > given the benefit (don't reconfigure, need a larger part with more > leakage, do reconfigure, and you can potentially use a much smaller > part, more efficiently). > > No one mentioned turning things off, or "sleep" modes as far as I know. > > Really very simple, and very straightforward. > > If you also bring into the mix just turning everything off, then doing > anything at all, other than leaving everything off, that is infititely > "significant" (anything more than 0). Designers also have the option to lower Vcc, to go into a Hold-Pgm mode, and so they trade off the energy of doing that, against the energy of full removal, and then reconfig. This shifts the static cost down, so moves the Config power higher up the significance scale. I've not seen FPGA vendors spec a 'energy optimium' vcc for config. Also look at other vendors, some offer more choices on power-save modes. uC designers are fairly used to all this. -jgArticle: 110401
David Ashley schrieb: > u_stadler@yahoo.de wrote: > > hi > > > > well thanks for all the answers so far. > > i 'm still trying to get some more speed out of edk. > > well as said before i'm not doing anything fancy. just straight forward > > stuff and i was wondering what good the ethernet core is if i can't get > > it to synthesize with more than 59 MHz. i have also tried to export it > > to ise. i mean there must be a trick somewhere or has nobody used > > microblaze with ethernet in a spartan 3e yet? > > any suggestions would be very helpful > > > > thanks > > urban > > > > I was pretty sure someone recently had just that running > on the spartan-3e starter board. Uclinux with networking > and I think it was microblaze. Look in the archives, like > in the last 1-2 months. > > -Dave > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architecture David you are right there is s3e500 uclinux design from www.petalogix.com but they use ethernet lite that has only 50mhzrequirement. unfrotunatly petalogix is not releasing the ethernet lite driver source codes (GPL !) so other can not use the ethernet lite core with uclinux yet. AnttiArticle: 110402
Peter Alfke schrieb: > On Oct 14, 10:47 am, "rickman" <gnu...@gmail.com> wrote: > > Documentation is often the poor stepchild of a development process.... > > > Personally I take pride in the documents I prepare. I never want > > anyone to read one of my documents and think it was written by a moron, > > even if it was! ;^) > > Same here. Through the XC3000 and XC4000 generations, I put together > every databook, from deciding the format and pagination to writing much > of the text, to negotiating the detailed descriptions and even the > parameter values. It was pretty much a one-man show. But the parts were > simple... > Then Xilinx got bigger and various people had to share the "fun". > > Documenting programmable logic may be more difficult than documenting > memories, microprocessors or ASSP dedicated circuits. FPGAs are used in > a myriad of ways by hundred thousands of designers with widely varying > backgrounds and skills. > > The person(s) in charge of documentation must be technically savvy in a > wide area, be able to write clear and reasonably tight English > sentences, have the eyes of an eagle, and the patience of Job. They > must be self-confident and persistent without becoming obnoxious, and > it helps when they have a respected and senior position in the company, > so that they can circumnavigate committees and get things implemented > or changed. That's a tough job desciption. > No wonder we do not always live up to the highest expectations. But we > are still trying... > Peter Alfke, Xilinx, fom home Peter, yes it looks the Xilinx documentation situation is way more complex now. after woopla with Virtex-4 (symon in printed documentation, sysmon in silicon - but disabled by software tools) Xilinx seems to be more careful not having data in datasheet. Virtex-5 (at least LXT) is claimed to be available NOW - in the matter of fact it is I have both parts and Xilinx SEG manufactured development board, but the datasheets are not yet available. Or ok there are datasheets available with partial information. I assume the datasheets will be fixed with next ISE service pack but at Xilinx website there is not schedule for the next ISE SP! current Virtex-5 datasheets dont have any information about 1) sysmon 2) R_FUSE and VFS pins 3) possible several other things (I havent looked if the CRC32, CRC64 are documented) ok, this is new product development related. but when I opened webcase because of errors in Coolrunner datasheet then the Xilinx response was, what you think? Fixing the datasheet? No the information was just removed, not fixed. It was regarding MC term numbers, it is not important to most of users, ok it is maybe only useful for those who write a PLD fitter. Still the partially available and wrong information was not fixed but removed (after my webcase). AnttiArticle: 110403
>On Oct 13, 12:46 pm, pbdel...@spamnuke.ludd.luthdelete.se.invalid >wrote: >> >I've been reluctant recently on envisaging a Virtex-4 device as being >> >operational in a battery-powered situation. The inrush configuration >> >current, high static power consumption, and the non-uniform power >> >exhibited subject to temperature rise are amongst few to name about the >> >shortcomings of SRAM FPGAs in general. Having said that, the >> >unprecedented versatile reconfigurable processing power is yet the >> >decisive factor in prototyping intensive DSP operations. My question >> >is: has any body come across a scenario in which a large FPGA was >> >battery-powered. I'm in the phase of deciding on solutions to employ >> >for my active research so it's quite critical. I don't want to start my >> >research with a major gap in my rationale. Can any veteran in here >> >comment on the topic please. Is it really ridiculous to think about >> >powering a large SRAM FPGA from a battery? Would really appreciate all >> >comments. What's the cheapest price ever a smallest Virtex-4 device was >> >reported? >>You said Xilinx fpga, but maybe actel's eeprom (?) based fpgas will do better >> for battery applications? Peter Alfke <alfke@sbcglobal.net> wrote: >Reconfiguration time is measured in ms (especially for a small part). >And, as Austin told you, reconfiguration does not take much current, >probably less than normal operation. >So it all depends on the frequency of reconfiguration (once a minute, a >second, or a ms?) and on the savings in static and dynamic power (and >money) you get from using a smaller part. >No need to generalize, but it should be easy to assess your individual >situation. My idea was that eeprom cells would use less power after powerup. I dault the powersurge (if any) is a power consumption problem.Article: 110404
how to change the CCLK frequency for FPGA in master-serial mode? I try to set the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock..Article: 110405
Jim Granville schrieb: > eg I have a Flash-RAM CPLD here, that is appx 200x more Icc during > Config load, than static icc. To me, that certainly IS significant. But that one is not built in a 65nm technology, right? Static sv. dynamic power consumption changed a lot with newer technologies. Kolja SulimmaArticle: 110406
i also thought that but then i read the description: <http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0109_70.html> KEEP Description KEEP is an advanced mapping constraint and synthesis constraint. When a design is mapped, some nets may be absorbed into logic blocks. When a net is absorbed into a block, it can no longer be seen in the physical design database. This may happen, for example, if the components connected to each side of a net are mapped into the same logic block. The net may then be absorbed into the block containing the components. KEEP prevents this from happening. KEEP is translated into an internal constraint known as NOMERGE when targeting an FPGA. Messaging from the implementation tools will therefore refer to the system property NOMERGE—not KEEP. and tried it out but no change ... i think i will go for antti's idea and just make some small logic to an unbound pin so it does not get removed ... too bad there is no constraint for this ... kind regards, Tim Brian Drummond wrote: > On 13 Oct 2006 02:13:55 -0700, "Tim Verstraete" > <tim.verstraete@barco.com> wrote: > >> Hey, >> >> I have 2 LVDS clock signals and both are terminated with the DIFF_TERM >> attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them >> ... now i want both buffers to stay in my design and not optimized >> away. Is there a constraint that i can place on that buffer? i guess >> that it should be a UCF constraint since when i look into the RTL >> viewer of planahead and ISE i still see the buffer. > > Look into "keep" attributes. See the Constraints Guide for details. > > (Sometimes "keep" attributes don't work though. On registers, they are > overridden by "equivalent_register_removal" and result in an obscure > error message instead. I haven't tried them on clock buffers) > > - BrianArticle: 110407
Matthew Hicks wrote: > You could try turning off the "Trim unconnected signals" option. > > > ---Matthew Hicks > > > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1160731469.227624.198590@f16g2000cwb.googlegroups.com... >> Tim Verstraete schrieb: >> >>> Hey, >>> >>> I have 2 LVDS clock signals and both are terminated with the DIFF_TERM >>> attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them >>> ... now i want both buffers to stay in my design and not optimized >>> away. Is there a constraint that i can place on that buffer? i guess >>> that it should be a UCF constraint since when i look into the RTL >>> viewer of planahead and ISE i still see the buffer. >>> >>> I know that there is an option in NGBuild -u which keeps the unused >>> logic, but i do not want to use it just for that 1 buffer ... >>> >>> thanks in advance, >>> >>> kind regards, >>> >>> tim >>> >>> p.s. i'm using ISE8.2SP2 and a V4SX55-FF1148C >> the best thing possible is to use it without using it :) >> 1) like route the unused input to non-bonded IO, >> 2) or use in some net in way that the signal isnt really used but XST >> fails to optimize it out >> 3) or if you dont use BSCAN you can also route it to TDO pin >> >> all those tricks would keep the net alive. sure it would use >> some interconnect resources. >> >> Antti >> > > indeed but then it does not optimize the part i do want to be optimized ... because it is a global option ... i was just hoping there was some constraint somewhere ... kind regards, TimArticle: 110408
Peter Alfke schrieb: > Most of use even understand percentages... Yes, at least 75% of us. But the remaining half cannot even spill simple words correctly. Kolja SulimmaArticle: 110409
wolflame schrieb: > how to change the CCLK frequency for FPGA in master-serial mode? I try to set the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock.. you cant change the initial CCLK rate, its always default, only when special command sequence is shifted in the CCLK clock frequency changes to its programmed value AnttiArticle: 110410
yttrium schrieb: > i also thought that but then i read the description: > > <http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0109_70.html> > > KEEP Description > > KEEP is an advanced mapping constraint and synthesis constraint. When a > design is mapped, some nets may be absorbed into logic blocks. When a > net is absorbed into a block, it can no longer be seen in the physical > design database. This may happen, for example, if the components > connected to each side of a net are mapped into the same logic block. > The net may then be absorbed into the block containing the components. > KEEP prevents this from happening. > > KEEP is translated into an internal constraint known as NOMERGE when > targeting an FPGA. Messaging from the implementation tools will > therefore refer to the system property NOMERGE-not KEEP. > > and tried it out but no change ... > > i think i will go for antti's idea and just make some small logic to an > unbound pin so it does not get removed ... > > too bad there is no constraint for this ... > > kind regards, > > Tim there is ASFAIK no way to use constraints to set options on used by the logic pins. this is sometimes real problem - you may want to have different unused pins to have optional pulldowns or pullups but this cant be specified unless those pins are used by the design it would be possible by patching the bitstream, but I am little behind with my bitpatch application at the moment AnttiArticle: 110411
Tommy Thorn schrieb: > I'm surprised none have mentioned it, but the Xilinx ML501 has finally > been released officially, even though it's not available online yet. > > Press release: > http://www.xilinx.com/prs_rls/2006/silicon_vir/06103ml501.htm > Board info: http://www.xilinx.com/ml501 > > It looks to be a very compelling kit. Unfortunately for me, the > XC5VLX50 isn't supported by the WebPACK and unlike with the original > ML401 release, software is _not_ included so unless you can afford the > full ISE package also, don't bother. > > Tommy If Xilinx has the same policy regarding WebPack as with Virtex-4 then I would expect WebPack 9.x to support V-5 LX30,LX50 (and smallest FX) In the meantime you can get 8.2 60-day eval, and who knows in 60 days the 9.1 maybe released? Of course it may also be possible that WebPack will not include V-5 ever this is of course big hit tho those who had Base-X license what was reduced to WebPack (as BaseX featured are now in WebPack). Well we have to wait, ISE 8.2 is not going to support whole V-5 family anyway, so things will get more clear with 9.x release I suppose. AnttiArticle: 110412
Hi to everyone, i've started using Libero 7.2 and I found a very nice feature (let's say), when you import package files from your package directory, it just copy it to the hdl directory and use them. In case you want to change the package is useless changing it in the package directory because it will use the one that has been copied on the hdl directory. Is it reasonable??? Can anyone explain me the advantages that this "hidden" behaviour will lead to, either than making people crazy? Thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110413
unverified and only has the important FX2 <> CPLD connections http://rapidshare.de/files/36822701/xil_jtag.pdf.html AnttiArticle: 110414
Hi, Sorry for the cross-post, but I think this is a relevant topic in both newsgroups. Has anyone come across this paper ? T.K. Troung, Ming-Tang Shih, I.S. Reed, E.H. Satorius, "A VLSI design for a trace-back viterbi decoder", IEEE Tranactions on Communications, Vol. 40, No. 3, March 1992. They describe a register-based systolic approach to implement the traceback that they claim requires "a minimal amount of storage and a short decoding time", when compared to the register exchange and traceback memory methods. I can see that this method would indeed provide a short decoding time, but I don't agree with the storage claim. For example, a rate 1/2, K = 9 code would require (256*2*45) + 8*45 = 23400 registers, just for the traceback portion (traceback length = 45). Using the one-pointer traceback RAM method (which uses the highest amount of RAM), we would need 45*256*4 = 46080 bits which would I guess, would still be more area efficient to implement. Is the traceback (RAM) method using the k-pointer (or R-pointer ??) algorithms still the best way to go to implement traceback in viterbi decoders (in terms of a decent tradeoff between area-efficiency and decoding delay) ? Thanks, Vijay.Article: 110415
i have read the edif file but i am not sure what is top level in it. is
there any document which expalins edif file format? i guess the word
"design" indicates what is top level. i found this at the end of the
file :
" (design ROOT
(cellRef xr16vx_1k
(libraryRef xr16vx_1k)))
so i renamed the edif file to ROOT.edf and also changed it in the vhdl
file where i instantiated this. but still i am getting the same error.
how can i find the top level entity name and input and out put ports
from edif file while opening it in text editor?
Duane Clark wrote:
> Avion wrote:
> > very valid argument, schematics have this inherent drawback. anyway, i
> > tried to use vhdl but i was unable to get the .bit file and process
> > fails with error "NgdBuild:76 - File
> > "D:\Xilinx\bin\xr16vx\_ngo\xr16vx_1k.ngo" cannot be
> > merged into block "ROOT" (TYPE="xr16vx_1k") because one or more pins
> > on the
> > block, including pin "rs232rx_IPAD_IN", were not found in the file.
> > Please
> > make sure that all pins on the instantiated component match pins in
> > the
> > lower-level design block (irrespective of case). If there are
> > bussed pins on
> > this block, make sure that the upper-level and lower-level netlists
> > use the
> > same bus-naming convention."
> > i am using webpack 8.2i. i have cross checked the port names by
> > converting ngd file to vhdl with ngd2vhdl and port names are exactly
> > the same. but still i am getting above message. any idea where i am
> > wrong? or how can i confirm port names of an edif design file?
>
> edif files are plain text, so they are easy to check. If your starting
> file is edif then look there. I have found that the top level entity
> name in the edif file needs to match the filename (or maybe I have not
> discovered the right flags to use). That is, if the file is
> xr16vx_1k.edf, then the top level entity within it needs to be named
> xr16vx_1k, and that is the name you instantiate within your
> HDL/schematic. It seems to me that when I have run into that error, it
> was not really the right location for the error. Check all the signal
> names and the top level edif entity name.
Article: 110416What endless repetition? It seems very clear at this point that Austin is stuck in the rut of comparing only current and not realizing that the device can be completely powered down in a real application. I still have not seen a post by him that acknowledges that. It only makes sense that if you have modes where a device is not used and the static current is significant, you would not keep it powered up. If you keep power on it, then why would you need to reconfigure it when you are ready to use it again? No, this may not be what the OP was talking about, but this is what I have been talking about. This is what I do on some of my designs. Many chips are capable of very low currents when powered but not used, including some brands of FPGAs. But when I need low power and parts like a Xilinx FPGA are not in use, I remove power to eliminate the high static power consumption. If I can't afford the time or the energy required to reconfigure (short duration of run time relative to the configuration time) then I have to use one of the brands of FPGA that are instant on. This even excludes some of the Flash FPGAs because they are dual mode with the Flash being copied into RAM. It is very clear that Austin is reading from a different page. My post was an attempt to get him to understand what was being discussed. I still don't see what you are complaining about. Power is what is stored in the battery and is related to the product of current and time. I can draw very large currents for a short time and not deplete the battery significantly. I can also draw very low currents and make a significant dent in the battery if the time is long. Austin simply did not address this in his posts. I don't appreciate your kindergarten comment. You continue to make it by saying "also". Please refrain from personal comments like this. It is not appropriate in this newsgroup. Peter Alfke wrote: > No knickers in a knot (interesting analogy). I was just tired of the > endless repetition of very simple calculations. > Regarding power-down: Some people think that sleep mode or idle mode > means powerdown (which it did, 10 years ago. Today you really have to > lower Vcc to a very low value in order to save the leakage current.) > But now I also sank to the kindergarten level. > Just because this is a newsgroup, we do not need to repeat the same > simple statements ad nauseam. > Peter Alfke > > On Oct 14, 7:01 pm, "ralphie" <ralphmalph_f...@yahoo.com> wrote: > > Peter Alfke wrote: > > > Ralphie, let's not sink to kindergarten level. We all can multiply > > > current and time. Most of use even understand percentages... > > > The OP did not give any specific values, and the thread has > > > deteriorated into generalities. > > > > > Notealso that there are different degrees of powerdown. As long as you > > > maintain Vcc, you have leakage current,which (unfortunately) is > > > significant in state-of-the -art FPGAs. > > > 'nough said. > > > Peter AlfkeWhat's up with you? No one's gotten offensive until you made the > > kindergarten comment. From his post it is clear that he is missing > > something about the problem being stated. I didn't get offensive about > > this. I just explained with plenty of detail to clear up the point of > > confusion. > > > > Of course it is possible that you don't want to clarify the point of > > confusion, I can't say. But I don't get what you mean when you say > > "there are different degrees of powerdown". Power down to me has always > > meant *no* power. Is there some other power state that is called > > "powerdown" that I don't know about? How do you mean the term? If you > > maintain Vcc, why would you need to reconfigure the FPGA? > > > > What is going on here? I am just trying to discuss a technical issue. > > Don't get your knickers in a knot!Article: 110417
alessandro basili schrieb: > Hi to everyone, > i've started using Libero 7.2 and I found a very nice feature (let's > say), when you import package files from your package directory, it just > copy it to the hdl directory and use them. In case you want to change > the package is useless changing it in the package directory because it > will use the one that has been copied on the hdl directory. > Is it reasonable??? Can anyone explain me the advantages that this > "hidden" behaviour will lead to, either than making people crazy? > Thanks a lot > > Al > > -- > Alessandro Basili > CERN, PH/UGC > Hardware Designer things are not always reasonable. the libero/designer is just to make people crazy. use it at the minimum, that is prepare all files using some other tools, then port to libero and try to get the bitstream file minimizing the work you do with libero. AnttiArticle: 110418
the default template for the Virtex-5 DSP48E block doesnt load into Xilinx internal simulator in ISE 8.2 SP3 there is a simple fix though the problem is one attribute being wrong/unregonized by isim type so the fix is just changing that one attibute from string to boolean, after that isim will load and simulate properly AnttiArticle: 110419
It obviously has to be this way, so that the beginning of the bitstream can be loaded in the least demanding way. Pter Alfke, Xilinx On Oct 15, 3:24 am, "Antti" <Antti.Luk...@xilant.com> wrote: > wolflame schrieb: > > > how to change the CCLK frequency for FPGA in master-serial mode? I try to set the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock..you cant change the initial CCLK rate, its always default, only when > special command sequence is shifted in the CCLK clock frequency changes > to its programmed value > > AnttiArticle: 110420
Antti wrote: > > things are not always reasonable. > the libero/designer is just to make people crazy. > > use it at the minimum, that is prepare all files > using some other tools, then port to libero and try to get the > bitstream file > minimizing the work you do with libero. This is what I usually do, I use emacs to edit vhdl, synplify to synthesize it and Modelsim to simulate it and Designer to make the P&R and to generate the back-annotate vhdl for the post-layout simulation. Unfortunately I'm still not able to use them without the Libero setup, which configures all the libraries to compile and everything, but it makes you crazy. I thought about migrating on something smarter but still don't have other choices. > > Antti > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110421
Thank you, rickman, for that lecture. Kindergarten seems to be a dirty word... But people in glass houses should not throw stones. (Remember your ongoing personal attacks on Austin?) I just got impatient with these trivial arguments running in a circle, making generalized comments, when everything depends on the specific circumstances. We have better things to do than that... Peter AlfkeArticle: 110422
Antti, As I write this, V5LXT (and SystemMonitor) has not yet been officially announced or released. But, hold your breath, it will be "soon". As I mentioned once before, a Product Announcement is a rutual dance, involving not only Xilinx, but also the press. And they are obsessed about the "virginity" of the information. So we have to keep mum. But soon we can discuss this openly. I am glad you got the ML501 board faster than anybody thought. But it has an 'LX, not LXT device on it. We will look at the other points in your posting. PeterArticle: 110423
Antti wrote: > unverified and only has the important FX2 <> CPLD connections > > http://rapidshare.de/files/36822701/xil_jtag.pdf.html > > Antti > Antti, I'm really shocked you would post a URL like this to this newsgroup. I urge everyone to avoid visiting this ridiculous site. -DaveArticle: 110424
rick, You missed my last post? Austin
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