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As I think everyone has said this isn't a simple task. We do a lot of obsolete component replacements in FPGA and CPLD and mainly they are massively less complicated that a 486. They take a lot of time to get anything like an exact match and even then you get other factors like power consumption is much less, or more, that causes secondary issues. I/O timing also tends to be hard to replicate exactly even if you have a 500 MHz clock that will allow placing of edges to a 1 ns resolution when using both edges of the clock. On this level of complexity you would be talking a very expensive, long timescale and possibly not achieveable project. I would say you would be better reverse engineering at a higher level say the I/O of your board. John Adair Enterpoint Ltd. enavacchia@virgilio.it wrote: > Hi all! > > We've some custom boards with i486 processor, some RAM, some dual port > ram and other stuff (interrupt controller, buffers, I/O transceiver and > so on). I'm investigating the opportunity to replace all of those > discrete ICs with soft/hard IP (cycle accurate), and syntesize the > system in an FPGA (Altera or Xilinx). > > Actually I don't care about costs and efforts that are involved in this > approach. The goal is to get a replacement for that processor without > re-writing the operating system and any other kernel routines. > > Any suggestions?Article: 110751
enavacchia@virgilio.it wrote: > We've some custom boards with i486 processor, some RAM, some dual port > ram and other stuff (interrupt controller, buffers, I/O transceiver and > so on). I'm investigating the opportunity to replace all of those > discrete ICs with soft/hard IP (cycle accurate), and syntesize the > system in an FPGA (Altera or Xilinx). Since you are asking for a board level replacement, there is a good chance that the primary worry over generating a 486 FPGA that is cycle accurate isn't a real concern, as long as the board performs correctly at the connectors. > Actually I don't care about costs and efforts that are involved in this > approach. The goal is to get a replacement for that processor without > re-writing the operating system and any other kernel routines. While softcore construction of an FPGA i486 is possible (and probably expensive) I would strongly suggest backing off and considering a system level replacement, that remains binary compatable, which might include an inexpensive embedded processor with an FPGA/PLD for the glue logic capable of executing your current bit files. There are alternative solution paths from a systems perspective that are probably remarkably easy to implement, and fairly low cost in both NRE and unit cost. My company DMS Design is used to these problems, and would certainly look forward to talking more if you plan to issue a contract to provide these new subsystems. We can do both design, and production to your specifications, with very competitive rates.Article: 110752
shadfc wrote: > Anyway, I've got to the point where my code simulates perfectly, but > when testing on different FPGA boards, I get mixed results. I recently > purchased a Xilinx Spartan-3E Starter Kit with a 500k gate chip. When > I program my project into this board, it does nothing but go to the > default state. None of the keys that are supposed to be recognized > are. We also have a board that our professor loaned to us which is a > Xilinx Spartan-3 with a 200k gate chip. On this one, the code > functions pretty well and the keys are recognized. I hesitate to ask a silly question, but you are completely re-compiling the code for the different board, right? That is, you are not trying to load the same .bit into both boards, right? Do you have the part number specified correctly and have you checked the .ucf file? I only ask because you said you are new at this... Alan NishiokaArticle: 110753
Aaron Curtin wrote: > Hi, I have a design that connects a Spartan 3e running a Microblaze > soft-core with an SPI unit attached to the OPB bus to a 16 Bit DAC unit > (DAC8534). The data I send to the DAC unit has the bit order reversed. > The SPI_OPB pheripheral has no way of reversing the shift out order > from what I can see. I can't see a parameter for reversing the bits either. The source for opb_spi is in c:/EDK81/hw/XilinxProcessorIPLib/pcores/opb_spi_v1_00_d/ Copy it to your local pcores directory and modify it. Then use your local copy. Alan NishiokaArticle: 110754
Andy Peters wrote: > fpga_toys@yahoo.com wrote: > > Mike Treseler wrote: > > > Sorry I rained on your parade. > > > Trial and error synthesis using a logic analyzer works also. > > > I guess I spent too many years hooking up those > > > little clip leads and waiting for a trigger. > > > > Not only are HP16xxx logic analyzers cheap on eBay these days, > > Anyone want mine? > > > but making one out of an FPGA is yet another fun project. > > it's real easy. The hard part is coming up with some nice host > software! Here is one for the Digilent/Xilinx S3 kit that comes with PC software: http://www.sump.org/projects/analyzer/ LeonArticle: 110755
On Fri, 20 Oct 2006 14:23:29 +0100, Evan Lavelle <eml@nospam.uk> wrote: >Anyone happen to know if there are any problems with sdf simulation >for Spartan-3? This works a lot of the time for me, but I get >occasional setup failures, with messages like > ># ** Warning: /X_SFF SETUP Low VIOLATION ON I WITH RESPECT TO CLK; > >Generally, everything else fails soon after a setup violation. Any asynchronous signals or clocks in this design? If this FF is a synchroniser, there is an attribute you can attach to indicate such, so it will not propagate 'X' to the rest of the design (hence the rest failing soon after). Unfortunately I can't remember the attribute. If not, it could indicate an asynch path that needs a synchroniser. - BrianArticle: 110756
On 20 Oct 2006 22:06:32 -0700, "shadfc" <jay.wineinger@gmail.com> wrote: >Hey everyone, I'm fairly new to VHDL and especially to synthesizing >code to program an FPGA. For a class project, I developed a FSM that >received its inputs from a ps/2 keyboard. >Anyway, I've got to the point where my code simulates perfectly, but >when testing on different FPGA boards, I get mixed results. I recently >purchased a Xilinx Spartan-3E Starter Kit with a 500k gate chip. When >I program my project into this board, it does nothing but go to the >default state. None of the keys that are supposed to be recognized >are. The "silly question" that occurs to me is, have you connected the inputs and outputs correctly? Device pins are connected to signal names in the user constraint file, e.g. "mydesign.ucf". But the keyboard and display signals will be on different pins on the two boards; therefore you need two different UCF files; e.g. mydesign_s3_200.ucf and mydesign_s3e_500.ucf. The design must be re-implemented with the appropriate UCF file to generate a bitfile for the new board. Synthesis may or may not be OK, depending on the differences between S3 and S3E. If you were merely moving between different sizes of S3, you would only have to re-run Translate/Map/Par and Gen Bitfile. You can make a new UCF file by copying the original and changing the pin "LOC" constraints with a text editor. (The pins wired to the keyboard etc should be specified in the board's documentation) Hope this helps. - BrianArticle: 110757
aijazbaig1@gmail.com wrote: > [...] > as the synthesis tool 'realises' such a block in the FPGA. The only > restriction we have is that we should write code keeping in mind the > actual hardware capabilities of the board and/or the target device. > Like incase of the XC2S50 device we can instantiate 8 blocks of 4K bits > each and so on. > Is my thinking correct in this regard or is there something which i am > overlooking and/on misinterpreting? That looks correct, as does your other conclusions that followed (which I've cut). The only other thing that may need a comment is: [...] > A last question: If I want to have more than 16 bit wide data bus, say > a 20 bit bus, do I just have to change it in the generic map for the > data_width and the synthesis tool will infer and create two 4K block > RAMs (in case of spartan II devices) and then cascade them to obtain > the given data width? I assume you mean parallel them. The answer is yes. Have fun, MarcArticle: 110758
Hi to every one, I'm sorry for the cross-post but I need information from both ng. I have problems with my server because is archiving every month more or less and I cannot access older posts through my mailer. I know google-groups have them all but I would have liked to read not on the web-browser. I found some free servers which keep some months of posts, is there anyone who knows some others which give better access? Thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110759
I have started a page on our website to encompass some the answers on this thread for this first time FPGA build. I'm sure the page is missing lots of things so do suggest anything I should add. Page is in out TechiTips section here http://www.enterpoint.co.uk/techitips/techitips_build_first_fpga.html. John Adair Enterpoint Ltd. John Adair wrote: > The most likely problem provided you have set up period constraints > correctly is probably not dealing with what are esssentially > asynchronous inputs properly. The timing out your keyboard is unlikely > to bear much relationship to your internal clock. Also keyboards tend > have open collector/drain driving which makes edges fairly slow and > makes timing even more variable. Your design needs to account for > those ensuring the data capture point you use is stable. > > Other things to check are (1) That you do have a pullup on the lines in > both cases, either phyiscal resistor or FPGA internal, and finally the > value of those pullups in discrete components. (2) Check your keyboard > does not need 5V CMOS levels. Occasionally they do and get upset by > 3.3V driving or limiting by protection diodes on the FPGA. Small > variations in the 3.3V supply might make one board work and the other > not if it is the margin levels zone. > > John Adair > Enterpoint Ltd. - Home of Tarfessock1. The Student Development Board > > shadfc wrote: > > Hey everyone, I'm fairly new to VHDL and especially to synthesizing > > code to program an FPGA. For a class project, I developed a FSM that > > received its inputs from a ps/2 keyboard. So this project has a > > keyboard controller (host-receive only), a component to translate the > > scan-codes into appropriate actions, the FSM being controlled by those > > actions, and a BCD converter which is to be mapped to a 7 segment > > display. > > > > Anyway, I've got to the point where my code simulates perfectly, but > > when testing on different FPGA boards, I get mixed results. I recently > > purchased a Xilinx Spartan-3E Starter Kit with a 500k gate chip. When > > I program my project into this board, it does nothing but go to the > > default state. None of the keys that are supposed to be recognized > > are. We also have a board that our professor loaned to us which is a > > Xilinx Spartan-3 with a 200k gate chip. On this one, the code > > functions pretty well and the keys are recognized. > > > > My (long winded) question is, is this normal? Should code that > > simulates and synthesizes fine work on one FPGA and not at all on > > another? > > > > thanks > > JayArticle: 110760
Eric Crabill schrieb: > Hello, > > I am fairly certain the main reason for the "requirement" is because Xilinx > IP Solutions has a validation platform with all eight lanes on one side of > the FPGA. Xilinx guarantees what is listed in the datasheet, and it's > prudent (as you can imagine) for Xilinx invest significant time in testing > complex IP cores such as this one. Nope. The datasheet contains no information on placement at all. There is an answer record that adds restrictions on the placement of the rocket IO, the clock input, and the location of the DCM used. Heaven knows why the datasheet is not updated once an answer record like that is created. Kolja SulimmaArticle: 110761
fpga_toys@yahoo.com wrote: > Ben Pfaff wrote: > > Look at Intel's latest Optimization Guide for its CPUs. It will > > tell you. > > Certainly look at the current Itanium products too. The more > interesting question for some time, with multi-issue architectures, is > how MANY add's can you do in a clock cycle :) Hi fpga, I really have looked at the latest CPU products software programming manual and found no column of number of clocks is specified for any kind of instructions, a big difference from 386, 486 and maybe Pentium manuals. Launching multiple integer instruction per clock may be the reason why there is no such specification in manual. So I can ask such a different and similar question: On average, how many integer instructions per clock can the latest Intel CPU run? For example, for a 4GHz CPU, can it run 24G integer instructions if, on average, 6 instructions can be launched per clock? Thank you. WengArticle: 110762
Is it possible to get the ISE 8.2i text editor to use CRLF for line endings on a Windows system? It seems to use LF only, and I can't find an editor option to control it. Their LF convention is causing complications for me because I use source code control (CVS) for my VHDL files. Thanks, EdArticle: 110763
"Weng Tianxiang" <wtxwtx@gmail.com> writes: > fpga_toys@yahoo.com wrote: >> Ben Pfaff wrote: >> > Look at Intel's latest Optimization Guide for its CPUs. It will >> > tell you. >> >> Certainly look at the current Itanium products too. The more >> interesting question for some time, with multi-issue architectures, is >> how MANY add's can you do in a clock cycle :) > > I really have looked at the latest CPU products software programming > manual and found no column of number of clocks is specified for any > kind of instructions, a big difference from 386, 486 and maybe Pentium > manuals. Launching multiple integer instruction per clock may be the > reason why there is no such specification in manual. It is clear that you have *not* looked at the Intel Optimization Reference Manuals, because those *do* specify clock cycles. -- Ben Pfaff email: blp@cs.stanford.edu web: http://benpfaff.orgArticle: 110764
EdJ wrote: > Is it possible to get the ISE 8.2i text editor to use CRLF for line endings > on a Windows system? It seems to use LF only, and I can't find an editor > option to control it. Their LF convention is causing complications for me > because I use source code control (CVS) for my VHDL files. > Well, at the risk of sounding annoying by not answering the question... why not just use your favorite text editor, rather than the one built into ISE? ISE will still correctly recognize when the source files have changed when you save them.Article: 110765
Duane Clark wrote: > EdJ wrote: > >> Is it possible to get the ISE 8.2i text editor to use CRLF for line >> endings on a Windows system? It seems to use LF only, and I can't >> find an editor option to control it. Their LF convention is causing >> complications for me because I use source code control (CVS) for my >> VHDL files. >> > > Well, at the risk of sounding annoying by not answering the question... > why not just use your favorite text editor, rather than the one built > into ISE? ISE will still correctly recognize when the source files have > changed when you save them. Another very simple option is to use DOS2UNIX / UNIX2DOS and post process the file. Apart from that, what complication does it cause? I've written boatloads of code under *nix and every text editor there uses LF (not CR-LF) and I never had any issues with CVS storing those files. Cheers PeteSArticle: 110766
Hello, I've recently acquired a Spartan-3E Starter Kit (RevD) and am new to the world of FPGAs and logic design. I've been experimenting with EDK trying to get a test design working on my board when I ran into a problem. I can use the wizard to create a simple MicroBlaze design with a small amount of cache and a DDR SDRAM memory controller that builds and downloads to the device without a problem. However, when I attempt to run the either the memory or peripheral test applications, built in the TestApp_(name) folders, the debugger reports a pipeline stall. The memory testapp reports the stall when the PC is at 0x000004bc. I investigated the contents of this address and its the LWI opcode. The peripheral test stalls at 0x22000000, which contains a zero. Pastebin link to memory test: http://pastebin.com/810943 My question is: should I be concerned at all that my wizard-create microblaze configuration isn't working? I have a feeling its not a drop-in and go type of deal, and I need to modify the HDL, but the fact that everything worked fine until the design actually ran real software has me a bit paranoid that perhaps my board is defective somehow. I am really just looking for something that would let me test out the board's capabilities, so if anyone wants to point me in the right direction it would be much appreciated.Article: 110767
Ben Pfaff wrote: > "Weng Tianxiang" <wtxwtx@gmail.com> writes: > > > fpga_toys@yahoo.com wrote: > >> Ben Pfaff wrote: > >> > Look at Intel's latest Optimization Guide for its CPUs. It will > >> > tell you. > >> > >> Certainly look at the current Itanium products too. The more > >> interesting question for some time, with multi-issue architectures, is > >> how MANY add's can you do in a clock cycle :) > > > > I really have looked at the latest CPU products software programming > > manual and found no column of number of clocks is specified for any > > kind of instructions, a big difference from 386, 486 and maybe Pentium > > manuals. Launching multiple integer instruction per clock may be the > > reason why there is no such specification in manual. > > It is clear that you have *not* looked at the Intel Optimization > Reference Manuals, because those *do* specify clock cycles. > -- > Ben Pfaff > email: blp@cs.stanford.edu > web: http://benpfaff.org Hi Ben, Thank you. I will have a look at the Intel Optimization Reference Manuals. I have looked at Intel Software Programming Manual. WengArticle: 110768
jrbattin@gmail.com wrote: > Hello, > > I've recently acquired a Spartan-3E Starter Kit (RevD) and am new to > the world of FPGAs and logic design. I've been experimenting with EDK > trying to get a test design working on my board when I ran into a > problem. I can use the wizard to create a simple MicroBlaze design > with a small amount of cache and a DDR SDRAM memory controller that > builds and downloads to the device without a problem. > > However, when I attempt to run the either the memory or peripheral test > applications, built in the TestApp_(name) folders, the debugger > reports a pipeline stall. The memory testapp reports the stall when > the PC is at 0x000004bc. I investigated the contents of this address > and its the LWI opcode. The peripheral test stalls at 0x22000000, > which contains a zero. get some working reference design and proceed from there the wizard generated systems dont always work you find some designs at xilinx website and www.petalogix.com has an uclinux ready MB system design for the se3sk board Antti http://groups.google.com/group/virtex5Article: 110769
Kolja Sulimma wrote: > Eric Crabill schrieb: > > Hello, > > > > I am fairly certain the main reason for the "requirement" is because Xilinx > > IP Solutions has a validation platform with all eight lanes on one side of > > the FPGA. Xilinx guarantees what is listed in the datasheet, and it's > > prudent (as you can imagine) for Xilinx invest significant time in testing > > complex IP cores such as this one. > > Nope. The datasheet contains no information on placement at all. > There is an answer record that adds restrictions on the placement of the > rocket IO, the clock input, and the location of the DCM used. > Heaven knows why the datasheet is not updated once an answer record like > that is created. > > Kolja Sulimma Kolja you arent born yesterday - so you should have figured out by now that NO ONE at Xilinx could possible think that anyone would be designing an PCIe 8 lane design without having Xilinx FAE holding his hand. There are many many things 'to know' that are somewhere but almost impossible to find. The MGT channels bonding is defenetly one of the most complicated things to get ever right so I am not wondering at all that all information that is there about the channel bonding constraints isnt there in the main datasheet. I have given up any assumptions what one may think is possible - whenever you have a design you must run it through the toolchain and see if it passes with no warnings - any attempts to get pin assignemnets and other simple things done correct by reading the datasheets - NO WAY. You may get lucky a few times, but one day you desing some thing by only datasheet info that defenetly want work because some strange constraints. in V4FX12 no IOB in right half of the die can reach any DCM input legally - there is no route! is that in datasheet? If you havent made commitments to buy PCIe IP core maybe you can retarget V5LXT - the 8 lane board ML558 is real, you should possible get even the schematics from your FAE, so it would be safe path, well of course it depends on your target deadlines. I bet Xilinx is interested to have more real V-5 based products out as fast as posssible to have more 'showcase' for the leading edge technology, so talk to them directly, maybe the V5LXT solution can be arranged in your timeframe Antti http://groups.google.com/group/virtex5Article: 110770
Hi,
I am learning a simple 16 bits adder using VHDL:
begin
a1: process (CLK)
variable count_a, count_b : std_logic_vector(15 downto 0);
begin
if (CLK'event and CLK = '1') then
count_a := A;
count_b := B;
CLK <= CLK;
Q <= count_a + count_b;
end if;
end process;
In the synthesis report, I can see that it uses 16 LUT2, 15 MUXCY and
15 XORCY. But I cannot find the XORCY on the .ngc file. Where are the
XORCY? They just function as route?
Thank you very much.
Article: 110771fl wrote: > In the synthesis report, I can see that it uses 16 LUT2, 15 MUXCY and > 15 XORCY. But I cannot find the XORCY on the .ngc file. Where are the > XORCY? They just function as route? LUT2, MUXCY and XORCY are inside the slice. Using fpga_editor, double click on one of the used slices. Each slice contains two LUT2, two MUXCY and two XORCY. MUXCY is part of the carry chain and is on the centerline of the diagram. XORCY is drawn as an XOR gate, so you should be able to find it. The MUXCY are named CYMUXF and CYMUXG. The XORCY are named XORF and XORG. Alan NishiokaArticle: 110772
On Wed, 18 Oct 2006 16:33:31 GMT, samiam <samiamSPAMTHIS@spamalert.com> wrote: >Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) > >Whats the cheapest board to study VHDL on? > >Ideally Id like an FPGA based board with a few inputs (dip >switches,toggles?), some outputs (parallel or serial connector, some >leds) < $100 > >I am looking on ebay now, and I see one or two boards well above $100. >Any suggestions? > >Thanks in advance You may also want to check out a very extensive list of boards at: http://www.fpga-faq.org/FPGA_Boards.shtml =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 110773
On Sat, 21 Oct 2006 14:38:05 +0200, Al <alessandro.basili@cern.ch> wrote: >Hi to every one, >I'm sorry for the cross-post but I need information from both ng. >I have problems with my server because is archiving every month more or >less and I cannot access older posts through my mailer. >I know google-groups have them all but I would have liked to read not on >the web-browser. > >I found some free servers which keep some months of posts, is there >anyone who knows some others which give better access? >Thanks a lot > >Al The archive at: http://www.fpga-faq.org/archives/index.html has every post ever made to comp.arch.fpga , and it is free. (it requires web-browser access which you didn't want) It includes theading by author, topic, and date. Both Google and Yahoo searches are available, and currently Yahoo does a much better job. Since I only update it once a month, it does not carry the most recent posts. =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 110774
i agree, i started using planahead a few months ago and it's pretty user-friendly and handy tool to get timing closure ... Joseph Samson wrote: > marc_ely wrote: >> I would really like to fix down some of the blocks to stop the Xilinx >> tool re-placing etc. > <snip> >> >> At first glance there seems to be many options in the Xilinx tools to >> do this, but I can't get any of them to work properly. >> So far I have tried the following: > <snip> >> - Planahead. Beta, poor doc's, didn't know where to start really. >> Even my FAE doesn't have a scooby-doo about this one. > > I have to come to the defense of PlanAhead here. Although I don't use it > as part of an incremental flow, I do use it to improve timing, and I > found it surprisingly easy to use. I watched the video-on-demand demo, > scanned the documentation then started floorplanning. In most cases I've > found it sufficient to just assign area groups to modules, but it's not > hard to lock the placement (but not routing) of logic elements within > the module. > > --- > Joe Samson > Pixel Velocity
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