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Zorjak napsal(a):
> Ray Andraka wrote:
>> Zorjak wrote:
>>> Ray Andraka wrote:
>>>
>>>> Zorjak wrote:
>>>>
>>>>
>>>>> Hi.
>>>>> I am trying to write generic VHDL code for FIR filter. generic
>>>>> parametars should be word_length, filter_order. Can anybody help me
>>>>> how to input filter coeficients. I tought something like, read
>>>>> coeficitients from file and write it in some LUT table. Could it be
>>>>> done (or something similar)?
>>>>>
>>>>> Thanks for help
>>>>>
>>>> If it is synthesizable code, it can't go and read files. What you can
>>>> do though is have a helper function that converts your coefficient file
>>>> into a VHDL package containing the coefficient constants. Write that
>>>> package to a file, and then include that file with the rest of the
>>>> design when you compile the design. The helper function can be
>>>> non-synthesizable VHDL, C, Matlab or any other programming language you
>>>> feel like using. Alternatively, you can cut and paste your coefficients
>>>> into a VHDL package or directly into a constant array in your code.
>>>>
>>>> You can also pass the coefficients into the entity through a generic by
>>>> defining an integer_array type in a top level package, referring to that
>>>> package in the library declarations, and then putting the int_array in
>>>> the generics like this:
>>>>
>>>> component matrix
>>>> generic(
>>>> coefs: int_array:= (
>>>> -62465, -8923, 24026, 39814, 41873, 33635, 18534,
>>>> 0,-18534,-33636,-41873,-39813,-24025, 8925, 62468,
>>>> 48188, 27536, 10061));
>>>> port(
>>>> clk : in std_logic;
>>>>
>>>> Leaving the integer array unconstrained allows you to put in an
>>>> arbitrary number of coefficients (must be more than 1).
>>>
>>> Thanks for your answer Ray
>>>
>>> I am using Altera Quartus|| software and I've seen there thet some
>>> *.mif files are using for ram initialization so I thought could I do
>>> something similar with my FIR filter. Can you help me with that helper
>>> function if it isnt to much that I am asking. I am VHDL beginer and I
>>> am not very familiar with it so any lkind of help would used me.
>>>
>>> If is to much that I asking, sory.
>>> Thanks again
>>>
>> The *.MIF files are tie-ins to the altera tools, and have nothing to do
>> with the VHDL. You don't have the hooks you need to get inside the
>> place and route tools to bring in your own custom initialization.
>>
>> The helper program I talked about just has to write out a text file
>> containing a VHDL package. The package contains a constant containing
>> your coefficients.
>
> I think I understand you. I'll try to do that
>
> Thanks again, Ray
>
You can use e.g. std.textio.all package. The coeffs can be stored in the
regular text file. In case std.textio.all the content of the file is
binary string like
-- file.dat
0010000
0010001
...
--
(there is also possibility to use hex representation but different
package has to be used - from IEEE....)
Then just define ROM (distributed or block RAM) by array statement. E. g.
TYPE ROM IS ARRAY (N_COEFF - 1 DOWNTO 0) OF SIGNED(N_BITS - 1 DOWNTO 0);
Define function "init_function" to be able read data from file by means
of "readline" and "read" statement from textio package.
And finally initiate e. g. constant of coeffs.
CONSTANT coeff : ROM := init_function("file.dat");
It works in XST. I don't have any experience with Quartus. Check in the
Quartus documentation how is possible define initial value of registers
an memories.
Article: 110951Antti wrote: > Dave Pollum schrieb: > >> ---------- >> Is an 8-bit soft-core CPU (e.g. picobalze(tm)), too big for your task? >> Is even a 4-bit CPU too much? Well at Fly-by-Night Enterprises, we >> have the perfect solution - the 2-bit FemtoFire CPU! If you've ever >> wanted a real 2-bit processor from a 2-bit company, now is the time to >> get one. And if you place your order in the next 2 minutes, you can >> get the FemtoFire for only 2-bits (0.25USD)! What a deal! If you need >> a high-end soft-core, we offer the MaxiFire 33-1/3 bit CPU. With some >> tweaking of the design, you can even create a 78-bit CPU. Accessing >> the MaxiFire's serial bus is via a magnetic transducer (found at any >> electronics surplus center). All of our soft-cores are offered in our >> poprietary FbNHDL, which in keeping with Fly-by-Night's philosophy, is >> not compatible with _any_ existing HDL. Both the source code and >> compiler are free, but there is a small download fee (*). Payment can >> be made with either PayMeBuddy or gold-pressed latinum. >> (* - 0.25USD per byte) >> ------------- >> This is what happens when I have a bad cold and cabin fever! >> I hope you enjoyed it. My apologies to PayPal(tm)! >> -Dave Pollum > > I had cold recently too. > But I am serious about designing and soft-core that uses 0 slices, 0 > luts and 0 FF's :) > > Antti > PS I an I almost had some experiene with 2 bit processors, > dont recall the part type any more but I had some of them > in my hands. Well didnt ever make a PCB for them. Was > some funky military 2 bit wide bit-slice thing. > To split the difference, you could use Motorola's 14500 1-bit CPU. Yes, this is/was a real product!Article: 110952
Mike Treseler wrote: > Weng Tianxiang wrote: > > > It is still problem !!! > > > ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136) > > Unknown identifier "read_mode". > > > What can I do to resolve the problem? > > Maybe you have an old version of modelsim? > Upgrade or read the manual. > > -- Mike Treseler > > Rebuilding Supplied Libraries > Resource libraries are supplied precompiled in the modeltech > installation directory. If you need > to rebuild these libraries, the sources are provided in the vhdl_src > directory; a macro file is also > provided for Windows platforms (rebldlibs.do). To rebuild the > libraries, invoke the DO file > from within ModelSim with this command: > do rbldlibs.do > Make sure your current directory is the modeltech install directory > before you run this file. > Note > Because accelerated subprograms require attributes that are > available only under the 1993 > standard, many of the libraries are built using vcom with the > -93 option. > Shell scripts are provided for UNIX (rebuild_libs.csh and > rebuild_libs.sh). To rebuild the > libraries, execute one of the rebuild_libs scripts while in the > modeltech directory. Hi Mike and KJ, Thank you for your help. I resolved the problem with a surprise method. The method KJ suggested is 95% right, but I failed at the last step. I copied textio.vhd into my project, compiled it and project still was wrong. My son helped me. He tried and was successful. What is the difference between my and his procedures? I compiled textio.vhd file and compiled all files by clicked icons in manu: 'compile' and 'compile all'. He compild textio.vhd using compile/compile-selected manus. I don't understand two things: 1. Why textio.vhd suddenly does not work after it had worked for 3 months? 2. Why clicking compile/compile-selected manus works but clicking icon doesn't? ModelSim really is a great software that makes everybody guess and confusing !!! WengArticle: 110953
David R Brooks wrote: > David Ashley wrote: > >> gen_vlsi wrote: >> >>> Hi, >>> >>> Can anyone suggest a good stream cipher algorithm for hardware >>> implementation. >>> >> >> I'd think AES would be a good choice. >> > But AES is a block cipher, not a stream cipher. Yes, it can be used in a > stream mode, but something else might be better. > Questions to the OP: > What level of security do you need (ie how well resourced & patient is > your adversary)? > How much hardware resources can you devote to this function? > How fast must it run? AES is a stream cipher -- every character is just 128 bits. :) -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 110954
Peter Alfke wrote: > > The person(s) in charge of documentation must be technically savvy in a > wide area, be able to write clear and reasonably tight English > sentences, have the eyes of an eagle, and the patience of Job. They > must be self-confident and persistent without becoming obnoxious, and > it helps when they have a respected and senior position in the company, > so that they can circumnavigate committees and get things implemented > or changed. And, IME, be willing to work for 1/2 to 1/3 of an engineer's salary. I am amazed at how little tech writers get paid. > No wonder we do not always live up to the highest expectations. But we > are still trying... > Peter Alfke, Xilinx, from homeArticle: 110955
Jiri Plasil wrote:
> Zorjak napsal(a):
>
>> Ray Andraka wrote:
>>
>>> Zorjak wrote:
>>>
>>>> Ray Andraka wrote:
>>>>
>>>>> Zorjak wrote:
>>>>>
>>>>>
>>>>>> Hi.
>>>>>> I am trying to write generic VHDL code for FIR filter. generic
>>>>>> parametars should be word_length, filter_order. Can anybody help me
>>>>>> how to input filter coeficients. I tought something like, read
>>>>>> coeficitients from file and write it in some LUT table. Could it be
>>>>>> done (or something similar)?
>>>>>>
>>>>>> Thanks for help
>>>>>>
>>>>> If it is synthesizable code, it can't go and read files. What you can
>>>>> do though is have a helper function that converts your coefficient
>>>>> file
>>>>> into a VHDL package containing the coefficient constants. Write that
>>>>> package to a file, and then include that file with the rest of the
>>>>> design when you compile the design. The helper function can be
>>>>> non-synthesizable VHDL, C, Matlab or any other programming language
>>>>> you
>>>>> feel like using. Alternatively, you can cut and paste your
>>>>> coefficients
>>>>> into a VHDL package or directly into a constant array in your code.
>>>>>
>>>>> You can also pass the coefficients into the entity through a
>>>>> generic by
>>>>> defining an integer_array type in a top level package, referring to
>>>>> that
>>>>> package in the library declarations, and then putting the int_array in
>>>>> the generics like this:
>>>>>
>>>>> component matrix
>>>>> generic(
>>>>> coefs: int_array:= (
>>>>> -62465, -8923, 24026, 39814, 41873, 33635, 18534,
>>>>> 0,-18534,-33636,-41873,-39813,-24025, 8925, 62468,
>>>>> 48188, 27536, 10061));
>>>>> port(
>>>>> clk : in std_logic;
>>>>>
>>>>> Leaving the integer array unconstrained allows you to put in an
>>>>> arbitrary number of coefficients (must be more than 1).
>>>>
>>>>
>>>> Thanks for your answer Ray
>>>>
>>>> I am using Altera Quartus|| software and I've seen there thet some
>>>> *.mif files are using for ram initialization so I thought could I do
>>>> something similar with my FIR filter. Can you help me with that helper
>>>> function if it isnt to much that I am asking. I am VHDL beginer and I
>>>> am not very familiar with it so any lkind of help would used me.
>>>>
>>>> If is to much that I asking, sory.
>>>> Thanks again
>>>>
>>> The *.MIF files are tie-ins to the altera tools, and have nothing to do
>>> with the VHDL. You don't have the hooks you need to get inside the
>>> place and route tools to bring in your own custom initialization.
>>>
>>> The helper program I talked about just has to write out a text file
>>> containing a VHDL package. The package contains a constant containing
>>> your coefficients.
>>
>>
>> I think I understand you. I'll try to do that
>>
>> Thanks again, Ray
>>
> You can use e.g. std.textio.all package. The coeffs can be stored in the
> regular text file. In case std.textio.all the content of the file is
> binary string like
>
> -- file.dat
> 0010000
> 0010001
> ...
>
> --
>
> (there is also possibility to use hex representation but different
> package has to be used - from IEEE....)
>
> Then just define ROM (distributed or block RAM) by array statement. E. g.
> TYPE ROM IS ARRAY (N_COEFF - 1 DOWNTO 0) OF SIGNED(N_BITS - 1 DOWNTO 0);
>
> Define function "init_function" to be able read data from file by means
> of "readline" and "read" statement from textio package.
>
> And finally initiate e. g. constant of coeffs.
> CONSTANT coeff : ROM := init_function("file.dat");
>
> It works in XST. I don't have any experience with Quartus. Check in the
> Quartus documentation how is possible define initial value of registers
> an memories.
It may work in some tools, but it isn't standard. Generally speaking
file i/o is not currently allowed in synthesizable code. It is allowed
in behavioral code (e.g. testbenches) that is not intended to be
synthesized, but I wasn't aware that any synthesizers supported file
i/o. I've asked for years for support of file i/o and reals for
filling constants. I think some are supporting reals in functions for
generating constants now.
Article: 110956My windows install is working fine but I have problem with the linux install. I have repeated the same steps as I did with windows machine. I have installed the following updates in the order listed. 8_2_03i_v5_lx_patch.zip 8_2_03i_v5_lx330_lxt.zip ise_82i_ip_update2_lxt_sup.zip On linux install, ISE does not give me the option to select any of the LXT parts. However when I run coregen, it's allowing me to select LXT parts. Any Idea what I shoud look for? Sovan. Antti wrote: > silently - but its really available for downloads. > > first you read 5 different answer records, then download 5 > different updates, but then ISE should be patched to support > V5LXT designs! > > AnttiArticle: 110957
Nope won't work. I talked to Lattice today. There is no internal osc to use, and they did not recommend using a bunch of gates. Moreover there is no extra flash space either - zip. This is not the first time. Overall I am very disappointed with what they put out in their MachXO and XP NV families. They lack a lot of little features that would make them so much more powerful. I guess they have heard that from others too, he told me that they were coming out with a 'revised' new XP line next year. XP-II I think he said. Chris.Article: 110958
Antti wrote: > I have to make a quick fix to get OPB_UARTLITE fifo larger > seems like simple thing, just replace the fifo, but xilinx coregen > is not able to create a FIFO with first word fall-through so there > latency on read and data from uart seems like delayed. > > the FIFO has to use BRAM, I was hoping that coregen is easy way > but it doesnt look like. sure its not so complicated to write it from > scratch but its really boring thing todo, there should be some ready > solutions also? > > target device is S3e so I cant use the V4-V5 FIFO16 that has > first word fall-through option > > Antti May be it's not pretty, but i'm using this for quite a while. I'm creating wrapper for the fifo and this component. ------------------------------------------------------------------------------- -- Special entity "auto_first_read" -- provide loading output register with first word, as soon this first word comes to Fifo. It forms additional -- RdEn pulse and take care of proper "Empty" signal. --------------------------------------------------------------------------- LIBRARY ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; ------------------------------ library work; use work.types.all; use work.components.all; --------------------------------------------------------------------------- ENTITY auto_first_read IS port ( RdEn: in std_logic; RdCe,RdClk: in std_logic; Ainit: in std_logic; Empty: in std_logic; RdEnOut: out std_logic; EmptyOut: out std_logic); END auto_first_read; ARCHITECTURE arch OF auto_first_read IS --------------------------------------------------------------------------- signal iNextState : integer; signal iAutoRdEnOut,iStrobRdEnOut,iEmptyOut: std_logic; begin --------------------------------------------------------------------------- -- This process forms "iAutoRdEnOut"- additional pulse to pass data to output pipeline reg -- and "iEmptyOut" - delayed ver of "empty" signal from asyncfifo process (Ainit, RdClk ) begin if (Ainit='1') then iNextState<=0; iAutoRdEnOut<='0'; iStrobRdEnOut<='0'; iEmptyOut<='1'; elsif (RdClk'Event and RdClk='1') then if RdCe='1' then iAutoRdEnOut<='0'; iStrobRdEnOut<='0'; iEmptyOut<='1'; case iNextState is when 0 => -- check was something written if empty='0' then iAutoRdEnOut<='1'; -- this write the word into output pipeline reg iNextState<=iNextState+1; end if; when 1 => -- make auto read of first word iEmptyOut<='0'; -- this shows that fifo is not empty. iStrobRdEnOut<='1'; iNextState<=iNextState+1; when 2 => iEmptyOut<='0'; -- this shows that fifo is not empty. iStrobRdEnOut<='1'; if RdEn='1' and empty='1' then iNextState<=0; -- start over iEmptyOut<='1'; -- this shows that fifo is empty. end if; when others => iNextState<=0; end case; end if; end if; end process; --------------------------------------------------------------------------- RdEnOut <= (iAutoRdEnOut or (iStrobRdEnOut and RdEn)) and RdCe; EmptyOut<=iEmptyOut; --------------------------------------------------------------------------- END arch;Article: 110959
I'm trying to understand the proper way to use the xgpio driver that comes with the MontaVista kernel. The driver includes adapter.c to look for available gpio devices and map them into the memory space, but doesn't seem to make the ioremap'ed addresses available to the user. Consequently, if I XGpio_Initialize() and then XGpio_SetDataDirection() normally, I get a segmentation fault. I wasn't able to find much of anything that addressed this, or that showed me how Xilinx and/or MontaVista intended for it to be used. Can anybody point me in the right direction? (Two comments: 1) The same question applies to any of the Xilinx devices that use the separate adapter.c paradigm. 2) GPIO isn't the specific concern, because I've written a linux driver of my own that does the job just fine, but I'm going to need to extend the concepts to other devices, and am trying to gauge how much to keep and how much to redo from scratch.)Article: 110960
Well, that luckily was not the problem at Xilinx 19 to 10 years ago. We were a small start-up and the company was happy to have a well-paid savvy director/engineer/writer/publisher/rebel, and gave me pretty much carte blanche. The joys of a start-up: Be experienced, don't ask for permission, just work your ass off, and do it ! Ask questions later, or never... Peter Alfke On Oct 25, 5:45 pm, ghel...@lycos.com wrote: > Peter Alfke wrote: > > > The person(s) in charge of documentation must be technically savvy in a > > wide area, be able to write clear and reasonably tight English > > sentences, have the eyes of an eagle, and the patience of Job. They > > must be self-confident and persistent without becoming obnoxious, and > > it helps when they have a respected and senior position in the company, > > so that they can circumnavigate committees and get things implemented > > or changed. And, IME, be willing to work for 1/2 to 1/3 of an engineer's salary. > I am amazed at how little tech writers get paid. > > > No wonder we do not always live up to the highest expectations. But we > > are still trying... > > Peter Alfke, Xilinx, from homeArticle: 110961
David R Brooks wrote: > David Ashley wrote: > > gen_vlsi wrote: > >> Hi, > >> > >> Can anyone suggest a good stream cipher algorithm for hardware > >> implementation. > >> > > > > I'd think AES would be a good choice. > > > But AES is a block cipher, not a stream cipher. Yes, it can be used in a > stream mode, but something else might be better. > Questions to the OP: > What level of security do you need (ie how well resourced & patient is > your adversary)? > How much hardware resources can you devote to this function? > How fast must it run? I don't have any specific requirement yet... Inorder to get an hold on stream cipher..i wanted to do an hardware implementation. so i wanted to know the most used sterm cipher algorithm in hardware.. please pass on ur comments on RC4 ,its applications and present useArticle: 110962
Hi I'm compiling my design using Quartus II and using a Cylclone II EP2C35 device. The fitter reports currently says it's using 34 /70 embedded 9-bit multiplier blocks. I'd like to see how much extra logic it uses if I tell it not to use the embedded multipliers, but I can't seem to turn them off. Under the synthesis settings I can set "maximum DSP block usage" from -1 to 0 but this has no effect. Any tips? Thanks, RichardArticle: 110963
Chris wrote: > I am evaluating using the Altera Cyclone with Quartus SOPC vs. Xilinx > Spartan3E and PicoBlaze. I need a soft core processor and I think PicoBlaze > would be enough. SOPC and Nios-II is very powerful but the learning curve > looks like a potential nightmare to me. In order to use SOPC I might have > to get involved writing custom components to do the job and then one has to > master the Avalon interface. That looks like a lot of potential debugging > time. > > The Xilinx solution seems more direct, and under my control, since PicoBlaze > is stand alone and does not depend on so many bus interrelated components > and SOPC infrastructure. Easier and quicker to write direct interfaces. > Nios seems to need much more of the SOPC (RAM,ROM,Avalon,etc) around it to > work. > > Also, it seems like the Nios/SOPC solution is likely to require far more > gates than a Xilinx/PicoBlaze implementation. > > I would be curious to know any of your experiences with SOPC/Nios-II. I > have very limited R&D time for this project. > > Thanks, Chris. > If you don't need very tight integration between the processor and the FPGA, you might save yourself a great deal of time and effort by using an external small microcontroller. Choose the right part, and things like I2C are a no-brainer.Article: 110964
Dave Pollum schrieb: > And this design has no inputs, outputs, or clocks, either? > -Dave You can't do that with Xilinx. At least in previous version my 0 input design would not run through map because "XC9572XL has not enough input pins available for the design". It was a design for a CPLD that was reserved for future use but had to set an output enable. Here is the code, released under GPL: output <= '1'; E-Mail me for a download link to the testbench.... Kolja SulimmaArticle: 110965
Ray Andraka schrieb: > There are still memories and DSP48's if this is V4, or MULTs if many > other families. You can make a microcoded state machine with just a BRAM. 2 BRAMs give a pretty complete processor. And then there is that PPC405 block. I wonder whether you could turn that into a CPU. Kolja SulimmaArticle: 110966
Assuming that "CLOCK" is your 16 MHz clock, and "pulse" is
your 90nS pulse, then it is no surprise at all that this design
is failing. The problem is you don't have a synchronizer on the
signal "pulse". Depending on how pulsestate is encoded,
multiple flipflops could change in this piece of code at the
indicated line
> when IDLE =>
> stretched <= '0';
> if (pulse = '1') then
> nextstate <= PAUSE; <<<<<<<<<<< here's where crap happens
> end if;
You must synchronize "pulse" before you use it in a state
machine to affect state changes.
Your problem is almost certainly not metastability (it is a race
condition between multiple conditional paths), but the solution
is the same as if it was a metastability issue.
Add something that looks like this:
signal pulse_sync_1 : std_logic;
signal pulse_sync_2 : std_logic;
process(CLOCK, RESET)
begin
if(RESET = '1') then
pulse_sync_1 <= '0';
pulse_sync_2 <= '0';
elsif(CLOCK'event and CLOCK = '1') then
pulse_sync_1 <= pulse;
pulse_sync_2 <= pulse_sync_1;
end if;
end process;
and use pulse_sync_2 rather than pulse in your state machine.
This will add 2 cycles of latency, but it will solve your problem.
To learn more about metastability and synchronizers, start reading here:
http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm
and look at the section "Multi-Stage Synchronizer" at:
http://www.interfacebus.com/Design_MetaStable.html
( the dual FF circuit matches my code example above)
Philip Freidin
On 25 Oct 2006 15:02:09 -0700, ghelbig@lycos.com wrote:
>Thanks for the inputs so far! Here's the code that's giving me greif:
>
>architecture inside of stepmachine is
>
> type pulsestate is (IDLE, PAUSE, OUT1, OUT2, OUT3);
> signal currentstate, nextstate : pulsestate;
>
> signal stretched : std_logic;
>
>begin
>
> process(CLOCK, RESET)
> begin
> if(RESET = '1') then
> currentstate <= IDLE;
> elsif(CLOCK'event and CLOCK = '1') then
> currentstate <= nextstate;
> end if;
> end process;
>
> process(currentstate, pulse)
> begin
>
> case currentstate is
>
> when IDLE =>
> stretched <= '0';
> if (pulse = '1') then
> nextstate <= PAUSE;
> end if;
>
> when PAUSE =>
> stretched <= '0';
> nextstate <= OUT1;
>
> when OUT1 =>
> stretched <= '1';
> nextstate <= OUT2;
>
> when OUT2 =>
> stretched <= '1';
> nextstate <= OUT3;
>
> when OUT3 =>
> stretched <= '1';
> nextstate <= IDLE;
>
> when others =>
> stretched <= '0';
> nextstate <= IDLE;
>
> end case;
> end process;
===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG
Article: 110967On 25 Oct 2006 12:53:11 -0700, "Marlboro" <ccon67@netscape.net> wrote: >It happens in a Virtex-E > >There's a 1M cycles test pattern on a 10 bit data bus with an ENABLE >signal (high for 1 M cycles) indicates data valid. The pattern is >clocked at 40 MHZ (0_degree) > >The data & enable is then fed into an accumulator with input >registered. The ACC does the sum for exact 1M cycles. The ACC and its >input register is clocked with the 90 degree phase shift > >The 0_degree and 90_degree clocks are DLL outputs (please dont ask why >it has to cross to the 90 degree). DLL has been locked long time >before ACC start (enbale high) > >PAR post timing well passes the 40 MHz constraint > >Here's what happens > >The accumulator once a while (about 1 out of 100) gives a random wrong >result. If I put another 90 degree clocked register before the ACC, >it fixes the problem. it seems not the setup time violation since 25/4 >= 6.25ns is much longer than the requirement Your data is only valid for 6.25 ns before the accumulation result is added to the register. You need a 160 MHz constraint for this, not 40 MHz. Your problem is almost certainly a setup problem! The aditional register proves it. =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 110968
leevv schrieb:
> May be it's not pretty, but i'm using this for quite a while.
> I'm creating wrapper for the fifo and this component.
>
{code snipped}
looks like exactly what I needed, tried last night the same but failed
with first attempt
sposiba ogromnoje!
Antti
PS I wonder how many xilinx users have made or have needed this
auto_read_first
FIFO fix? really simple thing, but not available with coregen
Article: 110969sovan schrieb: > My windows install is working fine but I have problem with the linux > install. I have repeated the same steps as I did with windows machine. > I have installed the following updates in the order listed. > > 8_2_03i_v5_lx_patch.zip > 8_2_03i_v5_lx330_lxt.zip > ise_82i_ip_update2_lxt_sup.zip > > On linux install, ISE does not give me the option to select any of the > LXT parts. However when I run coregen, it's allowing me to select LXT > parts. Any Idea what I shoud look for? > > Sovan. sorry, no. it all works on windows. linux-64 is recommended for LX330, initially it was said that LX330 is ONLY supported on linux-64 with 8GB RAM, but now its says recommended, so I guess LX330 might work on other platforms as well if you have time to spare. AnttiArticle: 110970
Your name wrote: > Hi there, > > I've recently installed the Xilinx ISE toolset so that I can play with the > Memory Interface Generator. I followed the readme and installed ISE 8.1i, > 8.1i_SP3 and then MIG 1.6. When I open CORE Generator and select MIG from > the drop down list nothing happens. I get the "Customise" and "View Data > Sheet" links but when I click on them nothing happens. > > Is there another download that I've missed or is the Xilinx software just > flaky? I've found that MiG 1.6 only supports Virtex5. It does support the other families internally (i.e., you can create cores for those families), but if your CoreGen-project is set to something other than V5, MiG won't start up because some GUI-setting suggests MiG is only compatible with V5. I had to start up MiG manually from the installation directory: %XILINX%\coregen\ip\xilinx\other\com\xilinx\ip\mig_v1_6\bin\nt contains batch-scripts to start it up. You might have to create a new one that sets the project to your specific part. cu, SeanArticle: 110971
Hello
I am fairly new to this FPGA game, and well am having a few teething
problems with my code. I am using an Actel ProAsic Plus Evaluation
board.
I am trying to clock in a single bit stream (called compout) at 8MHz
(clock on global clock line), and then put the bit stream through a
comb decimation filter to eventually get it to 8 bit, 125kHz data.
However, at the integrator stage of the code (which is at 8MHz), I get
jumps in the output (combacc, read out using a DAQ card on the falling
edge of the 8MHz clock), because I am only adding or subtracting 1 in
this integrator, it is a clocked process, and relatively slow (at 8MHz)
I am at a bit of a loss as to what could be causing jumps of 2, 4 and
sometimes 50 or 60 - not all power of 2) in combacc. combacc is a
signed, 8 bit signal, which I transfer into a std_logic_vector to be
read out.
process (Clk8MHz) is
begin
if rising_edge(Clk8MHz) then
feedbackbit<=compout;
if compout ='1' then
combacc1<=combacc1 + 1;
else
combacc1<=combacc1 - 1;
end if;
end if;
end process;
Interestingly, if I remove the else clause from the process (so 1 is
added if compout is 1, but nothing happens if compout is 0) then I
don't get the jump problem - but this causes problems for me further
down the line, so I would really like to be able to add or subtract 1
at this stage!
I don't get the problem when I use the simulator on the code
(pre-synthesis), and the timing analysis tells me (i think) that the
addition/subtraction only takes 30nS (much less than 1/2 an 8MHz clock
period of 62nS), so I don't think it can be a timing problem?
Any ideas would be gratefully received,
Cheers
Helen
Article: 110972On Fri, 20 Oct 2006 16:20:04 +0200, Zara <me_zara@dea.spamcon.org> wrote: >On Thu, 19 Oct 2006 10:46:24 +0200, Zara <me_zara@dea.spamcon.org> >wrote: > >>On Thu, 19 Oct 2006 10:33:07 +0200, Zara <me_zara@dea.spamcon.org> >>wrote: >> >>>On Thu, 19 Oct 2006 09:50:03 +0200, Zara <me_zara@dea.spamcon.org> >>>wrote: >>> >>>>This is not strictly a call for help, it is more of a warning to >>>>everyone. >>><...> >>> > >Continuing with the tale (please forgive me if I strip all the >contents from previous messages): > >Now I do have a double Xilinx installation (8.1 and 8.2), with 8.1 >working perfectly. > >If I communicate with 8.2 XMD to a core created with 8.2, everything >is fine, so there seesm to be no problem with XMD itself (al leats >with ParallelCable III, tests with Platfrom USB are delyed until I >stabilize the design). > >When I upgrade the design (a copy of it, of course) to 8.2, the >following modules are automatically upgraded: OPB, OPB_MDM, LMB, >BRAM_BLOCK, DCM, OPB_INTC. The following are not upgraded: MICROBLAZE, >LMB_BRAM_IF_CNTRL > <...> But the versions remain the same! There must be something really strange happening, because the design in 8.1 uses 83% slices, and only 80% on 8.2 The only apparent changes on the design are the nominal upgrading os the above mentionaed modules (without changing the version number!) and changin the inputs to DCM from SIGIG= DCMCLK to SIGIS=CLK.Revesing such change gives me no benefit at all. I will be trying some more possibilities. Should there be any improvement, I will tell you!Article: 110973
Hi, I have a Microblaze based project that communicates to a 16Bit DAC by means of an SPI interface. I'm using the OPB_SPI interface with a OPB to SPI clock ratio of 16 (the minimum for this property) which works out to be a clock of 3.125 Mhz for a 50Mhz OPB bus. This seems extremely slow considering that the DAC unit can work up to an SPI clock frequency of 30Mhz. Does anyone know why the minimum value for the OPB to SPI clock ratio has to 16 or am I just not configuring it properly.Article: 110974
Hi,
Helen schrieb:
> I am fairly new to this FPGA game, and well am having a few teething
[..]
> I am trying to clock in a single bit stream (called compout) at 8MHz
[..]
> process (Clk8MHz) is
> begin
> if rising_edge(Clk8MHz) then
> feedbackbit<=compout;
> if compout ='1' then
> combacc1<=combacc1 + 1;
> else
> combacc1<=combacc1 - 1;
Am I right, that compout is driven from outside the fpga without having
a register between the input pin and the counter?
Then you have a timing problem as compout may be switching from 0 to 1
or vice versa while calculating combacc1. This will lead to situations
where some of you register think they have to add and some think they
have to subtract at the rising clock edge. This could be easily
overcome by clocking in compout (and any other input) before using it.
if rising_edge(Clk8MHz) then
compout_reg <= compout;
if compout_reg='1' then
.....
would be the simplest sollution. In general it would be better to use
at least a two stage shift register at each asynchronous input either
from outside the fpga or from different clock domains.
bye Thomas
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