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Thanks Austin, I'd like to know what is the tool you're speaking about and if this tool act on vhdl or edif netlist. SalvaArticle: 105026
> Does anyone point me to where i can find document or material or > literature ? we had this topic a few months ago - google this group for "Question about multi write ports RAM in FPGA?" bye, MichaelArticle: 105027
> Just out of curiousity, why don't you want to edit the VHDL file since > apparently 'as it is now' the design is somewhat deficient in that it > doesn't do what you want it to do. The VHDL file is autogenerated, and I feel that editing it with specifics about the precise target board is a hack. To me this should reside in a separate file or be programmable via the GUI.Article: 105028
Subroto Datta wrote: > The Unused Pin Option setting is in: Assignments > Settings->Device->Device & Pin Options->Unused Pins. Thanks Subroto, but like I said: > > > I can find the option in Quartus to assign all unused pins to say > > > "driving low." However I want to keep the default at "driving low" > > > while assigning just this pin to "driving high." It's not the default I'm looking for, but rather a setting for individual pins to ovverride the default. To me it is unreasonable to assume all unsed pins should have the same behaviour. It would make more sense to allow the assignment editor to override the default for a given pin. Thanks for your reply, RichardArticle: 105029
Hi *, I'm having some issues understanding certain limitations regarding differential inputs/outputs: 1. In the "Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30, 2005" in table 1-3 on page 14 it is stated that LC, CC and GC pins do not support LVDS outputs. But obviously, they support other differential outputs like DIFF_SSTL18. At least that's what is stated in the "Virtex-4 User Guide UG070 March21, 2006" in table 6-38 on page 289. Is this correct or are there problems to be expected? The tools at least don't seem to mind. If I put LVDS_25-Outputs on CC/LC/GC-pins, I get ERROR:1107 during par (see Answer record #20092, http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20092), if I use DIFF_SSTL18, the flow finishes without errors. 2. In an earlier Virtex-II Pro-design I had LVDS_25_DT-inputs in a bank powered with VCCO=3.3V that had LVTTL outputs as well. I asked about this here before I did the schematic and was told this was OK, since the LVDS input buffers are not powered by VCCO, but by VCCAUX, which is always 2.5V. So you can put 2.5V-LVDS-inputs with differential termination enabled in any bank without problems. This in fact works, meaning that neither do the tools complain nor are there any problems "in real life" in the hardware; everything works as expected. In Virtex-4 this seems to have changed. According to the user guide (see note (2) for table 6-38 on page 290) LVDS input buffers are still powered by VCCAUX, so you can still have them in banks powered with 3.3V. But it seems you can only use the differential termination when your VCCO is 2.5V: "The VCCO of the I/O bank must be connected to 2.5V ±5% to provide 100? of effective differential termination. DIFF_TERM is only available for inputs and can only be used with a bank voltage of VCCO = 2.5V." (page 282). Why is that and what exactly does it mean? The tools don't seem to mind if you enable DIFF_TERM on banks with LVTTL-IOs, there is no error message or anything. So is the passage in the documentation wrong, or does it mean that if VCCO!=2.5V, you don't get 100R of effective differential termination but a different value? What would that value be? I'd be glad if Austin or someone from Xilinx could clear this up for me... cu, SeanArticle: 105030
> Richard, the fix for you problem is (from memory) to enter the general > settings (assignments?) and change the pin default from "output driving > ground" to "input tristated". That should solve this problem > completely. Spot on! I don't know why I didn't think of doing this. There is obviously an external pull-up resistor on that pin. Thanks a ton Tommy, and thanks to everyone for the help! RichardArticle: 105031
In article <e92di8$dog$1@readme.uio.no>, "Jan Hansen" <someone@microsoft.com> writes: |> Use windows. Thanks for your ... invaluable comments. Got it working meanwhile. RainerArticle: 105032
Hi Salva, Have a look at fishtail (http://www.fishtail-da.com/), not cheap but very powerful. As far as I know they support FPGA tools (ISE/Quartus/Precision/Synplify) although the main market is obviously ASICs. You just give it your RTL files and specify your clock and mode pins and the tool will then automatically create an SDC file listing all the FPs and MCP's found in your design. Hans www.ht-lab.com "pippo" <salvatore.callea@aleniaspazio.it> wrote in message news:1152699926.079795.231420@i42g2000cwa.googlegroups.com... > Thanks Austin, > I'd like to know what is the tool you're speaking about > and if this tool act on vhdl or edif netlist. > Salva >Article: 105033
Hello everyone, I have ISE Foundation 7.1 and I've downloaded a standalone CoreGEN, but they don't give me an option for generating Binary Counter even though I can find a *.vhd file with component c_counter_binary... I have tried to integrate the counter manually, but Synthesiser can't find a library XilinxCoreLib (where this component is)... Help... Thank youArticle: 105034
I think you need to copy the the license files to the dir:\Xilinx\coregen\core_licenses as well for the core to work correctly. At least that's what I did for my downloadable cores to simulate and synthesize correctly. Vivek Vassili wrote: > Hello everyone, > > I have ISE Foundation 7.1 and I've downloaded a standalone CoreGEN, but they don't give me an option for generating Binary Counter even though I can find a *.vhd file with component c_counter_binary... I have tried to integrate the counter manually, but Synthesiser can't find a library XilinxCoreLib (where this component is)... Help... Thank youArticle: 105035
pipo, I was using DC compiler for Verilog (or VHDL, but I was using verilog) from Synopsis. This was for the DCM's DFS "brain" which has a number of clock crossings, and quite a few multi-cycle paths. It was hell until we just figured out how to state all the constraints properly. Multi-cycle paths were the worst, because any general statement seemed like permission to ignore the critical single cycle paths! I am sure this is not unique to DC, as constraining a design during synthesis is probably the hardest step (after creating a design that simulates properly), and once taken, is even harder to verify that it was done properly (especially in a large complex design). Austin pippo wrote: > Thanks Austin, > I'd like to know what is the tool you're speaking about > and if this tool act on vhdl or edif netlist. > Salva >Article: 105036
Sean, I will comment below, Austin -snip- > 1. In the "Virtex-4 Packaging and Pinout Specification UG075 (v2.4) > September 30, 2005" in table 1-3 on page 14 it is stated that LC, CC and > GC pins do not support LVDS outputs. But obviously, they support other > differential outputs like DIFF_SSTL18. At least that's what is stated in > the "Virtex-4 User Guide UG070 March21, 2006" in table 6-38 on page 289. > Is this correct or are there problems to be expected? The tools at least > don't seem to mind. If I put LVDS_25-Outputs on CC/LC/GC-pins, I get > ERROR:1107 during par (see Answer record #20092, > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20092), > if I use DIFF_SSTL18, the flow finishes without errors. Those pins do not have LVDS outputs. This was done to reduce the input capacitance, as these pins can use the extra lower capacitance to improve signal integrity and lower jitter. > 2. In an earlier Virtex-II Pro-design I had LVDS_25_DT-inputs in a bank > powered with VCCO=3.3V that had LVTTL outputs as well. I asked about > this here before I did the schematic and was told this was OK, since the > LVDS input buffers are not powered by VCCO, but by VCCAUX, which is > always 2.5V. So you can put 2.5V-LVDS-inputs with differential > termination enabled in any bank without problems. This in fact works, > meaning that neither do the tools complain nor are there any problems > "in real life" in the hardware; everything works as expected. > > In Virtex-4 this seems to have changed. According to the user guide (see > note (2) for table 6-38 on page 290) LVDS input buffers are still > powered by VCCAUX, so you can still have them in banks powered with > 3.3V. But it seems you can only use the differential termination when > your VCCO is 2.5V: Yes. > "The VCCO of the I/O bank must be connected to 2.5V ±5% to provide 100? > of effective differential termination. DIFF_TERM is only available for > inputs and can only be used with a bank voltage of VCCO = 2.5V." (page 282). Yes. > Why is that and what exactly does it mean? The tools don't seem to mind > if you enable DIFF_TERM on banks with LVTTL-IOs, there is no error > message or anything. So is the passage in the documentation wrong, or > does it mean that if VCCO!=2.5V, you don't get 100R of effective > differential termination but a different value? Yes. What would that value be? Since we don't recommend to use it this way, we have done no characterization, so I can't tell you. It will be terminated, by a resistance, but how much that will vary is unknown.Article: 105037
Which license files? Besides, even standalone CoreGEN does not have a binary counter in the list of it's cores I can only find it in the ISE Foundation files' folder. The funny thing is that folder XilinxCoreLib (it contains the counter) is in the same folder as IEEE but IEEE is recognised as a libray and XilinxCoreLib is not :-(.Article: 105038
Pasacco wrote: > hi > > As a Xilinx dual-port memory (BRAM) user, > > i need to have more :) multiple port memory, for example, 8-read > 4-write port memory. > Some logic should wrap the memory, but i do not have idea how to > implement. > > Does anyone point me to where i can find document or material or > literature ? I can't help with that other than doing a Google search for you. But I will say that one of the things I have learned from studying programming in Forth is that often when a solution is particularly hard, it can be easier to change the problem. It is easy to provide more read ports. You just use more memories with common write ports. As long as the memories have been written with the same data reads from all memories will be equvalent. But the multiple write ports is not so easy. If a 4 port write memory is hard to construct, it is possible to instead use 6 - dual port memories to provide individual point to point comms between the four writers? Do they *really* need to all write to the same memory that everyone else is writing to? Another solution is to share the memory interface the way you would share a bus. But I am sure you have thought of these possibilities. I just thought I would toss them out for reconsideration.Article: 105039
Let's get a difficulty rating from you: how fast do you need to read/write data? Do you ever want to write to the same address with specific port-order priority on who gets the valid write? "Pasacco" <pasacco@gmail.com> wrote in message news:1152699672.483943.261570@m73g2000cwd.googlegroups.com... > hi > > As a Xilinx dual-port memory (BRAM) user, > > i need to have more :) multiple port memory, for example, 8-read > 4-write port memory. > Some logic should wrap the memory, but i do not have idea how to > implement. > > Does anyone point me to where i can find document or material or > literature ? > ThankyouArticle: 105040
Here's my FPGA solution. I have a bitonic sort core for an FPGA. Fill up a large FPGA and it will do 64-bit by 64 rows every clock cycle, pipelined of course. If you had a high-speed connection to the FPGA, you could stream your data through the FPGA and get out sorted sets of 64. You would then run a merge on those on the host processor. It should chop lg(6) off your quick sort or merge sort. > Since you posted on fpga and vhdl newsgroups in addition to programming, are > you interested in an FPGA solution? Most of the information that one *can* > find on the web deals with serial implementations. Parallel implementations > for an FPGA such as the Bitonic sort can speed up the implementation > significantly.Article: 105041
Would you mind indicating how you solved your poblem? I have been having a similar problem at home. Thank you, Nathan Rainer Buchty wrote: > In article <e92di8$dog$1@readme.uio.no>, > "Jan Hansen" <someone@microsoft.com> writes: > |> Use windows. > > Thanks for your ... invaluable comments. > > Got it working meanwhile. > > RainerArticle: 105042
Hello - I am trying to write a custom peripheral using Verilog and version 8.1 of the Xilinx tool kits (ISE and XPS). It is my understanding that only the user_logic component of the peripheral can be developed in Verilog, not sure if that is correct or not. Anyway, I used the XPS create custom peripheral tool to create the skeleton of the peripheral. I was careful to select the option to generate the user_logic stub in Verilog rather than VHDL. At which point I received a dialog box warning that the Verilog stub will be limited capabilities, I went ahead with the Verilog stub. Then, using the ISE, I added the required ports etc to the top level VHDL code and added my Verilog code to the user_logic component. Once I confirmed all of the syntax was correct, I went back to XPS and attempted to import the existing peripheral back into the project. I selected the standard options. I also selectd the 'MIXED' option for the question asking which HDL languages were used to implement the peripheral. I also realized that for some reason the create custom peripherial wizard did not seem to include my user_logic module in the PAO file. So I manually edited the file and added the following line: lib opb_DVIReceiver_v1_00_a user_logic Verilog I was a bit surprised that I had to do this, because in the past, I've created customer peripherals in VHDL and found that the user_logic entry was automatically placed into the PAO file. Anyway, I completed the import custom peripheral wizard and then added the IP to my XPS project. I specified the addresses, and tied in the required ports etc. All SEEMED well. However when I tried to generate the bitstream, I received the following error: ERROR:NgdBuild:604 - logical block 'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type 'user_logic' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'user_logic' is not supported in target 'virtex2p'. I have searched the net for information regarding this error message and found several mentions of it, however none of which seemed to help. There MUST be some information somewhere that explains how to import custome peripherals that make use of a user_logic component written in Verilog, but I have yet to be able to find anything. I would GREATLY appreciate it if someone out there could point me in the right direction. Thanks in advance, JimArticle: 105043
On 12 Jul 2006 08:26:20 -0700, Brannon <brannonking@yahoo.com> wrote: >Here's my FPGA solution. I have a bitonic sort core for an FPGA. Fill >up a large FPGA and it will do 64-bit by 64 rows every clock cycle As a matter of interest, how big is the bitonic sort? I guess I'm really asking "how many 64-bit magnitude comparators do you need", although there's presumably some swap or routing logic also associated with each comparator. (sorry, I'm not familiar with the bitonic sort algorithm - must go look it up). And how many levels of logic? I guess it's best to pipeline it... TIA -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 105044
>Here's my FPGA solution. I have a bitonic sort core for an FPGA. Fill >up a large FPGA and it will do 64-bit by 64 rows every clock cycle, How many I/O pins does that take? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 105045
Vassili wrote: > Hello everyone, > > I have ISE Foundation 7.1 and I've downloaded a standalone CoreGEN, > but they don't give me an option for generating Binary Counter even > though I can find a *.vhd file with component c_counter_binary... I > have tried to integrate the counter manually, but Synthesiser can't > find a library XilinxCoreLib (where this component is)... Help... First a question... why do you want to use CoreGEN to create a binary counter? That is a trivial thing to write in VHDL. Normally, CoreGen embeds the path to the xilinxcorelib components into the cores that it creates, in a way that XST understands. If for some reason you actually wanted to use a XilinxCoreLib component separately (but in general you should not be doing this), you would need to add the library to your ISE project. The XilinxCoreLib components are special, and I am not completely sure this will work, but here is how you normally add libraries to a project. Notice that in the ISE project window named "Sources in Project:", there is a tab at the bottom labelled "Library...". Right click and select "New Source". Select "VHDL Library" and name it xilinxcorelib. Make sure "Add to project" is selected and click on through to create the library. Then right click on the library, select "Add Source", and add the source code for the component. You want to select the *_comp.vhd version of the component, and hopefully XST will figure out that it is a xilinxcorelib component.Article: 105046
Hi Xilinx XCELL (First Quarter 2006) has an articel that says that the VHDL code is available from Micron website http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/p062-063_56-nand.pdf similarly microns TN2905.PDF says also that the VHDL code is available, but all the links at micron website are dead :( anyone fetched the VHDL before the links died? please contact me (if) -- I have success (partial) connecting NAND flash to OPB_EMC without any glue logic, but hence Xilinx XCELL says there is some public NAND related VHDL code available, well wanted to take a look Antti http://antti-brain.comArticle: 105047
> Why is that and what exactly does it mean? The tools don't seem to mind > if you enable DIFF_TERM on banks with LVTTL-IOs, there is no error > message or anything. So is the passage in the documentation wrong, or > does it mean that if VCCO!=2.5V, you don't get 100R of effective > differential termination but a different value? What would that value be? This will be flagged as an error in ADEPT. The tool is freely available at http://home.comcast.net/~jimwu88/tools/adept/ HTH, JimArticle: 105048
On Wed, 12 Jul 2006 16:51:40 +0100, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >As a matter of interest, how big is the bitonic sort? I guess I'm >really asking "how many 64-bit magnitude comparators do you need", >although there's presumably some swap or routing logic also >associated with each comparator. (sorry, I'm not familiar with >the bitonic sort algorithm - must go look it up). And how many >levels of logic? I guess it's best to pipeline it... OK, so I looked it up... it's the same as the Batcher sort/merge that I've played with before. Sorting 64 items requires 543 compare/swap blocks, and the longest path goes through 21 of these blocks. Each block consists of a 64-bit magnitude comparator and two 64-bit 2:1 muxes to do the swap. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 105049
Hello John ! Are you related to the famous "Red Adair" ? He put out an oilwell fire here i Norway some 20 years ago or so. Anyway, I wish you luck with the new dev. board, I only hope is has a better life ecpentancy than the SP305, wich i purchased, only to realise that the board went out of production after a few weeks, and no support from Xilinx... "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1152620387.58731.0@iris.uk.clara.net... > Following our recent Swinyard1 (Virtex-4) release we are now looking at the > Swinyard2 module concept which will be based on a middle end Virtex-5 > (initial XC5VLX50 and others) that will be supported by our Broaddown series > of main development boards. Bearing in mind this a small module what > features would you like us to put on this module? > > and what did you all think of the general Swinyard concept? > > This is you chance to influence what we deliver to the marketplace so do let > us know. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > >
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