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Messages from 104375

Article: 104375
Subject: Re: VHDL model for Micron SDRAM simulation ?
From: "sjulhes" <t@aol.fr>
Date: Mon, 26 Jun 2006 17:39:25 +0200
Links: << >>  << T >>  << A >>
Thanks for the answers but as I don't know anything in verilog (!) could 
someone give me a little example of how to declare a verilog component in a 
vhdl file and how to instanciate it in the vhdl file.

Thank you.

Stéphane.

"Sean Durkin" <smd@despammed.com> a écrit dans le message de news: 
449fecbb$1@news.fhg.de...
> sjulhes wrote:
>> Hello all,
>>
>> I'm desigining a Xilinx FPGA with a sdram controller for a 
>> MT48LC8M16A2-75
>> memory but I can not find anymore the VHDL model on the Micron's website 
>> !
>>
>> Does someone know if it still possible to get a VHDL from Micron ?
> I contacted them to get VHDL models just last week and got the following
> reply:
>
> "Unfortunately we no longer support VHDL models, as they have not been
> actively developed in many years.
> If you absolutely require a VHDL model, I suggest using a 3rd party
> model that can be compiled into VHDL (or many other languages).
> www.denali.com or www.synopsys.com"
>
> So unless you can find an older model somewhere (they used to have VHDL
> models), there's no VHDL from Micron anymore.
>
>> As there still verilog models on the Micron's website and as my modelsim
>> simulator can handle both vhdl and verilog, can someone give some clues 
>> to
>> use this verilog sdram model in my vhdl simulation project ?
> It's pretty much the same as you would do it with VHDL. Just add it to
> your project, instantiate it in your VHDL (in your testbench or
> whatever), and there you go. You just have to be able to "read" Verilog
> good enough that you can get the port descriptions for the entity. Plus,
> when you compile the Verilog model you have to specify the speed grade
> as a define, which you can normally pass to the compiler as a command
> line argument.
>
> cu,
> Sean 



Article: 104376
Subject: PicoBlaze and DDR Ram
From: "karrelsj" <karrelsj@gmail.com>
Date: 26 Jun 2006 08:53:26 -0700
Links: << >>  << T >>  << A >>
Hello.

I just started looking at Picoblaze.  Has anyone completed a Picoblaze
and DDR RAM implementation?  Or does anyone have any strong opinions on
this issue.  My main goal is to store program data on RAM and access it
with Picoblaze. I see OpenCores has a DDR/SDRAM controller...

Thanks for your constructive ideas.


Article: 104377
Subject: Re: R: still having same error
From: Duane Clark <junkmail@junkmail.com>
Date: Mon, 26 Jun 2006 16:17:56 GMT
Links: << >>  << T >>  << A >>
blisca wrote:
> I.e . failed to access  library 'xilinxcorelib' at "xilinxcorelib"

The xilinxcorelib is located in $XILINX/verilog/src/XilinxCoreLib/, 
assuming you are using verilog. There is a corresponding VHDL version 
available.

> 
> i ask,where is the path used for searching?in modelsim.ini?

I am not really familiar with how things are done in verilog. Hopefully 
someone will mention if there is a better way. The one time I used it, I 
created a compilation file, pmc_tb.f, that contained all the sources, 
that looked like:

+licq_all+
+access+r

../tb/bd_top.v
../tb/bd_test.v
../tb/dumb_targ64.v
../source/pcim_top.v
../source/cfg_pmc.v

+libext+.vmd+.v
-y $XILINX/verilog/src/unisims
-y $XILINX/verilog/src/simprims

Then I compiled with the statement "vlog -f pmc_tb.f". That can be 
included in a modelsim "do file".


> 
> what does it means this syntax?
> 
> verilog = $MODELTECH/../verilog

To start out with, notice that the modelsim.ini file is divided into 
sections, each with a header enclosed in brackets []. The first section, 
with that verilog line, is included in the [Library] section. As far as 
I know, the library section is only used by VHDL code, though I am not 
sure what that verilog line is used for. VHDL has a concept of libraries 
that seems to be different from Verilog. I am mainly familiar with VHDL.

> 
> what are the dots about?and  why slash is used?normally a path is indicated
> using backslashes

The Xilinx software was originally written for and only available on 
Unix machines, where a forward slash is used as a path separator. The 
double dots mean the same as on Windows; that is, move up one level in 
the directory structure.

It is fairly obvious to those who have used the Xilinx software for many 
years that the core tools have a lot of common code between the Windows 
and Unix/Linux versions, and the GUIs are mainly wrappers around these 
core tools. This has the added advantage that you really don't need to 
use the GUIs if you don't want. All the processing can be done at the 
command line, or with batch files, or makefiles, or any other way desired.

Article: 104378
Subject: Re: newbie wants to do VHDL on an FPGA
From: Philip Freidin <philip@fliptronics.com>
Date: Mon, 26 Jun 2006 16:28:15 GMT
Links: << >>  << T >>  << A >>
On 24 Jun 2006 15:04:13 -0700, frankgerlach@gmail.com wrote:
>Hello folks,
>I am doing this as a hobby venture, so I can't pay thousands of $$ 
>for design software.
>Can the experts of this newsgroup suggest a demo board and
>free/cheap software that fulfill those requirements ? Maybe a board
>from Xilinx and their ISE software? (I could not find out whether ISE
>actually includes VHDL synthesis...) As an alternative, I would be
>willing to specify my design in C if there is a free/cheap synthesis
>tool...


There are hundreds of boards listed at the FPGA-FAQ site:

    http://www.fpga-faq.org/FPGA_Boards.shtml

Xilinx provides their full suite of software for support of their
smaller products for free. It is called WebPak. This includes
synthesis (VHDL and Verilog), simulation, place and route, bit
stream generation, and download software. 

Check the Xilinx web site for the part numbers supported by the
free sw, and pick your board accordingly.

Note that for hobby use, what Xilinx calls small (as in supported by
WebPak) is in fact quite large. Quite sophisticated designs can be
done in these parts.

Philip

===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG

Article: 104379
Subject: Re: VHDL model for Micron SDRAM simulation ?
From: Duane Clark <junkmail@junkmail.com>
Date: Mon, 26 Jun 2006 16:30:42 GMT
Links: << >>  << T >>  << A >>
sjulhes wrote:
> Thanks for the answers but as I don't know anything in verilog (!) could 
> someone give me a little example of how to declare a verilog component in a 
> vhdl file and how to instanciate it in the vhdl file.

There is no special syntax for Verilog models. For instance, I use the 
Micron models for the mt16vddf12864. It starts out with:

module mt16vddf12864 (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, 
Cas_n, We_n, Dm);
   inout [0 : 63] Dq;
   inout  [0 : 7] Dqs;
   input [0 : 12] Addr;
   input  [0 : 1] Ba;
   input  [0 : 2] Clk;
   input  [0 : 2] Clk_n;
   input  [0 : 1] Cke;
   input  [0 : 1] Cs_n;
   input          Ras_n;
   input          Cas_n;
   input          We_n;
   input  [0 : 7] Dm;


And it is compiled into the work directory with:
vlog mt16vddf12864.v


My testbench contains:

    -- MICRON DDR SDRAM Simulation Model
    DIMM : entity mem.MT16VDDF12864
    port map (
       Dq             => DDR_DQ,
       Dqs            => DDR_DQS,
--      Addr           => DDR_Addr(C_DDR_AWIDTH-11 to 12),
       Addr           => DDR_Addr(0 to 12),
       Ba             => DDR_BankAddr,
       Clk(0)         => DDR_Clk_0,
       Clk(1)         => DDR_Clk_1,
       Clk(2)         => DDR_Clk_0,
       Clk_n(0)       => DDR_Clkn_0,
       Clk_n(1)       => DDR_Clkn_1,
       Clk_n(2)       => DDR_Clkn_0,
       Cke            => DDR_CKE,
       Cs_n           => DDR_CSn,
       Ras_n          => DDR_RASn,
       Cas_n          => DDR_CASn,
       We_n           => DDR_WEn,
       Dm             => DDR_DM
    );

Where my project.mpf file contains:
[Library]
mem = $MODELS/mem/work

Which is where I compiled the Micron models.

Article: 104380
Subject: R: still having same error
From: "blisca" <blisca@tiscali.it>
Date: Mon, 26 Jun 2006 17:33:42 +0100
Links: << >>  << T >>  << A >>
I.e . failed to access  library 'xilinxcorelib' at "xilinxcorelib"

i ask,where is the path used for searching?in modelsim.ini?

what does it means this sintax?

verilog = $MODELTECH/../verilog

what are the dots about?and  why slash is used?normally a path is indicated
using backslashes


thank you



Article: 104381
Subject: Re: still having same error
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Mon, 26 Jun 2006 17:35:21 +0100
Links: << >>  << T >>  << A >>

"blisca" <blisca@tiscali.it> wrote in message
news:449fffdb$0$16939$4fafbaef@reader4.news.tin.it...
> I.e . failed to access  library 'xilinxcorelib' at "xilinxcorelib"
>
> i ask,where is the path used for searching?in modelsim.ini?

Read the Modelsim manual.

> what does it means this sintax?
> verilog = $MODELTECH/../verilog

MODELTECH is an environment variable. It usually points to the directory
containing the Modelsim binaries.

> what are the dots about?

.. = up one directory, because the libraries will usually be in a directory
parallel to the binary files, not in a subdirectory.

> and  why slash is used?normally a path is indicated
> using backslashes

No, that's just Windows. The rest of the world uses forward-slashes for path
separators. Modelsim was originally a UNIX app and as such uses UNIX
conventions all over the place.

    -Ben-



Article: 104382
Subject: Re: PicoBlaze and DDR Ram
From: "Peter Alfke" <peter@xilinx.com>
Date: 26 Jun 2006 09:47:09 -0700
Links: << >>  << T >>  << A >>
How big a RAM do you need? PicoBlaze is usually a small 8-bit
controller that only uses BlockRAM.
Peter Alfke, Xilinx
==========
karrelsj wrote:
> Hello.
>
> I just started looking at Picoblaze.  Has anyone completed a Picoblaze
> and DDR RAM implementation?  Or does anyone have any strong opinions on
> this issue.  My main goal is to store program data on RAM and access it
> with Picoblaze. I see OpenCores has a DDR/SDRAM controller...
> 
> Thanks for your constructive ideas.


Article: 104383
Subject: Re: R: R: stillcan't access xilinxcorelib,where does modelsim looks
From: Duane Clark <junkmail@junkmail.com>
Date: Mon, 26 Jun 2006 17:09:57 GMT
Links: << >>  << T >>  << A >>
blisca wrote:
> sadly vcom is not able to find xilinxcorelib
> in modelsim xe workspace i can read in the second row
> vhdl                library  C:/xilinx... and so on ,the path where the
> xilinxcore lib really is
> 

Are you using Verilog or VHDL?

Article: 104384
Subject: Re: multisource on signal in XPS
From: "savs" <vidyutg@gmail.com>
Date: 26 Jun 2006 10:14:48 -0700
Links: << >>  << T >>  << A >>
here is the mhs file ....... though in this there is only one instance
of microblaze .... still not working ....

 PARAMETER VERSION = 2.1.0


 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Addr_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Addr, VEC = [0:12], DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_BankAddr_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_BankAddr, VEC = [0:1], DIR =
OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CASn_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CASn, DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CKE_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CKE, DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CSn_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CSn, DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_RASn_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_RASn, DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_WEn_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_WEn, DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DM_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DM, VEC = [0:1], DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQS_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQS, VEC = [0:1], DIR = INOUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQ_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQ, VEC = [0:15], DIR = INOUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clk_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clk, DIR = OUT
 PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clkn_pin =
fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clkn, DIR = OUT
 PORT fpga_0_HYB25D256800AT_DDR_CLK_FB = ddr_feedback_s, DIR = IN
 PORT sys_clk_pin = dcm_clk_s, DIR = IN
 PORT sys_rst_pin = sys_rst_s, DIR = IN
 PORT OPB_Clk = sys_clk_s, DIR = IN
 PORT OPB_Clk_n = sys_clk_n_s, DIR = IN


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_BASEADDR = 0x31000000
 PARAMETER C_HIGHADDR = 0x3100ffff
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN opb_ddr
 PARAMETER INSTANCE = Infineon_DDR_HYB25D256800AT_7
 PARAMETER HW_VER = 1.10.a
 PARAMETER C_DDR_DWIDTH = 16
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_INCLUDE_BURST_SUPPORT = 1
 PARAMETER C_REG_DIMM = 1
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CLK_PAIRS = 1
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x003fffff
 BUS_INTERFACE SOPB = ddrram_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Addr = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Addr
 PORT DDR_BankAddr = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_BankAddr
 PORT DDR_CASn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CASn
 PORT DDR_CKE = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CKE
 PORT DDR_CSn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CSn
 PORT DDR_RASn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_RASn
 PORT DDR_WEn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_WEn
 PORT DDR_DM = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DM
 PORT DDR_DQS = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQS
 PORT DDR_DQ = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQ
 PORT DDR_Clk = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clk
 PORT DDR_Clkn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clkn
 PORT Clk90_in = clk_90_s
 PORT Clk90_in_n = clk_90_n_s
 PORT OPB_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK180_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = sys_clk_s
 PORT CLK0 = dcm_clk_s
 PORT CLK90 = clk_90_s
 PORT CLK180 = dcm_clk_n_s
 PORT CLK270 = clk_90_n_s
 PORT CLKFB = dcm_1_FB
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN bram_block
 PARAMETER INSTANCE = tag_bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_PORT_AWIDTH = 32
 PARAMETER C_PORT_DWIDTH = 32
 PARAMETER C_MEMSIZE = 2048
 BUS_INTERFACE PORTA = tag_connector
END

BEGIN bram_block
 PARAMETER INSTANCE = cac_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = cac_connector
END

BEGIN opb_bram_if_cntlr
 PARAMETER INSTANCE = opb_tag_bram_cntlr
 PARAMETER HW_VER = 1.00.a
 PARAMETER c_baseaddr = 0x00000000
 PARAMETER c_highaddr = 0x0000ffff
 BUS_INTERFACE SOPB = tag_opb
 BUS_INTERFACE PORTA = tag_connector
 PORT opb_clk = sys_clk_s
END

BEGIN opb_bram_if_cntlr
 PARAMETER INSTANCE = opb_cac_bram_cntlr
 PARAMETER HW_VER = 1.00.a
 PARAMETER c_baseaddr = 0x00000000
 PARAMETER c_highaddr = 0x0000ffff
 BUS_INTERFACE SOPB = cac_opb
 BUS_INTERFACE PORTA = cac_connector
 PORT opb_clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = tag_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_BASEADDR = 0x42c00000
 PARAMETER C_HIGHADDR = 0x42c0ffff
 PORT OPB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = cac_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_BASEADDR = 0x42c40000
 PARAMETER C_HIGHADDR = 0x42c4ffff
 PORT OPB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = ddrram_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_BASEADDR = 0x42c20000
 PARAMETER C_HIGHADDR = 0x42c2ffff
 PORT OPB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN cntrl_cache_masters
 PARAMETER INSTANCE = cntrl_cache_masters_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x76000000
 PARAMETER C_HIGHADDR = 0x7600ffff
 BUS_INTERFACE CAC_OPB = cac_opb
 BUS_INTERFACE TAG_OPB = tag_opb
 BUS_INTERFACE DDRRAM_OPB = ddrram_opb
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PORT RST = dcm_0_lock
 PORT CLKIN = ddr_feedback_s
 PORT CLKFB = dcm_1_FB
 PORT CLK0 = dcm_1_FB
 PORT CLK90 = ddr_clk_90_s
 PORT CLK270 = ddr_clk_90_n_s
 PORT LOCKED = dcm_1_lock
END


Article: 104385
Subject: R: R: still having same error
From: "blisca" <blisca@tiscali.it>
Date: Mon, 26 Jun 2006 18:23:38 +0100
Links: << >>  << T >>  << A >>
thank you very much for the extended answer
Duane Clark <junkmail@junkmail.com> wrote in message
UMTng.73159$4L1.41875@newssvr11.news.prodigy.com...
> blisca wrote:
> > I.e . failed to access  library 'xilinxcorelib' at "xilinxcorelib"
>
> The xilinxcorelib is located in $XILINX/verilog/src/XilinxCoreLib/,
> assuming you are using verilog. There is a corresponding VHDL version
> available.
>
> >
> > i ask,where is the path used for searching?in modelsim.ini?
>
> I am not really familiar with how things are done in verilog. Hopefully
> someone will mention if there is a better way. The one time I used it, I
> created a compilation file, pmc_tb.f, that contained all the sources,
> that looked like:
>
> +licq_all+
> +access+r
>
> ../tb/bd_top.v
> ../tb/bd_test.v
> ../tb/dumb_targ64.v
> ../source/pcim_top.v
> ../source/cfg_pmc.v
>
> +libext+.vmd+.v
> -y $XILINX/verilog/src/unisims
> -y $XILINX/verilog/src/simprims
>
> Then I compiled with the statement "vlog -f pmc_tb.f". That can be
> included in a modelsim "do file".
>
>
> >
> > what does it means this syntax?
> >
> > verilog = $MODELTECH/../verilog
>
> To start out with, notice that the modelsim.ini file is divided into
> sections, each with a header enclosed in brackets []. The first section,
> with that verilog line, is included in the [Library] section. As far as
> I know, the library section is only used by VHDL code, though I am not
> sure what that verilog line is used for. VHDL has a concept of libraries
> that seems to be different from Verilog. I am mainly familiar with VHDL.
>
> >
> > what are the dots about?and  why slash is used?normally a path is
indicated
> > using backslashes
>
> The Xilinx software was originally written for and only available on
> Unix machines, where a forward slash is used as a path separator. The
> double dots mean the same as on Windows; that is, move up one level in
> the directory structure.
>
> It is fairly obvious to those who have used the Xilinx software for many
> years that the core tools have a lot of common code between the Windows
> and Unix/Linux versions, and the GUIs are mainly wrappers around these
> core tools. This has the added advantage that you really don't need to
> use the GUIs if you don't want. All the processing can be done at the
> command line, or with batch files, or makefiles, or any other way desired.



Article: 104386
Subject: Re: PicoBlaze and DDR Ram
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 26 Jun 2006 19:24:07 +0200
Links: << >>  << T >>  << A >>
karrelsj schrieb:
> Hello.
> 
> I just started looking at Picoblaze.  Has anyone completed a Picoblaze
> and DDR RAM implementation?  Or does anyone have any strong opinions on
> this issue.  My main goal is to store program data on RAM and access it
> with Picoblaze. I see OpenCores has a DDR/SDRAM controller...
> 
> Thanks for your constructive ideas.

I guess this is the wrong combination. Picoblaze is just a small 8 bit 
Micro, with only 256/1024 (Spartan-2/Spartan-3) words of instruction 
space directly addressable. If you need mor program space,

a) use two or more picoblaze, the are small
b) use bank switching to access multiple banks of BRAM

Regards
Falk

Article: 104387
Subject: Raggedstone1 Brackets
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 26 Jun 2006 18:59:09 +0100
Links: << >>  << T >>  << A >>
For those of asking for Raggedstone1 brackets we have them in now. Item will 
appear on our shop site in due course.

John Adair
Enterpoint Ltd. - Home of Swinyard1. The Virtex-4 Module.
http://www.enterpoint.co.uk



Article: 104388
Subject: R: R: stillcan't access xilinxcorelib,where does modelsim looks for it?
From: "blisca" <blisca@tiscali.it>
Date: Mon, 26 Jun 2006 19:05:58 +0100
Links: << >>  << T >>  << A >>
sadly vcom is not able to find xilinxcorelib
in modelsim xe workspace i can read in the second row
vhdl                library  C:/xilinx... and so on ,the path where the
xilinxcore lib really is

it is honest to suppose tha the vcon compilator will search for the library
exactly and only here?

if i click on the "+" symbol to expand it i can see a tree of entities (a
blue "E" in a white square)starting with

addr_gen_v3

iis it correct?thank you again

i hope this could be usefule for other newbies





Article: 104389
Subject: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
From: fpga_toys@yahoo.com
Date: 26 Jun 2006 11:06:21 -0700
Links: << >>  << T >>  << A >>

Simon Heinzle wrote:
> I need a C Simulation of some Floating Point Cores from the Xilinx coregen.
> I thought about automatically converting the behavioral VHDL code to C, e.g.
> with V2C or VHDL-2-C (found via comp.lang.vhdl FAQ part 3).
>
> While I'm investigating this -- has anyone in this group already done
> something similar, or are there C Simulations of the cores available
> somewhere?

Hi Simon,

People simulate for two reasons ... to prove correctness, and to
evaluate timings and performance. The translation from HDL to C is
primarily simulation to verify correctness, especially where cores are
involved. Timing/performance simulation requires a very tight
integration with the target tool chain and architecture, something lost
with generic C simulation of an HDL source.

Just what are you looking for?

John


Article: 104390
Subject: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
From: "Hans" <hans64@ht-lab.com>
Date: Mon, 26 Jun 2006 18:33:58 GMT
Links: << >>  << T >>  << A >>
Can't you co-simulate? that is, put a SystemC/FLI/VHPI wrapper around your C 
code and load that into your simulator? Alternatively, use shared 
memory/files/sockets to communicate between your C code and your simulator.

If you do translate,  how are you planning to validate your translated 
model? Remember you are converting from a concurrent to a sequential 
language which might not be that easy...,

Hans
www.ht-lab.com



"Simon Heinzle" <sheinzle@inf.ethz.ch> wrote in message 
news:449fefd7$1@news1.ethz.ch...
> Hi Guys,
>
> I need a C Simulation of some Floating Point Cores from the Xilinx 
> coregen. I thought about automatically converting the behavioral VHDL code 
> to C, e.g. with V2C or VHDL-2-C (found via comp.lang.vhdl FAQ part 3).
>
> While I'm investigating this -- has anyone in this group already done 
> something similar, or are there C Simulations of the cores available 
> somewhere?
>
> Thanks,
> Simon
>
> 



Article: 104391
Subject: Re: multisource on signal in XPS
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 26 Jun 2006 11:40:08 -0700
Links: << >>  << T >>  << A >>

savs wrote:

> BEGIN dcm_module
>  PARAMETER INSTANCE = dcm_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_CLK0_BUF = TRUE
>  PARAMETER C_CLK180_BUF = TRUE
>  PARAMETER C_CLK270_BUF = TRUE
>  PARAMETER C_CLK90_BUF = TRUE
>  PARAMETER C_CLKIN_PERIOD = 10.000000
>  PARAMETER C_CLK_FEEDBACK = 1X
>  PARAMETER C_EXT_RESET_HIGH = 1
>  PORT CLKIN = sys_clk_s
>  PORT CLK0 = dcm_clk_s
>  PORT CLK90 = clk_90_s
>  PORT CLK180 = dcm_clk_n_s
>  PORT CLK270 = clk_90_n_s
>  PORT CLKFB = dcm_1_FB
>  PORT RST = net_gnd
>  PORT LOCKED = dcm_0_lock
> END

You inverted CLKIN and CLK0


Article: 104392
Subject: Re: R: R: R: stillcan't access xilinxcorelib,where does modelsim
From: Duane Clark <junkmail@junkmail.com>
Date: Mon, 26 Jun 2006 19:06:37 GMT
Links: << >>  << T >>  << A >>
blisca wrote:
> Duane Clark <junkmail@junkmail.com> wrote in message
> FxUng.53669$fb2.51470@newssvr27.news.prodigy.net...
>> blisca wrote:
>>> sadly vcom is not able to find xilinxcorelib
>>> in modelsim xe workspace i can read in the second row
>>> vhdl                library  C:/xilinx... and so on ,the path where the
>>> xilinxcore lib really is
>>>
>> Are you using Verilog or VHDL?
> 
> 
> i'm using vhdl

Then in the [Library] section, you need a line like:
xilinxcorelib = $XILINX/vhdl/src/XilinxCoreLib/work

But before that will work, you need to actually compile the 
xilinxcorelib sources. There is a tool/script for that somewhere, 
included with the Xilinx tools. I haven't used the Xilinx supplied tool 
for compiling it, though. I do it manually, by creating a work directory:
vlib work
and then compiling the source:
vcom prims_constants_v4_0.vhd
vcom c_dist_mem_v5_0_comp.vhd
vcom blkmemdp_pkg_v4_0.vhd
vcom blkmemdp_v4_0_comp.vhd
...etc

But for someone doing it the first time, you should probably find and 
use the tool. Go to the xilinx website, and type xilinxcorelib into the 
search box, and for me, the second link shows how to compile those 
libraries.

Article: 104393
Subject: Re: PicoBlaze and DDR Ram
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 27 Jun 2006 07:36:58 +1200
Links: << >>  << T >>  << A >>
karrelsj wrote:
> Hello.
> 
> I just started looking at Picoblaze.  Has anyone completed a Picoblaze
> and DDR RAM implementation?  Or does anyone have any strong opinions on
> this issue.  My main goal is to store program data on RAM and access it
> with Picoblaze. I see OpenCores has a DDR/SDRAM controller...
> 
> Thanks for your constructive ideas.

  Do you mean a large data-space in DDR, and that the PicoBlaze runs from
Block Ram in the FPGA ?
  That would be do-able, and you could add features like the Serial FLASH
devices have, which is auto-inc of Rd/Wr address, for continual access.
( that saves a lot of address thrashing )

  If you needed more code, two bock RAMS, with reload-flip support in
the FPGA, would allow the DDR behave like a HardDisk (from
the code perspective).

What split and sizes do you need for Code/data ?

-jg



Article: 104394
Subject: R: R: R: stillcan't access xilinxcorelib,where does modelsim looksfor it?
From: "blisca" <blisca@tiscali.it>
Date: Mon, 26 Jun 2006 20:51:39 +0100
Links: << >>  << T >>  << A >>

Duane Clark <junkmail@junkmail.com> wrote in message
FxUng.53669$fb2.51470@newssvr27.news.prodigy.net...
> blisca wrote:
> > sadly vcom is not able to find xilinxcorelib
> > in modelsim xe workspace i can read in the second row
> > vhdl                library  C:/xilinx... and so on ,the path where the
> > xilinxcore lib really is
> >
>
> Are you using Verilog or VHDL?


i'm using vhdl



Article: 104395
Subject: Xilinx ML461 memory board, whats the real story?
From: "lecroy7200@chek.com" <lecroy7200@chek.com>
Date: 26 Jun 2006 13:46:59 -0700
Links: << >>  << T >>  << A >>
We purchased an ML461 board in Aug of 05 for $6000 from Avnet.  If I
follow the documention that came with the board, it has a memory test
screen that led me to believe that the board is running some sort of
memory test and reporting errors on the LCD.   If I look at the source
files the came with the board, they do not appear to be what was used
to create the actual images being loaded into the board.  So, for
example, FPGA 4 controls all of the LCD functions, however looking at
the actual code that was supplied for FPGA 4, there is no support for
the LCD.  The actual code for FPGA 4, for example will not even compile
without errors.   What is more strange is that if I look in FPGA 3
which contains the QDR controller, there appears to be only one signal
that reports the errors back to FPGA 4 and it is not routed to it.  So,
there appears to be no way for FPGA to actually detect an error.  For
fun, if I load FPGA 3 with the binary for FPGA 2, FPGA 4 reports no
memory errors on the LCD.  Not that this proves that the design was
faulted, but it does raise my suspicions.  I also found some other pins
defined in the source files that do not match the schematics that were
supplied.

I had opened a case, spoke with two different FAEs and even tried to
get our money back from Avnet.  Avnet claims Xilinx will support the
board and the last message from them provided me an inside contact at
Xilinx who was supposed to know this board and be able to help.  When I
called him a few weeks ago he explained he was in marketing, not
engineering and suggested that I open a case number with Xilinx, which
I have, yet again.   I have now came full circle with this board.

Does anyone here have all of the code that was used to create the
images for this board?


Article: 104396
Subject: Re: multisource on signal in XPS
From: Sean Durkin <smd@despammed.com>
Date: Mon, 26 Jun 2006 23:11:25 +0200
Links: << >>  << T >>  << A >>
> here is the mhs file ....... though in this there is only one instance
> of microblaze .... still not working ....
Let's have a look...

There it is:
>  PORT sys_clk_pin = dcm_clk_s, DIR = IN
"sys_clk_pin" is the external pin where the clock comes into the fpga.
You tell EDK to use the internal signal "dcm_clk_s" for this clock, i.e.
to drive the internal signal "dcm_clk_s" from the pin "sys_clk_pin".

> BEGIN dcm_module
> [snip]
>  PORT CLKIN = sys_clk_s
>  PORT CLK0 = dcm_clk_s
... and here you connect the OUTPUT of the DCM (CLKIN is the input, as
the name suggests, CLK0 is an output) to the same signal as above. So
"dcm_clk_s" is driven both by the DCM and by the external clock that
comes into the FPGA => multisource signal. You need to swap "sys_clk_s"
and "dcm_clk_s" here.

This is just what Zara suggested.

cu,
Sean

Article: 104397
Subject: Re: Space invaders on Spartan3e starter board
From: Michael <michael.dangler@gmail.com>
Date: Mon, 26 Jun 2006 14:12:44 -0700
Links: << >>  << T >>  << A >>
Nice application, was wondering where or how does one get the ROM needed to complete the design. Thanks.

Cheers, Michael

Article: 104398
Subject: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
From: christopher.saunter@durham.ac.uk (c d saunter)
Date: Mon, 26 Jun 2006 22:33:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
fpga_toys@yahoo.com wrote:

: People simulate for two reasons ... to prove correctness, and to
: evaluate timings and performance. The translation from HDL to C is
: primarily simulation to verify correctness, especially where cores are
: involved. Timing/performance simulation requires a very tight
: integration with the target tool chain and architecture, something lost
: with generic C simulation of an HDL source.

: Just what are you looking for?

I can think of a few things...

For example you might want to create a model in C / Matlab / whatever of a 
wider system incorporating an FPGA pipeline and feed it lots of sample 
datasets or link it to a Monte-Carlo simulation etc., and look at the 
effect of precision/dynamic range in the context of the overall system.

A quick and dirty way of doing that is to do some bit masking etc. in C.

---

cds



Article: 104399
Subject: ISE WebPack 8.2
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 26 Jun 2006 22:46:58 GMT
Links: << >>  << T >>  << A >>
Does anyone know if the 8.2 version of the ISE WebPack will support a wider 
range of devices or not? I'm particularly interested in the V II Pro range.

TIA,

Rog. 





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