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Antti wrote: > aName schrieb: > > >>Implementing USB slow protocol into xilink XC95xxx.. >>I don't need long vendor string and stuff like that just the basic protocol. >> >>Is it possible ? it seems pretty complex to do ... > > > do not try. I want say it is impossible - as only a few things are. > > SiLabs F326 usb micro has internal oscillator and costs 2.36 USD qty 1. > > any attempts to implemented USB with PLD or FPGA would cost more both > component cost and time spent. > > Antti > http://antti-brain.com > :-) Ofcourse what I meant is, implementing it for fun ;-) It is alot cheaper to buy it in ic ;-) For hobby I was looking for FTDI ics, but thank, I didn't know SiLabs. BTW I bought for a fair price a really simple USB - FIFO bridge (USBMOD4) from elexom.com for playing around and it works great in few minutes ;-) http://www.youtube.com/watch?v=UAzWsvPob7A :-)Article: 105001
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1152631088.157071.29040@75g2000cwc.googlegroups.com... > Hi Dann, > I have 3 good website to deal with sorting speed: > 1. http://www.azillionmonkeys.com/qed/sort.html > 2. http://www.eternallyconfuzzled.com/tuts/sorting.html#heap > 3. > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/d8380e137bdb410f/6d2a65ca85ac8bfc?lnk=st&q=Bitonic+sort&rnum=10#6d2a65ca85ac8bfc > > None of them mentioned radix sorting as the candidate as the fastest > sorting algorithm. If a tree falls in a forest with no ear to hear it, does it make a sound? Radix sort is the fastest way to sort a long list of integers. Period. > In the last email I referenced a measurement: > with 1000 values, the times were: ~275000 in clocks for bucket, ~435000 > in clocks for qsort. 1000 values is a trivial set. There are many optimizations that can be done for Radix sort. For instance, you can count all the buckets in a single pass for LSD radix sort. That means you have one counting pass, and (with 16 bit buckets) 2 distribution passes. There is simply no way for a comparison sort to do better. You were talking about a million objects in the list. With a list like that, Radix or bucket sort will dominate. If you have a billion items, then it is no contest. If (on the other hand) you have very long keys, then the comparison sorts become competitive. But for keys that are only a few bytes long, distribution rather than comparison sorts are the obvious choice. With special data sets and with small data sets, other sorts will be faster. But you can special case the entry point into your sort routine. > The measurement was made in 1999. > > I like to have more similar data in clocks with best algorithm and best > CPU available now. It is not difficult to do it yourself. > I really don't understand that for one data, above measurement needs > 1000 clocks . Probably a function of CLOCKS_PER_SECOND. > Why? Any comments? > > Weng >Article: 105002
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pippo wrote:
> i'm trying to map a very large design onto a stratix EP1S80B956C7
> device.
> After timing analysis with Quartus II 5.0 i have a "lot of high setup
> violations"
> on paths between registers of the such type of FF1 and FF2
> (see vhdl below that is pheraps only a simplification of the entire
> project).
OK. Let's have a look on the viewer:
http://home.comcast.net/~mike_treseler/prova.pdf
You really only have one clock.
The setup violations would go away if you could
synch up whatever is driving EN1,2.
-- Mike Treseler
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Article: 105003The Unused Pin Option setting is in: Assignments Settings->Device->Device & Pin Options->Unused Pins. Hope this helps, Subroto Datta Altera Corp. Tommy Thorn wrote: > rnbrady wrote: > > I have a VHDL design which I'm putting on an FPGA with Quartus II. > > There is a specific pin on the FPGA which I need to drive high. This > > pin has no corresponding port in my VHDL file and I don't want to edit > > the VHDL file. > > > > I can find the option in Quartus to assign all unused pins to say > > "driving low." However I want to keep the default at "driving low" > > while assigning just this pin to "driving high." > > This is one of the most mind boggling things about Quartus II. By > default it set all unspecified pins to ground, which is a terrible > default as one quick first test is likely to miss this and will end up > driving ground to a bunch of should-be input pins. > > Richard, the fix for you problem is (from memory) to enter the general > settings (assignments?) and change the pin default from "output driving > ground" to "input tristated". That should solve this problem > completely. > > Tommy > > > > > > The reason for this is that the default drving low value causes the > > configuration controller on my dev-kit (NiosII Stratix kit) to > > reconfigure repeatedly. > > > > How can I assign just one pin to drive high? I'm certain it can be > > done, but for the life of me I cannot find the option in Quartus. > > > > Thanks in advance, > > RichardArticle: 105004
Hi Pippo, Here are some guidelines and hints when using multicycle assignments. "After timing analysis with Quartus II 5.0 i have a "lot of high setup violations" on paths between registers of the such type of FF1 and FF2 " In the example design, there are no paths between FF1 and FF2, so any timing assignment will be ignored. But assuming such a path exists: - The clock_enable_multicycle constraint must be related to a hard timing edge(flop/pin) that derives the clock enable. This could be either internal_EN1 or internal_EN2. This is usually good practice anyway, since making assignments to nets like internal_ENA can be dangerous, since synthesis tools often change combinatorial node names(yes, there are ways around this, but for now it's easier to use the flop) - Think of the clock_enable_multicycle as a way to make a group and then apply a constraint. So everything that EN1 fans out to as a clock enable, even if it goes through logic, will be added to that group. So all that needs to be added is: set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -to internal_EN1 - Note that the -from/-to version of this constraint is best applied when there are multiple clock enables feeding different groups of registers, and the user is trying to constrain paths between those groups. The Quartus Help -> Index -> clock_enable_multicycle shows this. Hope this helps, Subroto Datta Altera Corp. pippo wrote: > Hallo to everybody, > i'm trying to map a very large design onto a stratix EP1S80B956C7 > device. > After timing analysis with Quartus II 5.0 i have a "lot of high setup > violations" > on paths between registers of the such type of FF1 and FF2 > (see vhdl below that is pheraps only a simplification of the entire > project). > These paths are multicycle 2 period wide. > Apart from clock settings, in the Assignment Editor i gave to Quartus > the subsequent constraints: > > set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from ENA -to > ENA > set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from > internal_EN1 -to internal_EN1 > set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -to > internal_EN1 > set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from > internal_ENA -to internal_ENA > set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from > internal_ENA -to * > > and after i ran timing analysis again, i got the Ignored Timing > Assignments in the report: > > > -------- option ---------------- setting ---- from --------- to > ----------------- help ----------- > Clock Enable Multicycle 2 internal_EN1 No > timing path applicable to specified destination > Clock Enable Multicycle 2 internal_EN1 internal_EN1 No > timing path applicable to specified source and destination > Clock Enable Multicycle 2 internal_ENA * > Destination wildcard does not match any nodes > Clock Enable Multicycle 2 internal_ENA internal_ENA No > timing path applicable to specified source and destination > Clock Enable Multicycle 2 ENA ENA > No timing path applicable to specified source and destination > > How can i force Quartus to consider paths enabled by ENA signal and > clocked by CLK > as multicycle paths without specifying all registers interested > (it would be difficult for me to built a list, because of their huge > number)? > > Thanks in advance. > Salva > > > ------------------ VHDL ------------------ > > library ieee; > use ieee.std_logic_1164.all; > > entity PROVA is > port ( > RSTN : in std_logic; > CLK : in std_logic; > IN1 : in std_logic; > IN2 : in std_logic; > EN1 : in std_logic; > EN2 : in std_logic; > OUT1 : out std_logic; > OUT2 : out std_logic > ); > end entity PROVA; > > architecture ARCH_1 of PROVA is > > component GLOBAL is > port ( > A_IN : in std_logic; > A_OUT: out std_logic > ); > end component GLOBAL; > > signal internal_CLK : std_logic; > signal internal_EN1 : std_logic; > signal internal_EN2 : std_logic; > signal internal_ENA : std_logic; > > signal ENA : std_logic; > signal FF1 : std_logic; > signal FF2 : std_logic; > signal FF3 : std_logic; > > begin > > -- clock is assigned to a global resource > GLOBAL_STRATIX1: GLOBAL port map(CLK, internal_CLK); > > > -- enable is assigned to a global resource > GLOBAL_STRATIX2: GLOBAL port map(internal_ENA, ENA); > > > -- internally latched signals > internal_CLK_P: process (RSTN, internal_CLK) > begin > if (RSTN = '0') then > internal_EN1 <= '0'; > internal_EN2 <= '0'; > elsif falling_edge(internal_CLK) then -- falling edge > internal_EN1 <= EN1; > internal_EN2 <= EN2; > end if; > end process; > > > -- internally generated enable > internal_ENA <= internal_EN1 and internal_EN2; > > > -- FF with internally generated enable > FF_1_2_P: process (RSTN, internal_CLK) > begin > if (RSTN = '0') then > FF1 <= '0'; > FF2 <= '0'; > elsif rising_edge(internal_CLK) then -- rising edge > if ENA = '1' then > FF1 <= IN1; > if IN1 = IN2 then > FF2 <= '1'; > end if; > end if; > end if; > end process; > > > -- FF without internally generated enable > FF_3_P: process (RSTN, internal_CLK) > begin > if (RSTN = '0') then > FF3 <= '0'; > elsif rising_edge(internal_CLK) then -- rising edge > FF3 <= IN1 and FF2; > end if; > end process; > > > -- outputs assignments > OUT1 <= FF1 or FF2; > OUT2 <= FF1 and FF3; > > > end ARCH_1;Article: 105005
> I have a VHDL design which I'm putting on an FPGA with Quartus II. > There is a specific pin on the FPGA which I need to drive high. This > pin has no corresponding port in my VHDL file and I don't want to edit > the VHDL file. Just out of curiousity, why don't you want to edit the VHDL file since apparently 'as it is now' the design is somewhat deficient in that it doesn't do what you want it to do. KJArticle: 105006
I would **LOVE** A module with a 2.54MM PGA form factor. Something with just the basics (decoupling caps, etc). (I am envsioning something that looks like an old socket 7 intel chip) I work in research where we do alot of our own PCBs and hand-solding, but cannot afford BGA. I only do 2 or 3 boards for a particular project. This limits my ability to use FPGA technology. I would love it if Xilinx still made things in PGA packages...... Alot fo the develop boards are big and clunky. I just want a module. this also makes thngs a bit more modular so I can swap things out later. Cost really isn' tthat big of an issue for me. I need prototyping ability. -Eli Hughes John Adair wrote: > The big issue with the GFZ connectors is that they themselves are not low > cost and tend to set a base cost for the module that takes it out of the > very low cost sector. However we have on our roadmap a FX12 module that is > going to use our DIl style connectors at the lower end. We are also > considering the same as a Spartan-3 solution. Other variations of the theme > we are considering are a module that breaks out a BGA usable PGA on 2.54mm. > We have already done that on a non-FPGA part for a very fine pitch BGA and > in a reasonably economic way for one of our customers. > > The Swinyard2 board will cover a cheaper sector than the Swinyard1 that you > can see on the website. Also if you are considering a small production run > there is room for discounting on Swinyard1. We are pricing on small batch > assembly costs due to the price of some of the silicon. We don't plan on > hold hugh stocks of these boards as there are 18 possible fits of FPGA on > Swinyard1 by the time you consider all sizes and speed grades available. We > are planning to hold stock of a small number of variants - the LX40 and SX55 > initially more if we see the a steady market. As these FPGA are common with > our Broaddown4 product we may also have a quick assemble to order capability > but that depends highly on stock we have at any given time. > > Putting a commercial spin on what we do we can usually come up with a cost > effective solution for products in fairly low production numbers. I won't > put exact numbers on it as I'm sure someone will disagree about what is > considered cost effective but we commonly provide custom solutions for year > product volumes of 10-25 units. By the time we hit 100 off batches we aren't > China style prices but we can definately give good value in the European and > N America context. > > John Adair > Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development > Board. > http://www.enterpoint.co.uk > > > "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message > news:npe7b21ppkddj74csrgr02pvjcbcu36b7l@4ax.com... > >>On Tue, 11 Jul 2006 15:38:53 +0100, John Adair wrote: >> >>[...] >> >>>One of our intentions is that these modules could be used to bring >>>high technology to what are relatively low technology host boards >> >>This is a truly excellent idea. For some while I've been frustrated >>by FPGA development boards that have a ragbag of low-tech >>functionality and connectors, pushing up the price just for me >>to get something I could easily provide for myself. What you're >>offering fixes that - for many users, even in small-scale production, >>the FPGA is the only part of the system that needs fine-line >>PCBs and non-trivial assembly techniques, and a small FPGA-only >>plug-in module is the right answer. >> >>My only concern would be that you've gone for a fairly high-end >>FPGA so the entry cost is quite high. Fine for some purposes, >>but pricing itself out of a potentially useful market for others. >>Have you any plans for a significantly lower-cost product with >>a similar overall approach? >> >>Thanks >>-- >>Jonathan Bromley, Consultant >> >>DOULOS - Developing Design Know-how >>VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services >> >>Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK >>jonathan.bromley@MYCOMPANY.com >>http://www.MYCOMPANY.com >> >>The contents of this message may contain personal views which >>are not the views of Doulos Ltd., unless specifically stated. > > >Article: 105007
I think you have the options pretty much on target. Other than DDR2 memory, the supporting board can pretty much fill in all of the required functionality. By the way, do these GFZ connectors require gold plating on the supporting card to make proper contact? Regards, Gabor John Adair wrote: > The big issue with the GFZ connectors is that they themselves are not low > cost and tend to set a base cost for the module that takes it out of the > very low cost sector. However we have on our roadmap a FX12 module that is > going to use our DIl style connectors at the lower end. We are also > considering the same as a Spartan-3 solution. Other variations of the theme > we are considering are a module that breaks out a BGA usable PGA on 2.54mm. > We have already done that on a non-FPGA part for a very fine pitch BGA and > in a reasonably economic way for one of our customers. > > The Swinyard2 board will cover a cheaper sector than the Swinyard1 that you > can see on the website. Also if you are considering a small production run > there is room for discounting on Swinyard1. We are pricing on small batch > assembly costs due to the price of some of the silicon. We don't plan on > hold hugh stocks of these boards as there are 18 possible fits of FPGA on > Swinyard1 by the time you consider all sizes and speed grades available. We > are planning to hold stock of a small number of variants - the LX40 and SX55 > initially more if we see the a steady market. As these FPGA are common with > our Broaddown4 product we may also have a quick assemble to order capability > but that depends highly on stock we have at any given time. > > Putting a commercial spin on what we do we can usually come up with a cost > effective solution for products in fairly low production numbers. I won't > put exact numbers on it as I'm sure someone will disagree about what is > considered cost effective but we commonly provide custom solutions for year > product volumes of 10-25 units. By the time we hit 100 off batches we aren't > China style prices but we can definately give good value in the European and > N America context. > > John Adair > Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development > Board. > http://www.enterpoint.co.uk > > > "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message > news:npe7b21ppkddj74csrgr02pvjcbcu36b7l@4ax.com... > > On Tue, 11 Jul 2006 15:38:53 +0100, John Adair wrote: > > > > [...] > >> One of our intentions is that these modules could be used to bring > >>high technology to what are relatively low technology host boards > > > > This is a truly excellent idea. For some while I've been frustrated > > by FPGA development boards that have a ragbag of low-tech > > functionality and connectors, pushing up the price just for me > > to get something I could easily provide for myself. What you're > > offering fixes that - for many users, even in small-scale production, > > the FPGA is the only part of the system that needs fine-line > > PCBs and non-trivial assembly techniques, and a small FPGA-only > > plug-in module is the right answer. > > > > My only concern would be that you've gone for a fairly high-end > > FPGA so the entry cost is quite high. Fine for some purposes, > > but pricing itself out of a potentially useful market for others. > > Have you any plans for a significantly lower-cost product with > > a similar overall approach? > > > > Thanks > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.bromley@MYCOMPANY.com > > http://www.MYCOMPANY.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated.Article: 105008
bjzhangwn@gmail.com wrote: > Hi,everyone,I now use the spartan2e400,and I want to use the dll in > fpga,I need 4 clock in fpga,so I have to divide the clock by using the > dlls,I used 3 dlls for my design,and all inputs are the same drived by > clock input ,but when place and route ,the system bring errors like > "can't place the clock pad or can't place the bupg buffers",and the > input clock I constaint it on the global clock,so I have no idea.I do > another thing ,I use only two dlls ,and the design can pass place and > route. It's a known "feature" that the placer gives up when it can't use the simplest possible connections for DLL's and associated global clock buffers. In the Spartan 2e series, DLL's are placed at the top and bottom edges of the chip. Any global clock input can route to any DLL, but only the DLLs on the same side of the chip will meet the tightest available timing. So when you drive two DLL's with one global clock input pin, the placer can choose the two on the same side of the chip as the global input. When you go to three DLL's the placer gives up, since it can't know which of your three DLL's can live with the cross-chip routing delay. You can still do this, but you'll need to add LOC constraints for your DLL's and possibly BUFG's as well. You may be able to fix this using the floorplanner. HTH, GaborArticle: 105009
Well hang on a bit and you may be pleasantly surprised. We have had this idea around for a while and done something similar for a 0.5mm pitch BGA already. It is just a matter of finding a spare day or so from my team to do it. If we do this design ideally would like to line up with a common;y available ZIF PGA, or standard, socket allowing easy and low risk attachment to a board. Eli Hughes wrote: > I would **LOVE** A module with a 2.54MM PGA form factor. Something with > just the basics (decoupling caps, etc). (I am envsioning something that > looks like an old socket 7 intel chip) > > I work in research where we do alot of our own PCBs and hand-solding, > but cannot afford BGA. I only do 2 or 3 boards for a particular > project. This limits my ability to use FPGA technology. I would love > it if Xilinx still made things in PGA packages...... Alot fo the > develop boards are big and clunky. I just want a module. this also > makes thngs a bit more modular so I can swap things out later. > > Cost really isn' tthat big of an issue for me. I need prototyping ability. > > -Eli Hughes > > > > > John Adair wrote: > > The big issue with the GFZ connectors is that they themselves are not low > > cost and tend to set a base cost for the module that takes it out of the > > very low cost sector. However we have on our roadmap a FX12 module that is > > going to use our DIl style connectors at the lower end. We are also > > considering the same as a Spartan-3 solution. Other variations of the theme > > we are considering are a module that breaks out a BGA usable PGA on 2.54mm. > > We have already done that on a non-FPGA part for a very fine pitch BGA and > > in a reasonably economic way for one of our customers. > > > > The Swinyard2 board will cover a cheaper sector than the Swinyard1 that you > > can see on the website. Also if you are considering a small production run > > there is room for discounting on Swinyard1. We are pricing on small batch > > assembly costs due to the price of some of the silicon. We don't plan on > > hold hugh stocks of these boards as there are 18 possible fits of FPGA on > > Swinyard1 by the time you consider all sizes and speed grades available. We > > are planning to hold stock of a small number of variants - the LX40 and SX55 > > initially more if we see the a steady market. As these FPGA are common with > > our Broaddown4 product we may also have a quick assemble to order capability > > but that depends highly on stock we have at any given time. > > > > Putting a commercial spin on what we do we can usually come up with a cost > > effective solution for products in fairly low production numbers. I won't > > put exact numbers on it as I'm sure someone will disagree about what is > > considered cost effective but we commonly provide custom solutions for year > > product volumes of 10-25 units. By the time we hit 100 off batches we aren't > > China style prices but we can definately give good value in the European and > > N America context. > > > > John Adair > > Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development > > Board. > > http://www.enterpoint.co.uk > > > > > > "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message > > news:npe7b21ppkddj74csrgr02pvjcbcu36b7l@4ax.com... > > > >>On Tue, 11 Jul 2006 15:38:53 +0100, John Adair wrote: > >> > >>[...] > >> > >>>One of our intentions is that these modules could be used to bring > >>>high technology to what are relatively low technology host boards > >> > >>This is a truly excellent idea. For some while I've been frustrated > >>by FPGA development boards that have a ragbag of low-tech > >>functionality and connectors, pushing up the price just for me > >>to get something I could easily provide for myself. What you're > >>offering fixes that - for many users, even in small-scale production, > >>the FPGA is the only part of the system that needs fine-line > >>PCBs and non-trivial assembly techniques, and a small FPGA-only > >>plug-in module is the right answer. > >> > >>My only concern would be that you've gone for a fairly high-end > >>FPGA so the entry cost is quite high. Fine for some purposes, > >>but pricing itself out of a potentially useful market for others. > >>Have you any plans for a significantly lower-cost product with > >>a similar overall approach? > >> > >>Thanks > >>-- > >>Jonathan Bromley, Consultant > >> > >>DOULOS - Developing Design Know-how > >>VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > >> > >>Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > >>jonathan.bromley@MYCOMPANY.com > >>http://www.MYCOMPANY.com > >> > >>The contents of this message may contain personal views which > >>are not the views of Doulos Ltd., unless specifically stated. > > > > > >Article: 105010
I think a flat board finish is good thing and one that does not have any nasty oxidising habits. We have done a reasonable amount of testing on some of Broaddown2 boards that have been around our lab for about 2 years. Those particular boards have a siliver finish and not the hard gold finish that would have been optional and whilst there is an obvious level of aging on the finish on the ones we have tested there don't appear to be any problems in any connections. What I would not do with a GFZ connector is use them in harsh environments. That said we don't expect our development boards to be subject to such use although ocasionally we do hear reports of boards ending up in some very strange places that we didn't expect. Gabor wrote: > I think you have the options pretty much on target. Other than DDR2 > memory, the supporting board can pretty much fill in all of the > required > functionality. > > By the way, do these GFZ connectors require gold plating on the > supporting card to make proper contact? > > Regards, > Gabor > > John Adair wrote: > > The big issue with the GFZ connectors is that they themselves are not low > > cost and tend to set a base cost for the module that takes it out of the > > very low cost sector. However we have on our roadmap a FX12 module that is > > going to use our DIl style connectors at the lower end. We are also > > considering the same as a Spartan-3 solution. Other variations of the theme > > we are considering are a module that breaks out a BGA usable PGA on 2.54mm. > > We have already done that on a non-FPGA part for a very fine pitch BGA and > > in a reasonably economic way for one of our customers. > > > > The Swinyard2 board will cover a cheaper sector than the Swinyard1 that you > > can see on the website. Also if you are considering a small production run > > there is room for discounting on Swinyard1. We are pricing on small batch > > assembly costs due to the price of some of the silicon. We don't plan on > > hold hugh stocks of these boards as there are 18 possible fits of FPGA on > > Swinyard1 by the time you consider all sizes and speed grades available. We > > are planning to hold stock of a small number of variants - the LX40 and SX55 > > initially more if we see the a steady market. As these FPGA are common with > > our Broaddown4 product we may also have a quick assemble to order capability > > but that depends highly on stock we have at any given time. > > > > Putting a commercial spin on what we do we can usually come up with a cost > > effective solution for products in fairly low production numbers. I won't > > put exact numbers on it as I'm sure someone will disagree about what is > > considered cost effective but we commonly provide custom solutions for year > > product volumes of 10-25 units. By the time we hit 100 off batches we aren't > > China style prices but we can definately give good value in the European and > > N America context. > > > > John Adair > > Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development > > Board. > > http://www.enterpoint.co.uk > > > > > > "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message > > news:npe7b21ppkddj74csrgr02pvjcbcu36b7l@4ax.com... > > > On Tue, 11 Jul 2006 15:38:53 +0100, John Adair wrote: > > > > > > [...] > > >> One of our intentions is that these modules could be used to bring > > >>high technology to what are relatively low technology host boards > > > > > > This is a truly excellent idea. For some while I've been frustrated > > > by FPGA development boards that have a ragbag of low-tech > > > functionality and connectors, pushing up the price just for me > > > to get something I could easily provide for myself. What you're > > > offering fixes that - for many users, even in small-scale production, > > > the FPGA is the only part of the system that needs fine-line > > > PCBs and non-trivial assembly techniques, and a small FPGA-only > > > plug-in module is the right answer. > > > > > > My only concern would be that you've gone for a fairly high-end > > > FPGA so the entry cost is quite high. Fine for some purposes, > > > but pricing itself out of a potentially useful market for others. > > > Have you any plans for a significantly lower-cost product with > > > a similar overall approach? > > > > > > Thanks > > > -- > > > Jonathan Bromley, Consultant > > > > > > DOULOS - Developing Design Know-how > > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > > jonathan.bromley@MYCOMPANY.com > > > http://www.MYCOMPANY.com > > > > > > The contents of this message may contain personal views which > > > are not the views of Doulos Ltd., unless specifically stated.Article: 105011
hi,
I did it in the same way what you have told, synthesis is going well
but while implementing design i stucked up at following errors:
ERROR:NgdBuild:809 - output pad net 'k<9>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<27>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<9>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<9>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<21>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<25>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<26>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<20>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<21>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<21>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<8>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<8>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<26>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<26>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<7>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<7>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<19>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<20>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<20>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<18>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<25>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<25>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<24>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<19>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<19>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<23>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<22>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<22>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<24>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<24>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<11>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<11>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<18>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<18>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<22>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<16>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<16>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<23>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<23>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<6>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<6>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<10>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<10>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<15>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<15>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<17>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<17>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<5>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<5>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<17>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<7>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<14>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<14>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<4>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<4>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<11>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<6>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<13>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<13>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<10>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<5>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<16>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<4>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<8>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<15>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<3>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<12>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<12>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<0>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<2>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<2>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<2>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<13>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<3>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<3>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<14>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<1>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<1>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<1>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<31>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<12>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<31>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<31>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<30>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<30>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<30>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<0>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<0>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<29>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<29>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<29>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<28>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<28>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<28>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<27>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<27>' is driving non-buffer
ERROR: NGDBUILD failed
shall i add any user ports in my design? as of i know user ports are
necessary when iam accessing any ports outside the FPGA.
But iam just instantiating the component in my ip, so its a internal
logic.
can you suggest me?
/gary
Article: 105012MM wrote: > "PeteS" <PeterSmith1954@googlemail.com> wrote in message > news:1152639919.953010.283430@p79g2000cwp.googlegroups.com... > > > > A two layer PCB (as noted by the esteemed Bill) may be ok with careful > > layout. > > If you try to do a 2-layer PCB for high-speed ADC/DAC you are on your own > with zero support from manufacturer. The chip pinouts are designed in the > assumption of existence of GND and PWR planes. I don't beleive one can get > advertised performance of a high-speed ADC/DAC using a 2-layer board. One > will be lucky if it will function at all... > > > What resolution did you want to get? There are a number of solutions at > > reasonably high speeds up to 24 bits (although they aren't cheap; say > > $30 to $100s per unit depending on features, and that's in 1k qtys) > > There no ADCs on the market with more than 14 bits that can cover the > requested band of 450 MHz. If oversampling is a requirement then you won't > even find a 12 bit device that can do it. Perhaps 10, or 8 for sure, but not > better. > > > /Mikhail I wasn't referring to the 450MHz rate :) That was a 'wish'. I said 'reasonably high speeds' simply because the OP seems to be open to suggestions. That said, I haven't seen better than 10 bit resolution at 450 MHz (which, unless you are undersampling, implies almost 1GS/s rates). Cheers PeteSArticle: 105013
"gary" <rgarik@yahoo.com> wrote in message news:jJidnUgPCvSQgCnZnZ2dneKdnZydnZ2d@giganews.com... > hi, > I did it in the same way what you have told, synthesis is going well > but while implementing design i stucked up at following errors: > > ERROR:NgdBuild:455 - logical net 'slv_reg0<21>' has multiple driver(s): The multiple driver errors seem to say that you still have wrong assignments in your code, i.e. you have slv_reg0 on the left side of the equation in more than one place... I am not sure about other errors... Try to clean this one first... /MikhailArticle: 105014
Subroto Datta wrote: > The Unused Pin Option setting is in: Assignments > Settings->Device->Device & Pin Options->Unused Pins. Thanks Subroto. Do you know why this isn't the default? Regards, TommyArticle: 105015
"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1152620387.58731.0@iris.uk.clara.net... > Following our recent Swinyard1 (Virtex-4) release we are now looking at > the Swinyard2 module concept which will be based on a middle end Virtex-5 > (initial XC5VLX50 and others) that will be supported by our Broaddown > series of main development boards. Bearing in mind this a small module > what features would you like us to put on this module? > > and what did you all think of the general Swinyard concept? > > This is you chance to influence what we deliver to the marketplace so do > let > us know. Well, I would want a board that can mate with 0.1" drilled prototyping boards that I can build experimental circuits. I'd like to be able to connect a logic analyser with readily obtainable IDC cable instead of specialist probes. I'd like to be able to buy just the minimal FPGA board and buy plug-in modules for the features I choose. I'd like a board that can slot into racks for 100mm wide cards. See: http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm for a list of features and reasons for them. Your Swinyard module is fine but seems like it needs a specially designed PCB to mate with the solderless connector. That cuts out customers who don't want to get such boards made up.Article: 105016
The choice of unused pins driving low was used I believe to improve signal integrity. However I am not an expert in this area, but I do know that several customers have mentioned this to be a confusing choice. The default will change with future device families. - Subroto "Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:1152662388.749655.119990@m73g2000cwd.googlegroups.com... > Subroto Datta wrote: >> The Unused Pin Option setting is in: Assignments >> Settings->Device->Device & Pin Options->Unused Pins. > > Thanks Subroto. > > Do you know why this isn't the default? > > Regards, > Tommy >Article: 105017
John Adair wrote: > Following our recent Swinyard1 (Virtex-4) release we are now looking at the > Swinyard2 module concept which will be based on a middle end Virtex-5 > (initial XC5VLX50 and others) that will be supported by our Broaddown series > of main development boards. Bearing in mind this a small module what > features would you like us to put on this module? > > and what did you all think of the general Swinyard concept? > > This is you chance to influence what we deliver to the marketplace so do let > us know. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk I would concur with some of the other posters. What would be really nice is a selection of decent size Spartan / Virtex parts on a PGA board that could be plugged into a socket 370 or socket 478 ZIF. These boards should have plenty of bypass caps on them - and it would be nice if these boards had a platform flash on them - making them, in essence, very nice CPLD's. If done properly, you could even strap a standard heatsink/fan unit on top! There are companies out there that have BGA -> PGA adapters, but then you have the little trick of getting the BGA on the board - a non-trivial task at best. I would definitely be interested in a pre-fitted, tested, PGA module with a Spartan 3/3E or Virtex II/II Pro BGA mounted on it. An ideal board would have: 1) Standard, commercially available socket pattern for the PGA. 2) Onboard 3.3 -> <core voltage> regulator 3) Bypass capacitors 4) Platform flash 5) Optional DDR SDRAM pads (or even devices). These could be on a "wing" that extends out past the socket like the Macintosh G3/G4 processor modules. 6) Reasonably high capacity XIlinx or Altera FPGA. Actually, if you could just make a G3/G4 processor module with a Virtex II Pro, you might be able to use an old Macintosh AS a development board!Article: 105018
In case anyone's interested: I just installed ISE8.2, and that works fine with OpenSUSE 64bit. Sean Durkin wrote > Hi *, > > just installed ISE8.1 with SP3 on a 64bit Linux-machine running OpenSUSE > 10. Just thought I'd give it a try, even if it's not officially > supported by Xilinx and I haven't read any reports here on people > getting it to run successfully (BTW, ISE8.1 works fine on other machines > running OpenSUSE, but this is the first 64bit-machine I've tried). > > Anyhow, most of it seems to work fine. The system is detected correctly > as lin64, the GUI works, and the utilities for flow work all right > (meaning XST, ngdbuild, map and so on don't crash and seem to do what > they should). The only thing that does not work is par. Starts up all > right, it reads in the constraints and displays device utilization, but > then exits with a fatal error before it starts placing: > > "Starting Placer > FATAL_ERROR:PersonalityModule:baspmdlm.c:164:1.25 - dll library > <PlXil_Legal> does not exist. Process will terminate. > To resolve this error, please consult the Answers Database and other > online resources at http://support.xilinx.com. > If you need further assistance, please open a Webcase by clicking on the > "WebCase" link at http://support.xilinx.com" > > There's nothing on this on the support website. I've opened a web case, > but since OpenSUSE is not a supported platform, they probably won't be > able to help there. > > Has anyone else seen this? "Xil_Legal" strikes me as kind of an odd name > for a library. It doesn't exist anywhere in the installation > directories, but it's not there on other machines running OpenSUSE > either, and on those machines the tools work fine. > > Has anyone gotten this to work? > > cu, > SeanArticle: 105019
FYI: ISE8.1 SP3 works without problems on Fedora Core 5 64bit (P4 650 3.4GHz)Article: 105020
Have you looked at our main development board product range. Raggedstone1, Broaddown2, Broaddown4, Hollybush1 can support stripboard prototyping. Headers on there even have 3.3V and 0V. Hollybush1 goes better and even has 0.1 power header that is aligned on 0.1 inch with left and right headers (containing 115 I/O on 0.1 inch + power). The power header allows a user to set a power supply for 1.2-4.3V, 1Amp, by simply connecting a resistor and also has 5V available. 3.3V also available on left and right headers on Hollybush1. Not to totally forget MINI-CAN that has a 40x2 0.1 inch header with both 5V and 3.3V for add-ons. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:n2Xsg.97246$uP.31845@newsfe2-gui.ntli.net... > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > in message news:1152620387.58731.0@iris.uk.clara.net... >> Following our recent Swinyard1 (Virtex-4) release we are now looking at >> the Swinyard2 module concept which will be based on a middle end Virtex-5 >> (initial XC5VLX50 and others) that will be supported by our Broaddown >> series of main development boards. Bearing in mind this a small module >> what features would you like us to put on this module? >> >> and what did you all think of the general Swinyard concept? >> >> This is you chance to influence what we deliver to the marketplace so do >> let > us know. > > Well, I would want a board that can mate with 0.1" drilled prototyping > boards that I can build experimental circuits. I'd like to be able to > connect a logic analyser with readily obtainable IDC cable instead of > specialist probes. I'd like to be able to buy just the minimal FPGA board > and buy plug-in modules for the features I choose. I'd like a board that > can slot into racks for 100mm wide cards. > > See: > http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm > for a list of features and reasons for them. > > Your Swinyard module is fine but seems like it needs a specially designed > PCB to mate with the solderless connector. That cuts out customers who > don't want to get such boards made up. > > > > > > > >Article: 105021
I will see if can fit in a design to try this market out. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "radarman" <jshamlet@gmail.com> wrote in message news:1152673375.661631.188980@p79g2000cwp.googlegroups.com... > > John Adair wrote: >> Following our recent Swinyard1 (Virtex-4) release we are now looking at >> the >> Swinyard2 module concept which will be based on a middle end Virtex-5 >> (initial XC5VLX50 and others) that will be supported by our Broaddown >> series >> of main development boards. Bearing in mind this a small module what >> features would you like us to put on this module? >> >> and what did you all think of the general Swinyard concept? >> >> This is you chance to influence what we deliver to the marketplace so do >> let >> us know. >> >> John Adair >> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development >> Board. >> http://www.enterpoint.co.uk > > I would concur with some of the other posters. What would be really > nice is a selection of decent size Spartan / Virtex parts on a PGA > board that could be plugged into a socket 370 or socket 478 ZIF. These > boards should have plenty of bypass caps on them - and it would be nice > if these boards had a platform flash on them - making them, in essence, > very nice CPLD's. If done properly, you could even strap a standard > heatsink/fan unit on top! > > There are companies out there that have BGA -> PGA adapters, but then > you have the little trick of getting the BGA on the board - a > non-trivial task at best. I would definitely be interested in a > pre-fitted, tested, PGA module with a Spartan 3/3E or Virtex II/II Pro > BGA mounted on it. > > An ideal board would have: > > 1) Standard, commercially available socket pattern for the PGA. > 2) Onboard 3.3 -> <core voltage> regulator > 3) Bypass capacitors > 4) Platform flash > 5) Optional DDR SDRAM pads (or even devices). These could be on a > "wing" that extends out past the socket like the Macintosh G3/G4 > processor modules. > 6) Reasonably high capacity XIlinx or Altera FPGA. > > Actually, if you could just make a G3/G4 processor module with a Virtex > II Pro, you might be able to use an old Macintosh AS a development > board! >Article: 105022
Use windows. Several of the Xilinx tools dont work on unix/linux anyway, so why bother ? Linux are shit compared to Windows when it comes to user friendlyness, so why bother ? Linux are for communists and "NERDS". "Rainer Buchty" <buchty@atbode100.lrr.in.tum.de> wrote in message news:e8vu3k$b59$1@news.lrz-muenchen.de... > Hello everyone, > > I recently got one of the HW-SPAR3E-SK eval boards and am trying to > get ISE/IMPACT under Linux to talk to it; I have ISE8.2 installed, > the actual Windriver compiled nicely and is also loaded: > > windrvr6 110208 0 > usbcore 68044 1 [windrvr6 usbserial usb-uhci ehci-hcd] > > Also /dev/windrvr6 exists: > > crw-rw-rw- 1 root root 254, 0 2006-07-11 11:15 /dev/windrvr6 > > However, IMPACT just doesn't see the board. Checking the syslog, I find the > following when plugging in the board's USB cable into the PC: > > Jul 11 12:18:02 kernel: usb.c: USB disconnect on device 00:1d.7-5 address 3 > Jul 11 12:18:04 kernel: hub.c: new USB device 00:1d.7-5, assigned address 4 > Jul 11 12:18:04 kernel: usb.c: USB device 4 (vend/prod 0x3fd/0xd) is not claimed by any active driver. > > What am I doing wrong? > > Kind regards, > RainerArticle: 105023
Hi Austin, Thanks for your reply, that's cleared up my question! Cheers, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:e90o4d$bt8@xco-news.xilinx.com... > Symon, > > The LVDS input buffer is a full CMOS differential comparator. You may > go within ~ 0.6 volts of either ground, or Vccaux, and it will still > meet speed spec. > > You may go all the way to the rails (and even a bit beyond -- see abs > max pin V specs), but then you take the diff stage out of its linear > region, and it gets a bit slower. > > Austin > > Symon wrote: >> Hi All, >> So, it looks like it's OK for me to use an unterminated LVDS input on an >> I/O >> bank with Vcco = 3.3V. I even checked that the tools don't complain! Does >> anyone know of any data for Vicm (the common mode range) for these >> inputs? >> If the receivers are powered by Vccaux, I assume the spec is the same as >> for >> LVDS_25, otherwise maybe the spec scales with Vcco. >> TIA, Syms. >> >>Article: 105024
hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some logic should wrap the memory, but i do not have idea how to implement. Does anyone point me to where i can find document or material or literature ? Thankyou
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