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In example RTCA DO-178B standard (Level A). Marco "Stephen Craven" <nevarcs@gmail.com> wrote in message news:1149514081.021714.128170@h76g2000cwa.googlegroups.com... > Marco, > > I'm afraid that I have no idea what the answer is, but I'm curious. > What makes an RTOS mil-qualified? Do you know which Mil Specs apply > here? > > Stephen > > > Marco T. wrote: >> Hallo, >> which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 >> FX)? >> >> Many Thanks >> Marco Toschi >Article: 103526
Pasacco wrote: > Hi > Thankyou Alfke and Nishioka for comments.... > I found the mapping error is not comming from "BRAM" but something else > trivial. Mapping error problem is now solved. > > "Read - Modify - Write" can not be done in one cycle for single port > memory. > But, in dual port, it is possible to "Load from port A - Data > processing - Store to port B" in one cycle, as far as different address > is accesed by port A and B. (Hopefully) it is correct. I do not think so. You said " in one clock cycle". You cannot read something on one cock edge, process the result, and write it back on the same clock edge. You have to use the next clock edge to write it back, but you can offset the other port address, so that you write the result back into the original location. That may be what you are thinking, and it effectively performs read-modify-write on every clock cycle. It's really a form of pipelining. Peter Alfke, Xilinx Applications.Article: 103527
Hi,everyone
i want to use the Xilinx DDC core version1.0, so i must simulate
it by modelsim,but i found the result of RDY,DOUT_I,DOUT_Q is zero, RFD
is '1', i have tried many many times to change my parameters, but it's
no effect.
i wish your help !
Thank you very much!
ARRON
Article: 103528On Mon, 5 Jun 2006 09:04:40 +0200, "Marco T." <marc@blabla.com> wrote: >which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 FX)? Take a llok at uCOS-II, at www.micrium.com This RTOS is certifiable for (or so they say): RTCA DO-178B EUROCAE ED-12B FDA-510(k) IEC-61058 I suppose one of them should fit your needs. Best regards, zaraArticle: 103529
nezhate wrote: > hi all, few days a go I updated my ISE8, now I have ISE Foundation > 8.03i and the problem is when I want to perform a multi place an route, > it falls and I get an error : "Process "Place & Route" failed" > > as a simple solution, I performed a simple place and route, after if my > constraints are not met, I change the cost table manually. my question > is : is it a bug in the service pack 3? also, > Is there another way to this automaically ? thanks in advance. Nezhate I normally use my own script for MPPR. The script "run_mppr" that I use is available at http://home.comcast.net/~jimwu88/tools/ under "Makefiles for running ISE command line tools". HTH, JimArticle: 103530
Yes exactly.
My goal is to have array C={1,2,3,4,5,6,7,8,9,10}, given two arrays
X={1,3,5,7,9} and Y={2,4,6,8,10} in less than 15 cycles.
I tried to do that in pipelined way (with single cycle throughput per
element). I managed "address" asynchronously and could have 12 cycles
in behaviral simulation. But implemented design is quite unstable.
At this moment, what I could do was 22 cycles (with 2 cycles throughput
per element).
Anyway my wish is to have
cycle 1 : load x=1
cycle 2 : load y=2
cycle 3 : compare, store x=1, load x=3
cycle 4 : compare, store y=2, load y=4
cycle 5 : compare, store x=3, load x=5
cycle 6 : compare, store y=4, load y=6
cycle 7 : compare, store x=5, load x=7
cycle 8 : compare, store y=6, load y=8
cycle 9 : compare, store x=7, load x=9
cycle 10 : compare, store y=8, load y=10
cycle 11 : compare, store x=9
cycle 12 : compare, store y=10
I concluded (at this moment) that this is not possible :) Thankyou
anyway.
Article: 103531Marco T. wrote: (top posting fixed) >> >>>Hallo, >>>which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 >>>FX)? >>> >>>Many Thanks >>>Marco Toschi >> >>Marco, >> >>I'm afraid that I have no idea what the answer is, but I'm curious. >>What makes an RTOS mil-qualified? Do you know which Mil Specs apply >>here? >> >>Stephen >> >> >>Marco T. wrote: > > > In example RTCA DO-178B standard (Level A). > > Marco > > > "Stephen Craven" <nevarcs@gmail.com> wrote in message > news:1149514081.021714.128170@h76g2000cwa.googlegroups.com... > DO-178B isn't a MIL standard (I used to know the applicable MIL-STD-XXXX, thank goodness I've forgotten!). The other answer about Micro-C/OS-II is correct. There are also commercial OS's that are qualified, but I don't know which ones, or if any of them go to Level A. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 103532
Marco, my advice is to design synchronously, use only the rising edges of a common clock, and do not worry about picosecond delays. (you mentioned 4 actions within 0.2 ns, hard to believe...) Peter Alfke ======== Marco wrote: > I have no processes working on the falling_edge, just one and working > on the rising_edge. I have found that on the simulation of the > behavioural model concurrent assignaments done outside the process are > done on falling_edges, while during the post-palece-and-route > simulation those updates appear on the rising_edge as I expect, any > ideas? > I can also the small delay of each line of a vector being updated > inside the process: if my vector value moves from 0 to 240, I see it > changing in the sequence 0 -> 16 -> 48 -> 176 -> 240 (start to end > within 0.2ns). I made some experiment changing the placement of the > otput pads of those vector bits (putting one for each bank instead of > all in one bank) and I found the total time required to change from 0 > to 240 to become 0.2ns, with a new sequence 0 -> 64 -> 80 -> 112 -> > 240. > As this is my first approach to real vhdl programming I'd like to hear > from you if what I see is correct or, at least, comprehensible. > Thanks, > MarcoArticle: 103533
Dave Have a look at this module http://www.enterpoint.co.uk/moelbryn/modules/usb_ps2.html in conjunction with our Raggedstone1 product. Basically the module is a voltage limiter(bus switch) on the USB lines leaving the logic to be implemented in the FPGA. -- John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Board. http://www.enterpoint.co.uk "Dave Farrance" <DaveFarrance@OMiTTHiSyahooANDTHiS.co.uk> wrote in message news:29t2821lqgte6hui7j4vqsjs3qgid4d212@4ax.com... > Hi. I want to get my brain around USB interfaces, how to design the > hardware and the software, and eventually to find what economic > hardware solutions are available, and how USB hardware interfaces can > be arranged to make the best use of generic USB drivers to minimise > problems associated with driver installation. > > It's not something that I've been able to investigate in the > time-limited projects that I've done as an electronic designer, and so > I've tended to use RS485 interfaces or other alternatives. I've decided > that It's high time that I understood USB, so I'll pick up the > knowledge by occasionally dabbling with it at home over a period of a > few months which is something that works OK for me. > > I'm not very good at reading screeds of technical description and > retaining it in my memory, so I need to get my hands dirty with some > experimental design and coding that I can interact with to get the > concepts anchored in my mind. I'm reasonably competent in C, C++, VHDL > and Verilog, and can code quite swiftly. > > To kick off, I'd like to get an FPGA board with a RAM-based FPGA that > can be configured via a serial or USB cable to a laptop. For my > experiments, the board also needs a USB interface that passes the raw > USB data stream directly to the FPGA, or it should be easily > convertible to do so. The FPGA needs to be big enough to hold > open-source HDL USB interfaces and to hold models that mimic the > interfaces to common USB equipment like flash keys, printers and > modems. Any suggestions? I'm aiming to keep the cost reasonable - $100 > to $150 say - and I'm prepared to put up with the limitations of free > software such as the speed-crippled Modelsim HDL simulator. > > -- > Dave FarranceArticle: 103534
I don't know exactly when this happened, but webpack will no longer fit on a single CD. I seem to recall when they split the download into multiple files so that they could be loaded in pieces over a phone line. Now the size means you have to have a DVD burner to carry it from one machine to the other. Any chance webpack can be provided in two hunks each of which will fit on a CD?Article: 103535
rickman <spamgoeshere4@yahoo.com> wrote: >I don't know exactly when this happened, but webpack will no longer fit >on a single CD. I seem to recall when they split the download into >multiple files so that they could be loaded in pieces over a phone >line. Now the size means you have to have a DVD burner to carry it >from one machine to the other. >Any chance webpack can be provided in two hunks each of which will fit >on a CD? Try "bzip2 -9z", it will compress most things to the limit.Article: 103536
Thank you for pointing this out. Notes 2-4 on VIN in Table 31 actually refer to the Notes 2-4 on VIN in Table 27. We will address this in the next update to the data sheet. <pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote in message news:44821e09$0$490$cc7c7865@news.luth.se... > In the Sp3 full datasheet p56/206 there's some notes numbered (3) and (4). > They are not to be found below table 31. Is this supposed to be that way? > > http://direct.xilinx.com/bvdocs/publications/ds099.pdf >Article: 103537
At the end of a successful synthesis (according to XST), I keep getting this warning: WARNING:ProjectMgmt - "C:/<full_path_to_project_directory/<project_name>.ngr" line 0 duplicate design unit: 'Module|<name_of_top_level_module>' I am not 100% sure what it means and how to eliminate this warning. Should it be a source of serious concern? Has anyone seen this kind of warning message before? Any help will be greatly appreciated. Best Regards, Marco.Article: 103538
marco wrote: > At the end of a successful synthesis (according to XST), I keep getting > this warning: > > WARNING:ProjectMgmt - > "C:/<full_path_to_project_directory/<project_name>.ngr" line 0 > duplicate design unit: 'Module|<name_of_top_level_module>' > > I am not 100% sure what it means and how to eliminate this warning. > Should it be a source of serious concern? > Has anyone seen this kind of warning message before? > > Any help will be greatly appreciated. > Best Regards, > Marco. Marco, I've seen this on every build of a design with COREgen modules and other .ngc design sources. The builds seem to run OK, so I guess the warning is not important. I would guess that there is a compatibility issue with .ngc files in 8.1, either with modules built from older tools or within 8.1, I'm not sure which. I've long ago given up on getting rid of all the warnings in ISE. There are some that you can't do anything about anyway, and I think this is one of them. There isn't any real information about the ProjectMgmt warnings on the Xilinx website. They are not numbered like the other warning types, so I'd guess that Xilinx isn't planning to add more info either. I would hope they go away on their own in a future release. By the way I'm also still using ISE 6.1i SP3 for any design that is still supported by those tools and I'm very happy with it. My initial reason for using 8.1i was a design that was too large when compiled in 6.1 XST but got about 40% smaller (LUTs) under 8.1 XST. Someday soon I may need 8.1i because of device support as well. I wish Xilinx (and other tool vendors) would stop mucking around with the user interface and just add the required fixes and updates to improve the tools for new device support and better fitting. The 8.1i editor is terrible. Sorry to rant, GaborArticle: 103539
Hi all, I have to admit I have never used the floorplanner before for anything useful. I am looking at a partially routed V4FX60 design. I want to swap the 2 PPC instances but can't figure out how it can be done. The manual doesn't seem to mention how to do unplace or unallocate. I tried deleting but it wouldn't delete either....No matter what I do the inctances don't move :( Thanks, /MikhailArticle: 103540
Alex, I was wondering if you made anymore progress with the PCI Express DMA problem. I have a similar problem but it is concerning bursting of data from the host to the Endpoint. My Windows Driver sets up a buffer of data to be sent to the endpoint and initiates a block transfer. The chipset, however, breaks this block into multiple single DW transfers effectively killing performance. I believe that allowing the Endpoint to become the bus master and initiate block transfers by reading from the allocated buffer on the host will lead to better bus utilization. Do you have any ideas about this or any updates on your progress with DMA? Thanks --KevinArticle: 103541
On a sunny day (05 Jun 2006 18:46:40 GMT) it happened pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote in <44847c10$0$490$cc7c7865@news.luth.se>: >rickman <spamgoeshere4@yahoo.com> wrote: >>I don't know exactly when this happened, but webpack will no longer fit >>on a single CD. I seem to recall when they split the download into >>multiple files so that they could be loaded in pieces over a phone >>line. Now the size means you have to have a DVD burner to carry it >>from one machine to the other. > >>Any chance webpack can be provided in two hunks each of which will fit >>on a CD? > >Try "bzip2 -9z", it will compress most things to the limit. Or you could just binary split the file [use 2 CDs], dunno about MS windows, but in Linux in the CD age I used dd, and cat on the other side. There is a similar command even for MSDOS. In Linux, create 2 images: dd if=myfile bs=1000000 count=700 of=part1 dd if=myfile bs=1000000 skip=700 of=part2 Then burn part1 and part2 as image: Insert empty CD1 growisofs -Z /dev/cd=part1 Insert empty CD2 growisofs -Z /dev/cd=part2 To restore: Insert CD1 cat /dev/cd > myfile Insert CD2 cat /dev/cd >> myfile Done whole movies that way..Article: 103542
rickman schrieb: > Now the size means you have to have a DVD burner to carry it > from one machine to the other. Or a USB stick or network connection. Kolja SulimmaArticle: 103543
rickman wrote:
> I don't know exactly when this happened, but webpack will no longer fit
> on a single CD. I seem to recall when they split the download into
> multiple files so that they could be loaded in pieces over a phone
> line. Now the size means you have to have a DVD burner to carry it
> from one machine to the other.
>
> Any chance webpack can be provided in two hunks each of which will fit
> on a CD?
I wrote a binary file splitor/combinor in Perl a while back. It's
available at
http://home.comcast.net/~jimwu88/tools/
You can split the file to any size you want.
HTH,
Jim
Article: 103544>>Try "bzip2 -9z", it will compress most things to the limit. >Or you could just binary split the file [use 2 CDs], dunno about MS windows, >but in Linux in the CD age I used dd, and cat on the other side. >There is a similar command even for MSDOS. >In Linux, create 2 images: >dd if=myfile bs=1000000 count=700 of=part1 >dd if=myfile bs=1000000 skip=700 of=part2 There's even simpler command for that :p split -b 640m myfile Should split myfile in 640 Mbyte chunks.Article: 103545
On Sat, 03 Jun 2006 23:10:39 +0200, Roland wrote: > Rich Grise wrote: > <snip> > >> What should I do? I've looked on the Xilinx site, in their "answers database", >> and I've searched both groups by google, and haven't seen anything addressing >> this particular situation. > > Are you by any chance missing a ModelSim installation? If you want to > simulate your design, you must install the appropriate version of > ModelSim because (AFAIK) Xilinx ISE relies on the ModelSim for all > simulations, including the "Generate Expected Simulation Results". > > Hope this helps, ignore if the problem is more complex. ;) > It helped indeed, but maybe not for the reason you've said. When I read your answer, I had a "D'oh!" moment - of course, the simulator has to be there! So, steeling myself to a day of downloading and installing, I uninstalled ISE 7.1, and did a webinstall of 8.1 and snagged the free Modelsim, and I'm up and running and all that. :-) Now, I have to do homework, although I've also read a post where someone has installed the RedHat verson on Fedora (which I thought was an offshoot of RH), but I've got Slackware. Slackware has "rpm", a redhat package manager, but when I look at the D/L, it's an 8 mb shell script???!!?? Should I trust that? (the point being that I wouldn't have to boot back and forth so much.) Thanks! RichArticle: 103546
Brandon Jasionowski wrote: > Under MAP or PAR properties (right click) change the "Starting Placer > Cost Table (1-100)" > > You could also try enabling Multi Pass PAR... Multi Pass PAR has problems in several versions of the tools. Another option is using command-line and the -t option. par ... -t n ... where n is the seed. Then you can have your own multi-pass batch file that works the same as single pass. > > -Brandon > > the.gaffar@googlemail.com wrote: > > Hi, > > > > I would like to know if there is a away to change the random seed used > > by the Xilinx tools ? > > > > I would like to do this in order to compare the results of multiple > > place and routes. > > > > > > Regards > > > > AltafArticle: 103547
Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > Hi, > > For the first time, I'm working with differential clock inputs on the > FPGA and I'd like to know how to properly constrain them. > > Currently what I put in my ucf is (for a clkin clock with a 200 MHz > frequency) : > > TIMESPEC "TS_clkin" = PERIOD "clkin" 200 MHz HIGH 50%; > > NET "clkin_p" TNM_NET = "clkin"; > NET "clkin_n" TNM_NET = "clkin"; > > > Is this correct ? Or should I define two timespec with an offset of > half a period, or just constraint the clkin_p ? > Just constrain the clkin_p. The differential receiver acts like a single input. > > I also have two others questions : > > * How to specify a maximum skew between multiple signals and also an > offset in/out compared to a clk output. (i/e I output a clock using DDR > FF and I want the related signals to be for example 1 to 2 ns after > that clock). > > * Finally, in my ucf I put lines like > > NET "leds<*>" IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=24; > > but I get *tons* of warning about putting the IOSTANDARD and SLEW and > DRIVE attribute on the "wrong type of object". What's the problem here > ? > Usually this means that the tools did not interpret these nets to be the IO Pad net. Perhaps they are generated internally in a slice and then routed to an output buffer, where the tools have a different internal name for the pad net like leds<1>_IOBUF or something similar. If these are outputs from your top level module, make sure that you tell the synthesizer to add IO buffers when you synthesize. > > Thanks, > > SylvainArticle: 103548
I think you can do it.
But please think of it in hardware terms. Change LOAD to READ, and
STORE to WRITE.
Then describe the inputs available before each clock edge, and the
outputs after the clock edge. And describe what COMPARE means (what are
you comparing with what, what's the output of the comparison is it just
a subtraction?)
In other words, put yourself into the "shoes" of the BRAM, and describe
what you are doing during each clock cycle...
Peter Alfke
============================
Pasacco wrote:
> Yes exactly.
> My goal is to have array C={1,2,3,4,5,6,7,8,9,10}, given two arrays
> X={1,3,5,7,9} and Y={2,4,6,8,10} in less than 15 cycles.
> I tried to do that in pipelined way (with single cycle throughput per
> element). I managed "address" asynchronously and could have 12 cycles
> in behaviral simulation. But implemented design is quite unstable.
> At this moment, what I could do was 22 cycles (with 2 cycles throughput
> per element).
> Anyway my wish is to have
>
> cycle 1 : load x=1
> cycle 2 : load y=2
> cycle 3 : compare, store x=1, load x=3
> cycle 4 : compare, store y=2, load y=4
> cycle 5 : compare, store x=3, load x=5
> cycle 6 : compare, store y=4, load y=6
> cycle 7 : compare, store x=5, load x=7
> cycle 8 : compare, store y=6, load y=8
> cycle 9 : compare, store x=7, load x=9
> cycle 10 : compare, store y=8, load y=10
> cycle 11 : compare, store x=9
> cycle 12 : compare, store y=10
>
> I concluded (at this moment) that this is not possible :) Thankyou
> anyway.
Article: 103549
Ok, so I'm working with a COTs DSP board vendor's ISE project and
customizing the logic (essentially tossing code in a user wrapper).
Unfortunately, I'm having some 'user-friendly' issues with the project
file and customizability.
Here is a snippet of what I sent to their engineer:
<SNIP>
----------------------------------------------------------------------
Constraint | Requested | Actual
| |
----------------------------------------------------------------------
* TS_clk_fx = PERIOD TIMEGRP "clk_fx" TS_sy | 0.000ns | -0.821ns
s_clk_in * 1.33333 HIGH 50% HOLD ERROR | |
----------------------------------------------------------------------
* TS_clk_fx = PERIOD TIMEGRP "clk_fx" TS_sy | 6.696ns | 20161.65ns
s_clk_in * 1.33333 HIGH 50% | |
----------------------------------------------------------------------
* TS_sys_clk_in = PERIOD TIMEGRP "sys_clk_i | 8.928ns | 20.255ns
n" 112 MHz HIGH 50% | |
This is the PAR result from the baseline project I got off the web. I
assume this project is built to operate with the 250 MHz A/Ds. Here are
my assumptions:
1) The 'sys_clk_in' is over-constrained to 112 MHz (100 MHz actual)
2) The 'clk_fx' derived from the fx port of the DCM is constrained to
1.333*sys_clk_in (125 MHz = 250 MHz/2 actual)
</SNIP>
-Notes:
1) 'sys_clk_in' is a board clock at 100 MHz (constrained to 112 MHz)
2) 'sys_clk' is derived from 'sys_clk_in' via DCM's fx output at 4/3.
'sys_clk' needs to operate at 125 MHz (constrained to ~150 MHz).
-His response:
<SNIP>"You're right. The Xilinx tool has a bug. Something about
spinning up a clock using a DCM & subsequent timing analysis. The
hardware does work."</SNIP>
-My questions to those experienced:
I've seen clock's overconstrained before with another vendor.
1) Is this a common practice? If so, I could envision timing results
being highly overconstrained when dealing with DCMs.
2) Is this really a bug or is the project misconstrained?
3) Am I crazy to think it's unreasonable to be given a
'user-defineable' project with timing that is seemingly failing by
default? (i.e. how am I to modify the project and know it will work if
the baseline does not meet timing?)
Thanks,
-Brandon
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