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Hi Wong, n*log2(n) is the number of comparison operations that must be done with a comparison sorting algorithm. It must have some overhead to do a loop and to swap two compared data into place. That is the reason why the formula has a 14.5 coefficient. Weng Oliver Wong wrote: > "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message > news:1152158287.898968.14220@l70g2000cwa.googlegroups.com... > > Hi, > > Can I find a website that lists the time for sorting 1 million > > 64-bit/32-bit random data using the fastest software sorting algorithm > > in a PC? > > Here's a ballpark figure: > > Let n = 1000000 > > n*log2(n) / 3Ghz = 6.64385619 milliseconds > > - OliverArticle: 104826
MM wrote: > Hi all, > > I was wondering which PC upgrades can make ISE to run faster? For example, > can it take advantage of dual CPU, and/or dual-core Xeon, etc.? I am > currently running at 2.6 GHz P4 with HT, 2GB 400MHz RAM, 800FSB and it is > too slow... > > > Thanks, > /Mikhail Toms HW recently did a review on the DualCore D805 (around $150 or less) which can be highly overclockable from 2.6Ghz with stock fan to 3.6Ghz with Zalman cooler and even 4.1GHz with water cooling which was then able to beat out the >$1K Extreme edition 965 and the AMD Athlon 64 FX-60 on gaming benchmarks. That article lead to a good run of sales for that chip. http://www.tomshardware.com/2006/05/10/dual_41_ghz_cores/ http://www.tomshardware.com/2006/06/12/your_diy_gaming_rig_for_720/ Intel locked out cpu overclocking, but left in FSB modding. Nominal power is 90W, but at 4.1GHz it went to 200W, takes some nerve to try that. I got mine with a free Intel mobo with no Bios level FSB tampering but I believe some Windows tools can still change the FSB setting. The article suggest several boards with specific D805 serial versions. I was in too much of a hurry to really bother, but I might try out the 3.6Ghz mod later on a better board. The stock fan was very quite except for occasional spin ups. John JaksonArticle: 104827
Peter Alfke wrote: <Snip>> We can model that by (conceptually or really) driving the input of the > double-inverter to an input voltage that is identical with the output > voltage, which means both inverters are in their linear range. Any > two-stage (non-hysteresis) non-inverting amplifier has such an > operating point where Vin = Vout. > To go metastable, we have to hit > exactly (or almost exactly) that point. > Now we activate the pass transistor that connects Vout to Vin. Nothing > happens momentarily, since, by definition, there is no voltage > difference. > But very soon a voltage difference will develop and will drive the > output either to the positive or the negative rail. > The debate in this thread has been whether that recovery from > metastability is monotonic, or can involve oscillation. I claim it is > monotonic since the phase response of the circuit loop is dominated by > the RC of pass transitor impedance times input capacitance. > Perhaps somebody with a more recent education can take it from here. Yes: I would call it 'behavioural monotonic'. Parasitic ringing and coupling effects may add to this, but it will not oscillate in the classic sense. The biggest disturbance source is likely to be the capacitance of the pass switch, as the IP signal has to be changing at the clock instant, in order to hit the metastable jackpot. -jgArticle: 104828
Hope the excerpt below from page 39 of Spartan3 datasheet DS099 v2.1 (http://www.xilinx.com/bvdocs/publications/ds099.pdf) answers your question: Eight Global Clock Multiplexers (also called BUFGMUX elements) are provided that accept signals from Global Clock inputs and route them to the internal clock network as well as DCMs. HTH, Jim http://home.comcast.net/~jimwu88/tools/ James Morrison wrote: > Hello everyone, > > I have a question that I'm having a difficult time confirming from the > datasheets, app notes, answer database,.... > > Can a BUFGMUX drive a global clock directly in the Spartan-3? I know > that you can drive the input of a DCM from the output of a BUFGMUX and > then drive the global clock from there. But can I do this without the > DCM? And I don't want to go through the logic fabric :) > > >From the Spartan-3 datasheet (Figure 18) the BUFGMUX can drive the Top > or Bottom Spines. I think that can then get on the horizontal spine and > then drive one of the global clocks. But I can't find any text to > confirm that. > > Cheers, > > James.Article: 104829
"rickman" <spamgoeshere4@yahoo.com> wrote: >> Put this into a Spice pgm, and try it. > >Two reasons why I can't... 1) I don't have Spice 2) I don't have >"this". 1) Spice is free, written at U.C. Berkeley CAD. http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE/ There are paid versions, with fancy features, or encypted models support, or beter GUIs. If you do a lot of Spice work, one of the paid versions might be worth the cost. I've also heard good things about this version: http://ngspice.sourceforge.net/download.html I have not tried this version. Any feedback from users? 2) This is a fairly simple netlist with 5 or so transistors: take a half a hour to enter at most. -- Phil Hays (Xilinx, but speaking for himself)Article: 104830
Hi - On 6 Jul 2006 11:53:39 -0700, "Brian McFarland" <brian.mcf1985@gmail.com> wrote: >I've been messing around with my own sort of development board for an >Altera MAX 3064 because I have some downtime at work (I'm a coop) and >wanted to teach myself some PLD stuff. I wanted ot put a manual clock >button on it so I could just mess around with some simple designs to >get a feel for how to use HDL's and Quartus. I have some DIPs for >inputs and LEDs for outputs, everything run on 3.3V. But the I can't >manage to get the clock to pulse just once when I press the button. >Can anyone recomend a debouncing circuit to use for something l like >this? Jack Ganssle has written extensively about this. Here's a paper that summarizes his findings and design suggestions: http://www.ganssle.com/debouncing.pdf Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 104831
Weng Tianxiang wrote: > What I really want to know is that the following formula for best > sorting timing is correct (it is copied from Knuth's "Sorting and > Searching") and it is not too far away from the PC computer reality: > 14.5* N * (lg N). No, the formula is not correct. The formula does not have any units; therefore, the constant factor is meaningless and the formula cannot be correct. Also, it's not clear whether lg() is a natural logarithm (the usual symbol for that is ln()) or a base-2 logarithm or some other base. So that adds in a second unknown constant factor. Consider, for a moment, if you sort 1 million numbers, each 32 bits in size. Should I let N = 1 million? If so, then when I evaluate that formula, I get some number like 200324903, or about 200 million. But what does this number mean? Is it clock cycles? Microseconds? Memory fetches? Microjoules of electrical energy used to power the computer while it performs this computation? - LoganArticle: 104832
Bob Perlman wrote: > Hi - > > Jack Ganssle has written extensively about this. Here's a paper that > summarizes his findings and design suggestions: > > http://www.ganssle.com/debouncing.pdf On this general subject, does anyone know of a LOW PROFILE microswitch action ( SPCO / SPDT ) switch ? There are std microswitches, which tend to have a high profile, and couple of old ITT style snap switches, also ~10mm high, but nothing I have found is close to a tact button, with SPCO ? -jgArticle: 104833
In addition to the above replies, you can have a look at the following points. 1) When you say that you are using Memec board, then I assume that the board is already tested for the required frequency. So as such there might be no problem with resepct to the Board routing, SI and all. 2) As you are using OPB DDR Controller (which is a proven core), there is no issues from the controller side, unless we are giving wrong parameters to it. but as you are using the xbd file, that means we can rule out any issues in the ucf file, mhs file,.... . 3) Under this circumstances, the first opton I will try is to run the DDR controller at a low frequency. By low frequency I mean Actual Frequency /4 or /8. For this you have to change the parameters accordingly. If it still does not work, then see if there is dry soldering in the components (mostly Pull up/ Pull down registers and capacitors) in the DDR SDRAM path. Wish you all the best. Saumyajit Nico Coesel wrote: > David <simianfever@gmail.com> wrote: > > >Hi All, > > > >I'm trying to get a DDR controller fo r the Micron MT46V16M16TG-75 up and running on a Memec V2MB1000 dev board but not having much luck so far. > > > >I initially tried the Opencores ddr_sdr which seemed to be sending the correct signals to the RAM when I checked with a scope, but DQS was not being strobed during the read cycle and the controller was reading back the last value written - presumably because of the bus capacitance. After reading a few discussions I got the idea that my external clock might be skewed, but I was unsure of how to calculate the necessary phase shift as I have no idea how long the feedback trace is (the feedback and clock pins are right next to each other on the package however so I would imagine it would be pretty short). I tried various speculatory values for the phase shift to no avail. > > > >In the last couple of days I've been trying a similar thing in EDK 8.1 - I downloaded the XBD files for the board from Avnet and set up a simple memory test project using the OPB DDR controller. The test passes for the flash memory and then freezes when it gets to the DDR and returns neither a pass or a fail. I'm kinda stuck here and unsure what to try next - is it possible that there's a problem with the board? Any help you guys could give me would be much appreciated. > > > > What kind of memory speed are you trying to achieve? Maybe you should > try to use 100MHz first. Anyway, if the DDR memory is not responding, > you should look into the initialisation and alignment of the clock and > control signals. A logic analyzer (16 channels at 400MHz is enough) > will help a lot. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 104834
dear Aurash thank you for your helpful reply. It really solved my problem. regards MH Aurelian Lazarut wrote: > mh wrote: > > >hi > >how can i instantiate EDN core (exported from PlanAhead) in top level > >of a verilog design , while the core doesnot have any associated I/O > >buffers and gives same error in ISE mapping. > > > > > > > you can create a verilog wrapper, keeping the same ports, and > instantiate the wrapper in your top level verilog. This wrapper will be > empty and XST will cosider it a black box, but ngdbuild should pick up > your edif. > make sure you place the edif in the design directory. > Aurash > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324Article: 104835
HI, Weng Tianxiang schrieb: > What I really want to know is that the following formula for best > sorting timing is correct (it is copied from Knuth's "Sorting and > Searching") and it is not too far away from the PC computer reality: > 14.5* N * (lg N). > > There are about 20 algorithms, and I reall don't know what formula > should be selected as a representative for best software algorithm > running for 1 million random data. > > 14.5* N * (lg N) is likely the best one. Thats totaly wrong for 1 Mio 32-Bit integers. In a HW-group you should be aware of space time tradeoffs. A simple fpga with enough memory(4G) should need o(N) to sort that number just by storing in the adress of its value. Maybe you need to be be aware if you fold two numbers with the same value, this would increase your memory to a max of 120Gbit (30 bit counter value results in a memory 32x30) and should increase your runtime from o(N) to o(N)+1 for pipelined lookup. Knuth is applicable for real great numbers of N, but nowadays we should consider 1 mio numbers as small. bye ThomasdArticle: 104836
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:44ade255@clear.net.nz... > Bob Perlman wrote: >> Hi - Jack Ganssle has written extensively about this. Here's a paper >> that >> summarizes his findings and design suggestions: >> >> http://www.ganssle.com/debouncing.pdf > > On this general subject, does anyone know of a LOW PROFILE microswitch > action ( SPCO / SPDT ) switch ? > There are std microswitches, which tend to have a high profile, and > couple of old ITT style snap switches, also ~10mm high, but nothing I have > found is close to a tact button, with SPCO ? > > -jg > Here is an article in ECN about some Ultraminiature Mircroswitches from Tyco http://www.ecnmag.com/article/CA6339402.html?nid=2730&rid=1635558756 -- GregArticle: 104837
Gregory C. Read wrote: > "Jim Granville" <no.spam@designtools.co.nz> wrote in message > news:44ade255@clear.net.nz... > >>Bob Perlman wrote: >> >>>Hi - Jack Ganssle has written extensively about this. Here's a paper >>>that >>>summarizes his findings and design suggestions: >>> >>>http://www.ganssle.com/debouncing.pdf >> >> On this general subject, does anyone know of a LOW PROFILE microswitch >>action ( SPCO / SPDT ) switch ? >> There are std microswitches, which tend to have a high profile, and >>couple of old ITT style snap switches, also ~10mm high, but nothing I have >>found is close to a tact button, with SPCO ? >> >>-jg >> > > > Here is an article in ECN about some Ultraminiature Mircroswitches from Tyco > http://www.ecnmag.com/article/CA6339402.html?nid=2730&rid=1635558756 Thanks, yes, seen that. The microswitch market is industrial-legacy: what they call "Ultraminiature Mircroswitches" are around 12.7mm long - which is what the semiconductor sector would consider "quite large" :) -jgArticle: 104838
Hi Peter, Nico, Saumyajit, Thanks for your replies. I was initially trying to use 100 MHz and I've tried slowing the OPB bus down to 66MHz - which EDK says is as slow as the Micron chip will go - but it still freezes on the memory test. The solder joints look fine to me but I'm just a Masters student - not exactly an expert! I checked the initialisation and found that it wasn't waiting 200 cycles after setting the mode register the second time so I fixed that but it had no effect. I checked the precharge - the period met the specifications - 7.8us. I haven't been able to check the clock relative to the commands as I only have a 100MHz scope - I can see that the signals are going up and down in roughly the right places but the time resolution is pretty lousy - I'm working on getting access to a better logic analyser. While I was checking the UCF for the pin configurations I noticed that in the mapper report I was getting this: | data<0> | IOB | BIDIR | SSTL2_I | | | OUTDDR | | | | | | | | ENFF2 | when according to the readme I should be getting this: | data<0> | IOB | BIDIR | SSTL2_I | | | INFF1 | | | | | | | INFF2 | | | | | | | OUTDDR | | | | | | | ENFF2 What do I need to set to get it to use the INFFs? (They aren't being used on the input pins either) Thanks again, DavidArticle: 104839
Weng Tianxiang schrieb: > Hi Wong, > n*log2(n) is the number of comparison operations that must be done with > a comparison sorting algorithm. Forget about comaprisons on PC hardware. You are interested in the number of load/stores because these are a lot slower than comparisons. A typical comparison sort will have two loads and two store per comparison. Radix Sort with 11-bit digits requires three O(N) passes for a total of about 12M loads and 6M stores. If your cache is big enough you could also do only two passes using 16-bit digits. Kolja SulimmaArticle: 104840
Hi Peter, Nico, Saumyajit, Thanks for your replies. I was initially trying to use 100 MHz and I've tried slowing the OPB bus down to 66MHz - which EDK says is as slow as the Micron chip will go - but it still freezes on the memory test. The solder joints look fine to me but I'm just a Masters student - not exactly an expert! I checked the initialisation and found that it wasn't waiting 200 cycles after setting the mode register the second time so I fixed that but it had no effect. I checked the precharge - the period met the specifications - 7.8us. I haven't been able to check the clock relative to the commands as I only have a 100MHz scope - I can see that the signals are going up and down in roughly the right places but the time resolution is pretty lousy - I'm working on getting access to a better logic analyser. While I was checking the UCF for the pin configurations I noticed in the mapper report that the data line IOBs were only using the OUTDDR and ENFF2 registers, when according to the Readme they should also be using INFF1 and INFF2. None of the input IOBs were using any registers either. I'm pretty sure that I checked the map report back when I was using ISE 7.1 and the input registers were being used - has anything changed in 8.1? Is there a constraint I can set to force it to use the INFFs? Thanks again, DavidArticle: 104841
Weng Tianxiang wrote: > Hi, > What I really want to know is that the following formula for best > sorting timing is correct (it is copied from Knuth's "Sorting and > Searching") and it is not too far away from the PC computer reality: > 14.5* N * (lg N). > > There are about 20 algorithms, and I reall don't know what formula > should be selected as a representative for best software algorithm > running for 1 million random data. > > 14.5* N * (lg N) is likely the best one. If you're referring to the table I think you are, you're completely misinterpreting it. Knuth compares a number of different internal sort algorithms, and gives average and worst case timing formulas based on MIX assembler implementations of the algorithms. So you can at best, get estimates of the average and maximum runtimes for a MIX implementation. And then you need to define "best." The table shows a number of algorithms that have better time complexity than (14.5n*lg n), although they may impose requirements on the input data or require extra space. Do you define best as average or maximum run times, stable or not, using minimum memory or not...? As others pointed out, there are plenty of sorting algorithms which are not bound by the (n*lg n) canard, it's just that they tend not to be as useful as the old standby's. FWIW, for 32 or 64 bit integers, some extra memory (a bit more than double what you need to hold the data) and a high-order radix sort will trivially lead to O(N). Is that "best" in some scenario?Article: 104842
On a sunny day (Thu, 06 Jul 2006 18:32:23 -0700) it happened Phil Hays <Spampostmaster@comcast.net> wrote in <o6dra2d48e7e7hafrqpuve0umnck888ioh@4ax.com>: >"rickman" <spamgoeshere4@yahoo.com> wrote: > >>> Put this into a Spice pgm, and try it. >> >>Two reasons why I can't... 1) I don't have Spice 2) I don't have >>"this". > >1) Spice is free, written at U.C. Berkeley CAD. > >http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE/ This is a nice one: http://www.linear.com/designtools/softwareRegistration.jsp ltspice is free too. Also it has lots of linear regulators already modelled. Works in Linux wine too: wine scad3.exe And there are many examples in it.Article: 104843
I want to make a FPGA/CPLD test board to plug into a socket to test the connectivity of the socket. Does anyone know of a way to check that all of the gnds and powers are connected given that I want to power the test board from the socket. I need to connect an fpga pin to a GND pin (there is ten of them) so that if the connector pin is O/C it floats high but if it is connected to GND then it contributes to the GND plane and vice versa for VCC. I don't think it can be done without several op amps and I'll have to use some power pins properly but just thought I'd ask. ColinArticle: 104844
colin schrieb: > I want to make a FPGA/CPLD test board to plug into a socket to test the > connectivity of the socket. > > Does anyone know of a way to check that all of the gnds and powers are > connected given that I want to power the test board from the socket. I > need to connect an fpga pin to a GND pin (there is ten of them) so that > if the connector pin is O/C it floats high but if it is connected to > GND then it contributes to the GND plane and vice versa for VCC. > > I don't think it can be done without several op amps and I'll have to > use some power pins properly but just thought I'd ask. > > Colin Sure you can do this with single PLD! 1) take a 2.5V (or 3.3V if your socket has 5V) PLD with permanent protection diodes in the chip to both GND and VCCIO - the GND diodes should present in all devices but the VCC protection diodes may only be enabled after configuration, so you may need to check datasheets or make some experiments 2) connect a bypass capacitor and parallel zener diode (2.5 or 3.3V) to the PLD GND and VCC pins 3) connect GND pins from socket to regular PLD IOs and with week pullup to VCC (if that pullup can not be enabled in the PLD) 4) connect VCC pins from socket via series resistor to PLD IO pads, add weak pulldown if not possible to enable in PLD Thats it! The PLD power and GND should float somewhere between the socket GND and VCC but you should be able to test all you need if the PLD lacks the protection diodes to VCC rail you need to add those externally. Antti http://antti-brain.comArticle: 104845
"John_H" <johnhandwork@mail.com> wrote in message news:4Scrg.4982$Oh1.4730@news01.roc.ny... > > I've had no problem with Synplify inference for the last few years. The > memories easily imply up to 9 bits, up to 18 bits, or up to 36 bits in a > single BlockRAM. > Thanks John, that's useful to know! Syms.Article: 104846
Helloo,
Anyone who worked with MIG ddr controller please help me.
subint wrote:
> Hi,
> I am using the DDR controller(generated by MIG1.5) for the ddr
> MT46V32M16 -6 for the board V4MBlx60. I am getting the expected result
> in simulation with the hdl code generated by the MIG.But when i tried
> to simulate the post-par model of the code all interfaces to the ddr
> are driven with x.Any idea.
> thanks in advance
> subin
Article: 104847Peter Alfke wrote: > Here comes some basic stuff. Excuse me if you find it boring. > > Most metastable problems are cused by input set-up time violations on > classical edge-triggered flip-flops. Such flip-flops consist of a > master latch and a slave latch. > > When the clock is Low, the D input drives the master latch, which does > not have any feedback during that time. The slave latch is isolated > from the master, and retains the previous data through its slave-latch > feedback. > > When the clock is High, the master latch is isolated form the D input, > retaining data by means of its master-latch feedback. The slave latch > then has no feedback, but is directly driven by the output of the > master latch. > > Metastability occurs when the input data happened to change exactly to > a specific "bad" level, just at the moment when the clock rises. At > that moment the master latch is being decoupled from the D input, and > the master-latch feedback is being activated. That is the (only) moment > when a (rising-edge triggered) flip-flop can go metastable. Only the > master latch is responsible for metastability. > > To analyze the behavior, we look at the innards of the master latch: it > consists of two cascaded simple inverter stages, each with a p-channel > pull-up transistor and an n-challel pull-down transistor (nothing but > these four transistors with very short connections between them) plus a > clock-controlled pass transistor feeding the output back to the input. > That's all, none of all that TTL junk that caused those metastable > problems decades ago. > > What happens when the master latch exits the metastable state? > We can model that by (conceptually or really) driving the input of the > double-inverter to an input voltage that is identical with the output > voltage, which means both inverters are in their linear range. Any > two-stage (non-hysteresis) non-inverting amplifier has such an > operating point where Vin = Vout. To go metastable, we have to hit > exactly (or almost exactly) that point. > Now we activate the pass transistor that connects Vout to Vin. Nothing > happens momentarily, since, by definition, there is no voltage > difference. > But very soon a voltage difference will develop and will drive the > output either to the positive or the negative rail. AH! We have the first condition for chaotic behaviour, sensitivity to initial conditions... When the input is near the balance point, the slightest difference will determine whether the output goes positive or negative. That is a very significant aspect of the circuit. > The debate in this thread has been whether that recovery from > metastability is monotonic, or can involve oscillation. I claim it is > monotonic since the phase response of the circuit loop is dominated by > the RC of pass transitor impedance times input capacitance. > Perhaps somebody with a more recent education can take it from here. I think there is more to it than just oscillation. Chaotic behavior does not require the same things. Once the input to the inverter has varied just a bit the output will move in the opposite direction. But there is a delay (which is mostly from the RC it appears). If the input then moves (from noise or parasitic feedback or any other reason) in the opposite direction as its initial movement, the output will start to swing in the other direction. Now we have two larger amplitude swings at different times chasing each other around the loop. Given all the various parasitics and delays, I don't see why this could not create oscillation and possibly chaotic behavior. Obviously it doesn't, but I don't think we still know why as yet. > If the structure is any more complicated, involving additional > transistors or lengthy interconnects, all bets are off, and the circuit > may have poor metastable behavior. But we are not interested in such a > bad circuit.. I don't know what is so different about the TTL FF because no one has explained why it is soooo "bad".Article: 104848
Hi Kolja, I am talking about a real world measurements, not a theoretical one: 1. Input data are in random; 2. Input data are 32-bit or 64-bit; 3. Sorting must be stable; Radix sort cannot be applied to my case: how can you sort by 11-bit for a data set of 32-bits? You may imagine a set of data with same all lowest 11 bits, but different upper 21 bits? Now I have clearer idea on what I really want: As indicated by someone above, 14.5*N*(lg N) is for MIX referenced by Knuth and is not useful in getting real PC world computation. So now I want to know the coefficient in the following formula in real PC world to replace Knuth's calculation formula: Coefficiant * N * (lg N) for a real PC environment. PC running frequency and cache size are not my concern, because when a coefficient is given, a PC frequency and cache size may be appended to the result and everyone knows their relations. If a table of coefficient can be available based on frequency and cache size, it is convenient for everyone to get a taste on how fast a sorting algorithm is. Thank you. WengArticle: 104849
Logan Shaw schrieb: > No, the formula is not correct. The formula does not have any units; > therefore, the constant factor is meaningless and the formula cannot > be correct. Maybe you should google a bit after landau symbols and complexity theorie. In general complexity therorie constants are ignored, but for more detailed (or practical oriented) inspections they are still used. bye Thomas
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