Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thank you for your useful hints. The good news is, that I am running Linux in a virtual machine, and that I am able to chose whatever system is most compatible with the Xilinx tools. After trying this and that, I found that WebPACK installs on Debian 3.1r2 installs without too much problems. I seem to have a problem with windrv, I will need to investigate what the symptoms of this really are. Again, thank you for your useful hints and it seems that the solution to the windrv problem is already described as well. Best regards, Felix -- Dipl.-Ing. Felix Bertram http://www.bertram-family.com/felixArticle: 103501
Pasacco wrote: > -- Synchronous implementation > process(reset, clock) ... > WARNING:MapLib:701 - Signal clk connected to top level port clk has > been removed. > WARNING:MapLib:41 - All members of TNM group "clk" have been optimized > out of the design. Is "clock" connected to "clk" somewhere? You can't read-modify-write, but it should still map and not work correctly. Alan NishiokaArticle: 103502
Dave Farrance schrieb: > "Antti" <Antti.Lukats@xilant.com> wrote: > > >the USB chip on the Xilinx s3e starterboard is the same as on the > >opalkelly board I think, > >so just rewrite the usb eeprom and use the xilinx s3e board as usb > >devel board - only drawback > >you need to re-create that parts of the schematic that xilinx censored > >out from the digilent design > >eg the wiring of the usb controller - but with an beep-tester it should > >not take longer than a few hours > > Thanks for that. It would have to be the USB interface on the censored > page. Is the usb eeprom reprogrammable on-board? > > -- > Dave Farrance the usb micro is cypress fx2 so if you dont load xilinx usb drivers then you should be able to rewrite the eeprom using cypress tools AnttiArticle: 103503
"Antti" <Antti.Lukats@xilant.com> wrote: >the usb micro is cypress fx2 so if you dont load xilinx usb drivers >then you should be able to rewrite the eeprom using cypress tools Ah, I see. I've looked up the Cypress FX2 details, but I'm not interested in developing interfaces to a specific USB controller chip at the moment. I want to investigate the generic USB protocol hardware, and I'd put that on the FPGA itself. I'll use another USB port for that, and I'll put together a transceiver board to handle the signal-levels so that I can route the raw data stream directly to the FPGA I/O. Such a USB interface would be speed-limited, but I'm not worried about that. -- Dave FarranceArticle: 103504
In comp.arch.fpga Dave Farrance <DaveFarrance@omitthisyahooandthis.co.uk> wrote: > "Antti" <Antti.Lukats@xilant.com> wrote: > >the usb micro is cypress fx2 so if you dont load xilinx usb drivers > >then you should be able to rewrite the eeprom using cypress tools > Ah, I see. I've looked up the Cypress FX2 details, but I'm not > interested in developing interfaces to a specific USB controller chip > at the moment. I want to investigate the generic USB protocol hardware, > and I'd put that on the FPGA itself. > I'll use another USB port for that, and I'll put together a transceiver > board to handle the signal-levels so that I can route the raw data > stream directly to the FPGA I/O. Such a USB interface would be > speed-limited, but I'm not worried about that. The interface is not only speed limited, but also missing needed functionality, at least for USB2. USB+ and USB- need to be evaluated in many ways, not possible with a normal FPGA input. There are chips implementing the physical access (UTMI). -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 103505
mailmekaran wrote: > Dear all, I am implementing FLOATING point FIR filter with LATTICE > structure. > For this project i want 32bit Floating Point ADDER and > MULTIPLIER in VHDL. > Please tell me how and from where i can get the VHDL code for the > same. > THAKING YOU ALL. > > Shivkaran Ravidas > Why? Consider that the floating point add nas to denormalize one of the addends in order to be able to sum the two values. In other words, all the addends in the sum have to have the same weighting, which is indicated in floating point by the exponent. You gain very little by attempting to do the filter with floating point arithmetic, and what you do gain comes at a very high cost.Article: 103506
Hi,all: I want to use webcam to capture image data by using usb1.1. Is it difficult to do? I am a flashman on it and still have no idea to do this. Please tell me where can get these information. Thanks a lot!!!Article: 103507
On 1 Jun 2006 08:04:31 -0700, "Brandon" <killerhertz@gmail.com> wrote: >XST doesn't seem to mind that I'm driving two DCMs with a BUFG. Are >there any implications of this? I'm using the FX output on both DCMs, >one clock domain to capture digitized data, the other to process it >after a different rate after an asychronous FIFO. > I have driven three DCM's from the same BUFG, and foru DCM's from the same IBUF(G) witout problems, btoh in Spartan 2E and Spartan 3 Regards, ZaraArticle: 103508
Hello guys,
Is anyone used the Mig tool to generate a DDR SDRAM
controller here.i have some doubts on the code generated by mig.It
include a testbench inside it.I dont need such a interface and also i
want to use this as a sub block of the Full system fpga of the v4lx60
board.
i am confused with structure of the code.Is it possible to use this
code with out much modification such as not removing the testbench.
regards
subin
Article: 103509I have no processes working on the falling_edge, just one and working on the rising_edge. I have found that on the simulation of the behavioural model concurrent assignaments done outside the process are done on falling_edges, while during the post-palece-and-route simulation those updates appear on the rising_edge as I expect, any ideas? I can also the small delay of each line of a vector being updated inside the process: if my vector value moves from 0 to 240, I see it changing in the sequence 0 -> 16 -> 48 -> 176 -> 240 (start to end within 0.2ns). I made some experiment changing the placement of the otput pads of those vector bits (putting one for each bank instead of all in one bank) and I found the total time required to change from 0 to 240 to become 0.2ns, with a new sequence 0 -> 64 -> 80 -> 112 -> 240. As this is my first approach to real vhdl programming I'd like to hear from you if what I see is correct or, at least, comprehensible. Thanks, MarcoArticle: 103510
stijena wrote: > There is a (in the spec for cardbus) well documented method for extending the res delay, to get enough time for fpga initialisation. Read more detailled. One pin should be tied low, and one can hold recognition proces long enough. Thanks for the information.Could you please tell me how to obtain the spec for cardbus.Do I need PCMCIA membership for the same?Article: 103511
Hallo, which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 FX)? Many Thanks Marco ToschiArticle: 103512
Antti a écrit :
>>>the USB chip on the Xilinx s3e starterboard is the same as on the
>>>opalkelly board I think,
>>Thanks for that. It would have to be the USB interface on the censored
>>page. Is the usb eeprom reprogrammable on-board?
> the usb micro is cypress fx2
Are you 100% sure of that (the only FX2 they mention in the datasheet
is an extension connector) ?
If yes, how is the FIFO port of the FX2 connected to the FPGA ?
Goodbye,
Stéphane.
Article: 103513"Stéphane Goujet" <stephane.goujet@pp.invalid> schrieb im Newsbeitrag news:5RQgg.38$VW4.19@read3.inet.fi... > Antti a écrit : > >>>>the USB chip on the Xilinx s3e starterboard is the same as on the >>>>opalkelly board I think, >>>Thanks for that. It would have to be the USB interface on the censored >>>page. Is the usb eeprom reprogrammable on-board? >> the usb micro is cypress fx2 > > Are you 100% sure of that (the only FX2 they mention in the datasheet is > an extension connector) ? > If yes, how is the FIFO port of the FX2 connected to the FPGA ? > > Goodbye, > Stéphane. pretty sure, yes the datasheet refers to FX2 (as extension connector) but the board has on on-board embedded usb platfrom cable, and that includes the cypress FX2 usb micro this pages are left out from schematics and are covered up with ink on PCB prints AnttiArticle: 103514
Hello,
How to explain the difference of the following two cases? I thought
that case one should be better, but the readout data sometimes have big
jumps. It seems that case two can work better in my tests. Thanks!
CASE ONE:
-------------------------------------------
-- Read out data in FPGA to PC
read_proc:process(clk)
begin
if clk='1' and clk'event then
if read_EN = '1' then
case read_address is
when xxx => read_port <= "xxxxxxxx";
...
end case;
end if;
end if;
end process;
---------------------------------------
CASE TWO:
-------------------------------------------
-- Read out data in FPGA to PC
read_proc:process(clk, read_EN )
begin
if read_EN = '1' then
if clk='1' and clk'event then
case read_address is
when xxx => read_port <= "xxxxxxxx";
...
end case;
end if;
end if;
end process;
---------------------------------------
Note: read_EN is one clock period-long and generated in FPGA with 3
flip-flops with input being the read-flag from PC. I use Xilinx
xcv200e.
-Brian
Article: 103515
Antti Lukats a écrit :
>>>the usb micro is cypress fx2
>> Are you 100% sure of that (the only FX2 they mention in the datasheet is
>>an extension connector) ?
>> If yes, how is the FIFO port of the FX2 connected to the FPGA ?
> pretty sure, yes the datasheet refers to FX2 (as extension connector)
> but the board has on on-board embedded usb platfrom cable, and that includes
> the cypress FX2 usb micro
But perhaps just the pins to program the FPGA and the flash memory
are connected, and the USB port cannot be used to transfer personal data
through the FIFO of the FX2 microcontroller. It seems to be so, because
else they would probably mention that this board has a USB port that can
transfer high-speed USB data, and they do not. They just say that the
board can be programmed through USB.
> this pages are left out from schematics and are covered up with ink on PCB
> prints
Yes, I saw that... :-(
Goodbye,
Stéphane.
Article: 103516Hi, > I'll use another USB port for that, and I'll put together a transceiver > board to handle the signal-levels so that I can route the raw data > stream directly to the FPGA I/O. Such a USB interface would be > speed-limited, but I'm not worried about that. take a look here: http://shop.trenz-electronic.de/catalog/default.php?cPath=1 I think, the Spartan-3 Micromodule with USB UTMI Phy is exactly what you want. best regards Thorsten TrenzArticle: 103517
St=E9phane Goujet schrieb: > Antti Lukats a =E9crit : > > >>>the usb micro is cypress fx2 > >> Are you 100% sure of that (the only FX2 they mention in the datasheet= is > >>an extension connector) ? > >> If yes, how is the FIFO port of the FX2 connected to the FPGA ? > > pretty sure, yes the datasheet refers to FX2 (as extension connector) > > but the board has on on-board embedded usb platfrom cable, and that inc= ludes > > the cypress FX2 usb micro > > But perhaps just the pins to program the FPGA and the flash memory > are connected, and the USB port cannot be used to transfer personal data > through the FIFO of the FX2 microcontroller. It seems to be so, because > else they would probably mention that this board has a USB port that can > transfer high-speed USB data, and they do not. They just say that the > board can be programmed through USB. > > > this pages are left out from schematics and are covered up with ink on = PCB > > prints > > Yes, I saw that... :-( > > Goodbye, > St=E9phane. well they dont provide and user communication over the USB controller, but sure it would be possible, maybe not with the max transfer rate, but still possible AnttiArticle: 103518
St=E9phane Goujet schrieb: > Antti a =E9crit : > > >>>the USB chip on the Xilinx s3e starterboard is the same as on the > >>>opalkelly board I think, > >>Thanks for that. It would have to be the USB interface on the censored > >>page. Is the usb eeprom reprogrammable on-board? > > the usb micro is cypress fx2 > > Are you 100% sure of that (the only FX2 they mention in the datasheet > is an extension connector) ? > If yes, how is the FIFO port of the FX2 connected to the FPGA ? > > Goodbye, > St=E9phane. I did not say the FIFO port is connected - I said that the USB controller can be used for user defined protocols, also transferring user data AnttiArticle: 103519
Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >In comp.arch.fpga Dave Farrance <DaveFarrance@omitthisyahooandthis.co.uk> wrote: >> I'll use another USB port for that, and I'll put together a transceiver >> board to handle the signal-levels so that I can route the raw data >> stream directly to the FPGA I/O. Such a USB interface would be >> speed-limited, but I'm not worried about that. > >The interface is not only speed limited, but also missing needed >functionality, at least for USB2. USB+ and USB- need to be evaluated in many >ways, not possible with a normal FPGA input. There are chips implementing the >physical access (UTMI). Thanks. I see. If I built an transceiver board myself, it'd have to be for USB 1.1 with a basic transceiver chip such as the MAX3346E which I'd run at low speed. I have managed to solder 14-pin TSSOP packages to prototype boards in the past, although I'd rather find a DIP chip if I could. -- Dave FarranceArticle: 103520
Thorsten Trenz <nq@trenz-electronic.de> wrote: >Dave Farrance wrote: >> I'll use another USB port for that, and I'll put together a transceiver >> board to handle the signal-levels so that I can route the raw data >> stream directly to the FPGA I/O. Such a USB interface would be >> speed-limited, but I'm not worried about that. > >take a look here: >http://shop.trenz-electronic.de/catalog/default.php?cPath=1 > >I think, the Spartan-3 Micromodule with USB UTMI Phy is exactly what you >want. Ah yes. Thanks. That's the most promising so far. The Trendz TE-XC3S micromodule with TE-0143 carrier board and TE-0149 programmer comes to $173. I can live with a parallel-port programmer, although I rather have USB or serial-port programming. -- Dave FarranceArticle: 103521
Dave Farrance <DaveFarrance@OMiTTHiSyahooANDTHiS.co.uk> wrote: >Ah yes. Thanks. That's the most promising so far. The Trendz TE-XC3S >micromodule with TE-0143 carrier board and TE-0149 programmer comes to >$173. I can live with a parallel-port programmer, although I rather >have USB or serial-port programming. Whoops, I mangled your name, Herr Trenz. Sorry about that. -- Dave FarranceArticle: 103522
Hi Thankyou Alfke and Nishioka for comments.... I found the mapping error is not comming from "BRAM" but something else trivial. Mapping error problem is now solved. "Read - Modify - Write" can not be done in one cycle for single port memory. But, in dual port, it is possible to "Load from port A - Data processing - Store to port B" in one cycle, as far as different address is accesed by port A and B. (Hopefully) it is correct.Article: 103523
subint wrote: > Hello guys, > Is anyone used the Mig tool to generate a DDR SDRAM > controller here.i have some doubts on the code generated by mig.It > include a testbench inside it.I dont need such a interface and also i > want to use this as a sub block of the Full system fpga of the v4lx60 > board. > i am confused with structure of the code.Is it possible to use this > code with out much modification such as not removing the testbench. > regards > subin > I've been using the DDR2 interface from MIG 1.5, and the interface can be generated with or without the test bench. I just checked MIG, and it looks like you're right, it can only be generated with the testbench. In the DDR2 interface it was tedious but possible to 'unwire' the testbench and connect my own interface. The hierarchy of the DDR interface looks to be the same as the DDR2 interface, so I think that the job shouldn't be too difficult. As for doubts about the quality of the DDR code, you should do a thorough simulation. I have opened 4 or 5 webcases on the DDR2 MIG 1.4 and 1.5. --- Joe Samson Pixel VelocityArticle: 103524
Marco, I'm afraid that I have no idea what the answer is, but I'm curious. What makes an RTOS mil-qualified? Do you know which Mil Specs apply here? Stephen Marco T. wrote: > Hallo, > which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 FX)? > > Many Thanks > Marco Toschi
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z