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Kishore wrote:
> I personally feel that one can be very
> productive as in time with Verilog?
If that is a conviction rather than a question
why not get back to writing code?
> -> Are there things that VHDL does better than verilog
variables
> -> What is the most widely used language in the industry i.e. FPGA and
> ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
> VHDL?
totally?
I've been trolled.
I should really get back to writing code . . .
-- Mike Treseler
Article: 102951My suggestion is to confront the seller (distributor) and make him justify the price, considering package, speed, temperature. (Something you never mentioned in this newsgroup. Might have saved us all a lot of hot air). Also try to convince him that your 100,000 piece requirement is not just your wishful thinking. (Which he may suspect). Distributors are independent businesses, they have a lot of freedom to set their pricing... Peter AlfkeArticle: 102952
Peter Alfke wrote: > My suggestion is to confront the seller (distributor) and make him > justify the price, considering package, speed, temperature. > (Something you never mentioned in this newsgroup. Might have saved us > all a lot of hot air). > Also try to convince him that your 100,000 piece requirement is not > just your wishful thinking. (Which he may suspect). > Distributors are independent businesses, they have a lot of freedom to > set their pricing... > Peter Alfke And just where is the hot air Peter? Which "you" are you refering to?Article: 102953
On Tue, 23 May 2006 22:04:23 +0000, mk wrote:
> Here is my very simple research: go to monster.com and search for
> verilog and vhdl keywords. Here are the results:
>
> verilog (%) vhdl (%)
> overall 387 (55) 320 (45)
> 100 miles around 104 (78) 30 (22)
> zipcode 94087
>
> 94087 is zipcode of Sunnyvale, CA.
I did this for a smattering of different states a month ago and came up
with 60% Verilog vs 40% VHDL. We're pretty close.
The OP should google "verilog vs vhdl" for a lot of info.
~Dave~
Article: 102954"Hot air" is what I call all those references to the Law, "truth in advertizing" etc, before we even know the facts of this quotation... We still do not know. The distributor might have had a reason to effectively "no bid" this request for quote. I am always leary when somebody calls himself Anonymous, and the people in this newsgroup then respond as if they had to help a Damsell in Distress... Peter AlfkeArticle: 102955
Kishore wrote: > Hi, > > I know this has been brought up many times in various groups but > here is my view on them and I would really appreciate some > clarification. I started working on FPGA design and stuff some 3 months > back or so. All the time I was switching back and forth between verilog > and VHDL for various projects. I personally feel that one can be very > productive as in time with Verilog? I only use VHDL if there is no > choice but I am not aganist VHDL or anything. > > After some searching on google and various usenet groups I came > across many arguments regarding Verilog vs VHDL summarising either as > "use the right the tool for the right job" or "leading to language > wars". I am open-minded and I am biased to the former at the same time > a bit biased to verilog :) I just wanted to know some things. > > -> Are there things that VHDL does better than verilog or vice-versa > -> What is the most widely used language in the industry i.e. FPGA and > ASIC designs. I think VHDL is the dominant one as Xilinx totally uses > VHDL? > > All kinds of thoughts, experiences and constructive criticisms will > be helpful. > > cheers, > kishore. VHDL was often said to be used more in Europe, DOD, and in the schools and now perhaps in FPGAs too. I am always surprised to hear about Verilog use in schools or outside the US but I am biased to Verilog mostly because I use only a tiny fraction of the language anyway and come from the ASIC background. At one time Verilog had a bulls eye mark on it by the EDA industry. The US ASIC guys had chosen Verilog and liked it enough because it had cell library support and could be mixed with C tools via the PLI. Verilog had been proprietary but when taken over by Cadence, it was released as an open standard. Phil Moorby had gone to Cadence along with his language and for awhile the entire EDA industry was going against Verilog and pronounced it as dead. Even Cadence people could only say Verilog under their breadth as politically incorrect. The customers eventually won out and atleast in the US Verilog still dominates in ASICs. It also helped that Synopsys took on Verilog for synthesis and pushed it forward no end. VHDl though came in right behind. Trouble is as some will point out, ASIC starts are dying, FPGA designs are growing and the nature of design in both of these is quite different, huge teams v tiny teams, high risk v low risk. In olden times, Verilog had alot more useablity at a low level for gate and device level modeling, which nobody really does anymore since synthesis took over. VHDL always had advantages in higher level modelling. I think they overlapped by 70% but used different language constructs to say the same thing, Verilog generally used about half the key strokes. Nowadays in the ASIC world Verilog is getting replaced by SuperLog now known as SystemVerilog which borrowed/stole several of VHDLs language features. I do wish Verilog could abandon some of its old features though and get light again. Anyway the wars are really over, both the standards groups merged into one camp,. Officially both languages are merging in a way that neither could have predicted. Most EDA tools have 2 parsers in front end and a common language internal engine. Its more hassle to support this but it will go on for some time. John Jakson transputer guyArticle: 102956
Dear Friends, Please, I need help. I have met difficulty with reading data from and writing data to J3 Intel StrataFlash NOR Flash PROM on Spartan3E Starter Kit. I have followed the instructions which have been written in its datasheet but I still have met problems. I used the method =E2=80=9Conce read then write many times=E2=80=9D to Intel StrataFlash (SF) and its read/write controller program was multiplexed with LCD writing state program, like this following states: Power On =EF=83=A0 LCD Init =EF=83=A0 Read SF then loads its data to Binary Counter = input port =EF=83=A0 Writing first round characters to LCD =EF=83=A0 Writing Bina= ry Counter output data to SF =EF=83=A0 Writing second round characters to LCD =EF=83=A0 Writing Binary Counter output data to SF =EF=83=A0 Writing first = round characters to LCD =EF=83=A0 Writing Binary Counter output data to SF =EF=83= =A0 and so on. Hence, I hope the memory data was always be updated according to Binary Counter alteration. But, actually the data was not updated after I turned off then turned back on the Starter Kit. I also have added more delays onto read/write waiting states, but the data still was not updated. According to datasheet, data reading needs the times at least 75 ns after SF_CE0 signal goes =E2=80=98low=E2=80=99 or can be represented with 4= T clock 50 MHz then followed with SF_OE signal goes =E2=80=98low=E2=80=99. Valid da= ta will be emerged 25 ns after SF_OE signal goes =E2=80=98low=E2=80=99 or can be represented with 2T clock 50 MHz (40 ns). Also, data writing needs the times at least 60 ns =E2=80=98low=E2=80=99 SF_CE0 and SF_WE signals (or 3T = clock 50 MHz). I used 2 bytes 8-bit data to be kept onto memory. Data port was bidirectional, so I used IBUF8 =E2=80=93 OBUFT8 and T pin on OBUFT8 became = to the data traffic controller. Hence, I designed its reading states like this: SF_A0 <=3D =E2=80=980=E2=80=99; SF_CE <=3D =E2=80=980=E2=80=99; Tpin = <=3D =E2=80=981=E2=80=99; =EF=83=A0 wait 4T =EF=83=A0 SF_OE <=3D =E2=80=980=E2=80=99; =EF=83=A0 wait 2T =EF=83=A0 LOAD = <=3D =E2=80=981=E2=80=99; =EF=83=A0 LOAD <=3D =E2=80=980=E2=80=99; =EF=83=A0 SF_OE <=3D =E2=80=981=E2=80=99; SF_A0 <=3D = =E2=80=981=E2=80=99 =EF=83=A0 wait 2T =EF=83=A0 LOAD <=3D =E2=80=981=E2=80=99; =EF=83=A0 LOAD <=3D =E2=80=980=E2=80=99; =EF=83=A0 SF_= OE <=3D =E2=80=981=E2=80=99; SF_A0 <=3D =E2=80=980=E2=80=99; SF_CE <=3D =E2=80=981=E2=80=99; Tpin <=3D =E2=80=980=E2=80=99;. And I desig= ned its writing states like this (without changing Tpin bit): SF_A0 <=3D =E2=80=980=E2=80=99; SF_C= E <=3D =E2=80=980=E2=80=99; SF_WE <=3D =E2=80=980=E2=80=99; =EF=83=A0 wait 3T =EF= =83=A0 SF_WE <=3D =E2=80=981=E2=80=99; SF_A0 <=3D =E2=80=981=E2=80=99; =EF=83=A0 wait 2T =EF=83=A0 SF_WE <=3D =E2=80=980=E2= =80=99; =EF=83=A0 wait 3T =EF=83=A0 SF_WE <=3D =E2=80=981=E2=80=99; SF_A0 <=3D =E2=80=980=E2=80=99; SF_CE <=3D =E2=80=981= =E2=80=99;. Is it correct? Please advise and suggest me, what was wrong on my program? Why my current program did not affect memory contents? Thank you all for great help and attention. I look forward to hearing you soon. Best regards, Eka INDONESIAArticle: 102957
Peter Alfke wrote: > "Hot air" is what I call all those references to the Law, "truth in > advertizing" etc, before we even know the facts of this quotation... > We still do not know. The distributor might have had a reason to > effectively "no bid" this request for quote. Two things ... first, I referenced the law, simply to provide Xilinx some credibility, as I don't think Xilinx would violate the Truth in Advertising with the legal liabilities in California. The speculatation that Xilinx would actually lie in the PR releases is far more damaging. If I'm wrong about Xilinx's credibilty, I'm sure there will be legal action to correct that problem. Second, if Xilinx quotes those prices, and none of your distributors are willing to honor them, and Xilinx refuses to deal directly with customers, then the figures are truely false advertising, and need to be corrected ... as Xilinx is then liable under California law for the misrepresentation. that is hardly hot air ... and actually in favor of Xilinx.Article: 102958
Hi I am facing the following problem during P&R of my design =================================== Error - Description Phase 1.1 ERROR:Place:341 - The design contains 3 Block RAM components that are configured as 512x36 Block RAMs and 11 Multiplier components. The Multiplier site adjacent to the location of a 512x36 Block RAM component must remain free because of resource sharing. Therefore a device must have at least 14 Multiplier sites for this design to fit. The current device has only 12 Multiplier sites. =================================== I am using FFT core with 18-bit as the input data width, then all these above errors pops up if i reduce the input width to 17-bit, the design won't give any error. can any body help me to sort this problem ?? Thanks in advance BijoyArticle: 102959
Hi want to know how to add Location constraint for BRAM placements in my design I am using a statement like this INST "coeff_ram1" LOC=RAMB16_X1Y1; But the problem is i don't know how to find out the location values to put for my FPGA Spartan-3e ie the correct values for X?Y? can any one help me rgds bijoyArticle: 102960
Peter Alfke wrote: > I am still raising hell inside Xilinx to make it easier for our > customers to buy parts in small volume. > I have not given up, never will... Seems things are going backwards :( Until a few months ago you could buy Spartan 3's in 1-of qtys off the Xilinx website.. I got a prototype board back last week and went to buy the bits for it, and now I find I can't buy them from Xilinx anymore and have to go through Avnet. They do have some "recommended for prototype" parts, unfortunately the one I want isn't one of those :( Still I think we can use one of those parts but it was rather annoying having to stuff around getting quotes and blah blah blah whereas before it was just a simple CC transaction. Then again it's not like this is particularly uncommon.. Usually for prototypes we try and get samples (Hello Maxim, Ti, National :) or buy from Farnell (ouch) -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 102961
Hi, I am traing to use iMpact to program Xilinx PROM XCF04S, but no success. When I read back the file from the PROM after programing it and I compare the readback one with the original, they do not match. Also my iMPCAT doesnt program my Xilinx FPGA Spartan-3E : when I use iMPACT the prog doent run at all but if I use chipscope the prog will run fine on the demo borad : Spartan-3E starter kit with USB cable. But unfortunatly I cant use chipscope to prog the PROM :-(. Any idea whats wrong with iMPACT or with me :-) ?? Note: when i open the originale mcs file and the readback one, the readback one containe many FFFFF at the end of almost each line, compared to the original that have zerors instead. thank for your help in advence.Article: 102962
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > Rapid changes in kernel interface is something that is avoided within bsd > operating systems (freebsd, netbsd, openbsd) due more conservative code > acceptence policy.. Should jungo.com ever try it ;) I'd just prefer Xilinx publish the code for cableserver and standardise all their tools to use it. There's no reason all this could be done in userland (ppdev) and have maximum compatibility (and trivial portability). For faster performance you could write a driver (with source :) which bundled together JTAG ops or something.. Even pure userland is not terribly slow (I have an XC3/XCF programmer which is not much slower than impact) I'm sure you're all sick of me mentioning this by now of course 8-) -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 102963
This newsgroup is not the substitute for a request for quote sent to the appropriate sales channel. That sales channel would also have told you that the V4FX12 is too small to be a candidate for EasyPath. There are proper ways to get this information, without abusing the newsgroup, where you started a rambling discussion, without ever revealing your Anonymous identity, or even the details of your request or complaint. Most of us have better things to do than engage in these wide ranging speculations. Peter AlfkeArticle: 102964
My work is usually split 50/50 between the two. When asked which I prefer, I usually reply "the other one". Which ever one I'm currently using, I always wish I was using the other. In today's designs, you're (almost) always integrating IP from various vendors, and odds are you'll be integrating modules written in both languages. Learn both.Article: 102965
On 2006-05-24, bijoy <pbijoy@rediffmail.com> wrote: > Hi want to know how to add Location constraint for BRAM placements in my design > > I am using a statement like this > > INST "coeff_ram1" LOC=RAMB16_X1Y1; > > But the problem is i don't know how to find out the location values to put for my FPGA Spartan-3e ie the correct values for X?Y? > > can any one help me rgds bijoy One way would be to do an automatic place & route of the design and then open it in the floorplanner to see where the place & route tools placed your memories. That is probably a good starting point. Using floorplanner you can even write out a UCF file containing the placement if you want to. /AndreasArticle: 102966
> -> Are there things that VHDL does better than verilog or vice-versa Yes, yes > -> What is the most widely used language in the industry i.e. FPGA and > ASIC designs. I think VHDL is the dominant one as Xilinx totally uses > VHDL? both plus other. I see Verliog getting more and more replaced by SystemVerilog. WIth SV you enable Verilog designer to do everything you could do with VHDL including the most disadvantage of VHDL: writing bad code. A more detailed view is availabel under http://groups.google.com/groups?as_oq=vhdl+verilog or in several other discussions around the web. On a first glance you gain abstraction levels by walking along Verilog -> VHDL -> SystemVerilog -> SystemC Each gain in abstraction level costs you more effort to ensure your code is not too abstract for your task. bye ThomasArticle: 102967
John, MJ, Thank you for the suggestions. I am not sure what TIM stands for but seems like some standard connector/interface for FPGA modules. But thats right, I am looking for a 64bit/66MHz card with fpgas. I wanted to experiment with some interfaces and needed CPU to communicate with the FPGAs over PCI. BTW, I am surprised that 64/66 would still be new. I used a 64/66 MHz cPCI core in an FPGA about 3 years ago. And as far as I can tell we did not have any problems with the cPCI based processor boards. Nevertheless, thanks for the heads up. -sanjay John Aderseen wrote: > Hi again, > > I have one of > http://www.hunteng.co.uk/legacy_products/hepc4.htm > plus a couple of TIM processing modules. > If ever this is what you are looking for. > > Rgds, > John > > <fpgabuilder-groups@yahoo.com> a =E9crit dans le message de > news:1148398325.753179.326230@38g2000cwa.googlegroups.com... > > Folks, > > > > After search the net for various eval boards, I haven't found the one > > that I need and afford... that is so oxymoronic... nevertheless, I > > figured I might try the community before making a decision. > > > > I am looking for an FPGA proto board that sits on a 64/66 PCI on a ATX > > motherboard. Since we are on a budget we would like to stick with low > > end devices such as Spartan 3 or Cyclone 2 with possibility to add more > > FPGA modules as we need them. > > > > I found one at http://www.4dsp.com/PCI.htm > > > > Unfortunately, it seems that it has a 32/33 pci interface. > > > > Any suggestions? > > > > Thank you. > > Best regards, > > -Sanjay > >Article: 102968
Daniel O'Connor <darius@dons.net.au> wrote: > Peter Alfke wrote: > > I am still raising hell inside Xilinx to make it easier for our > > customers to buy parts in small volume. > > I have not given up, never will... > Seems things are going backwards :( > Until a few months ago you could buy Spartan 3's in 1-of qtys off the Xilinx > website.. I got a prototype board back last week and went to buy the bits > for it, and now I find I can't buy them from Xilinx anymore and have to go > through Avnet. > They do have some "recommended for prototype" parts, unfortunately the one I > want isn't one of those :( > Still I think we can use one of those parts but it was rather annoying > having to stuff around getting quotes and blah blah blah whereas before it > was just a simple CC transaction. > Then again it's not like this is particularly uncommon.. Usually for > prototypes we try and get samples (Hello Maxim, Ti, National :) or buy from > Farnell (ouch) For Prototyping you probably don't use BGA packages. Look at digikey for Spartan3 parts in QFP. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 102969
You might want to look at our Hollybush1 product. We have a LVDS oscillator module position, and module, that is capable of generating clocks up to 700 Mhz into the Spartan-3 on that board. The Spartan-3 on than board will realistically operate at input clock of 250-270 MHz (single rate) on the I/O and 500 Mhz DDR style with careful design. Maybe a bit faster if you are lucky. That will give at least 2nS resolution and more may be possible with phased clocks or using clock enables if the clock enable logic can be made to go fast enough. We will also have a V4 FX12 module for this board in design shortly that will be capable of higher clock rates and hence resolution. Hollybush1 can take an add on module with up to something like 110 I/O connecting to the Spartan-3 available. Longer term we are looking at a PC104 equivalent as a product. We are already doing customer specific PC104 derivatives of Hollybush1 so when we get a free engineering slot it will get done and released as a Enterpoint product. John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan-3 Development Board. http://www.enterpoint.co.uk "amko" <sinebrate@yahoo.com> wrote in message news:1148383255.575687.208820@j33g2000cwa.googlegroups.com... Hello everybody, Currently I am designing very accurate delay generator, which will be based on FPGA . This delay generator should have similar technical requirements with DG535 http://www.thinksrs.com/products/DG535.htm. The major Delay Generator requirements are · 2 ns (1ns is desired, but 2ns will be also ok) time resolution on delayed channel (it means that time differences between any delayed channels can be set in 2 ns steps) · maximal 50 ps - 60ps (RMS) jitter on each output. · 14 delayed ECL channels · Two high speed (PECL) inputs (500 Mz ECL clock signal and ECL trigger) · Configurable via standard bus (Ethernet/USB/Serial bus) · Internal trigger with variable rate (DDS) · Internal clock oscillator · Clock master or slave Does anybody know for commercial available FPGA boards (preferred ISA (PC104) or PCI (PC104 plus) standards) that can be suitable for my requirements? Sutiable FPGA for my design is V5 or Stratix 2 GX. Thank you and Regrads, AmirArticle: 102970
ivo wrote: > Hi all, > > I am exploring the possibility of using a FIFO between the OPB and my custom IP-core. I want to write data from my IP into the FIFO. I see that the FIFO has an output called RFIFO2IP_WrAck. This is an ackonowledge signal that the fifo asserts when it is ready to read data. According to some examples it seems like this signal can go low randomly, that means regardless of the fifo being full or not. To me this means that the data I want to write to the fifo must be buffered before it enters the fifo, resulting in 2 levels fifos. Then it is better to use a self written FIFO that can accept data all the time(unless when the fifo is full, of course). > > Is my assumptions wrong ? In real life, maybe this signal never goes low ? Hi Ivo, I tried to build a OPB peripheral using EDK's Create/Import peripheral wizard. After inital ease of use I got a cold shower: the OPB master support (the essential function for me) did not work as specified. Then I built my own OPB master peripheral with DCR registers. I incorporated burst transfer support of any size and asyncronous FIFO (which is not supported by the wizard). In this way I have achieved very high transmission rates from my peripheral to DDR RAM - 400MB/s (excluding retries which occur about every 300 cycles). The peripheral works much better (because it is tailored to my needs) than the one created by the wizard. Lesson: If you want the things to work, do it yourself! Cheers, GuruArticle: 102971
Hi i just realized that a DIP40 module on my desk at work could be the most expensive 8051 compatible DIP40 thing ever made - its a Virtex-4 V4LX25 based FPGA module with current manufacturer price (qty 1) of 607 USD. This expensive 51 was developed as support request to help our customers to use Nexxar to build FPGA applications - the design is based completly on open-source T51 IP Core from Daniel Wallner (jesus@opencores ) as that design does not work directly for V-4 I made the small changes (only change of BRAMs prims) and after copying the .BIT to mini-SD card, I got: HydraXC BIOS 1.0.2.a MAC: 15E087309014 Status: File: BASIC52 .BIT Loading FPGA Loading O/S... *MCS-51(tm) BASIC V1.1* READY >10 PRINT "Hello Virtex-4 MCS-51 Basic" >12 PRINT "--------------------------" >list 10 PRINT "Hello Virtex-4 MCS-51 Basic" 12 PRINT "--------------------------" READY >run Hello Virtex-4 MCS-51 Basic -------------------------- READY > ------------ the above is actual screenshot from terminal, at the place where the MCS-51 prompt appears I pressed ' ' (space) to invoke the auto-baud detection. funny, after doing it I remembered that I have done some MCS basic work earlier, porting it to 89S8252 to use internal flash. The Virtex-4 version just has the ROM Basic and 32KB XRAM the demo design should work on any decent Virtex board all 'porting' needed would be changing the UCF NET CLK LOC = W10; # 12MHz NET RXD LOC = D6; NET TXD LOC = E7; NET RST LOC = W3; all the porting was rather simple, but as I am not aware of any 'ready to run' versions of the T51 IP core, the all project may be interesting to get started with the T51 IP core in FPGA http://hydraxc.xilant.com/CMS/index.php?option=com_remository&Itemid=41&func=fileinfo&id=7 the archive contains the full ISE project - no extra tools needed - just change UCF and FPGA part, resynth and should work :) Antti LukatsArticle: 102972
uups google mocked up the url the archive is in downloads /app notes /xcapp004 or direct download link http://hydraxc.xilant.com/downloads/XCAPP004.zipArticle: 102973
Hi Jim, there was some discussion about the ise binary project file, but unortunatly I remembered it too late also I wasnt so aware that the damaged .ise file will make PN start look like freeze. I hope that the issue was solved yesterday, but sinked another two hours into the same time-sink today, a project that DID work yesterday, did not work today, failing on MAP with no error messages. after re-building a .ise file for that project again from scratch it all worked. it looks like I may up sinking more time into this by remaking the damaged .ise files :( AnttiArticle: 102974
On Wed, 24 May 2006 01:19:40 -0700, fpgabuilder wrote:
>
> Thank you for the suggestions. I am not sure what TIM stands for but
> seems like some standard connector/interface for FPGA modules.
Texas Instruments Module. See
http://www.hunteng.co.uk/legacy_products/tim40.htm
~Dave~
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