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If your FIFO is only 4-deep and runs at only 25 MHz, there are lots of ways to implement the design "brute force". Contact your ASIC supplier or other friends. They can surely help you. Peter Alfke, Xilinx ApplicationsArticle: 98251
kulkarku@math.net wrote: > Hi, > I am a beginner in the vlsi industry.I am having a doubt.Whenever we > are starting soem project work,how can we decide how much gates,logic > will be required to implement the design?and which family should be > used? > Beacuse how can we come to know this information before actual starting > the design phase? > Ok, you can equate one macrocell to one flipflop plus some lookuptable. Logic combinations are done in the lookup tables and the registered stuff are the flipflops. So, a 32bit counter takes 32 flipflops. If the counter has to auto reload when it is down, then add 32 flipflops for the latching. What did you have in mind ? an FPU ? Fourier transform ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 98252
Marco wrote: >Hi, I think it is, as you can see from table 21 on page 23 of DS099-3 >(Spartan3 datasheet), LVDS low input is (Vicm - 0.125), while LVDS high >is (Vicm + 0.125), so the difference is 25mV. >Marco > > > Funny, I read what you have above as 250 mV. 40 mV should work, at the chip, but leaves very little room for external noise sources. A very short run might work fine, but a long cable between separate pieces of equipment could easily pick up enough noise that is not perfectly balanced and cause errors. JonArticle: 98253
Symon wrote: > <sandypure@yahoo.com> wrote in message > news:1141751267.321930.165700@v46g2000cwv.googlegroups.com... > >>I have implemented a 8-bit synchronous counter by VHDL. The result is >>that the LED display show continuously running the count from 0 to >>F(in Hex). Now, I need to change the result which the LED display can >>count from 0 to 9 only. How can I change in the VHDL code? Can anyone >>answer me? Thanks a lot!! >> > > How about gating the clock to something really fast when the count is 10 - > 15 inclusive. The A-F will whizz by so fast, no-one will notice. > If you get that to work, you deserve extra marks. > HTH, Syms. That would only appear to count 0..9, a smart marker might say it still shows A..F just that your eye cannot resolve it... I think the answer is to re-write the FONT ROM code, so it only displays 0..9 - This would even pass a cursory test. ;) - and it appears to fully meet the wording of the spec... -jgArticle: 98254
Hello, there is a problem with the reset signal in DCMs but it's nothing to do with my design. I define rst signal for dcm in my ddr_sdr module (not in my testbench) and initialize it with '0' but it's not the point. The point is Xilinx libraries were buggy. Look here http://www.xilinx-china.com/xlnx/xil_ans_printfriendly.jsp?getPagePath=18941 and here http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=19851&BV_SessionID=@@@@1915933191.1141761817@@@@&BV_EngineID=cccgaddhejdkhjgcefeceihdffhdfjf.0 Any case I ignored this error and also changed some libraries and DCM locked. So now I could say that Post Synthesis looked ok. I have also just done Post-Place & Route Simulation (with -sdfmax parameter) and I had lots of warnings: 1) for all CKEs Warning: CKE Setup time violation -- tIS 2) for all ddr_sdr_data_lo1_q (it's a low part of buffered data bus) Warning: /X_FF SETUP X VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.182 ns; Observed := 0.129 ns; At : 207478.794 ns 3) for some ddr_sdr_data_hi_q (it's a high part of buffered data bus) # ** Warning: /X_FF HOLD Low VIOLATION ON CE WITH RESPECT TO CLK; # Expected := 0.028 ns; Observed := 0.016 ns; At : 207494.807 ns I also saw lots of data glitches on data bus. But I have to look at the simulation results more detailed and it's already too late. I think I could tell more tomorrow. Till tomorrow.Article: 98255
Matt Clement wrote:
> what kind of money are we talking for commercial use?
About $16K per seat.
> what software
> packages would you suggest or recommend?
corelis
-- Mike Treseler
Article: 98256Marco wrote: > Hi, the best way to estimate power consumption is through the XPower > tool within your ISE, starting from your vhdl/verilog design. Otherwise > should be hard, from my small experience, to get close-to-reality > results. However, for your XC3S1500 I would go also with, at least, 1A > for Vcco and Vccint, you can give something less only for Vccaux I > think. If it could help you, I'm making some test with an evaluation > board from Analog Devices (this has been done to extend the Blackfin > DSP features, but it can work alone as the other boards from Xilinx, > Avnet or so) equipped with a XC3S100. I have the schematic (or I can > give you a link, let me check) and you could take a look therein for > comparison. Thanks for the info. I can't use XPower because we don't have a working design yet, we are still working on it. I was told today by one of the FPGA engineers that the web based tool can give worst case numbers and not just typical, but I haven't seen it yet. I looked for a control for that and did not see it. We'll see if the FPGA guy can find it. It may not matter. I realized that the voltage margins that Xilinx specs are so small, it is not practical to put the core regulator on a different board. Instead we will run a low voltage to the board and use an LDO with the FPGA and DSP. That means I get to pick the regulator and I will be using a 1 Amp part.Article: 98257
I've used onTap in the past, although not extensively. It was fairly easy to use and I believe it costs about $2,500. John ProvidenzaArticle: 98258
Austin Lesea wrote: > http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 > > Well, I guess that about wraps it up for the attempt to disguise ASIC > design as something different... Different than the ASIC's that a number of fabless vendors produce that we call FPGA's? The business case for in-house fab, or fabless, has been a difficult call for the last two decades, and all I see from this announcement is that AMD reached the point where investing in 45nm fabs wasn't in the cards with their current volumes. When you shed your fab, with it goes your ASIC business. There are still plenty of places to take your ASIC design, or there wouldn't be the ASIC's produced by fabless FPGA vendors.Article: 98259
toys, That was the link to LSI logic dropping their structured ASIC business. Austin fpga_toys@yahoo.com wrote: > Austin Lesea wrote: > >>http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 >> >>Well, I guess that about wraps it up for the attempt to disguise ASIC >>design as something different... > > > Different than the ASIC's that a number of fabless vendors produce that > we call FPGA's? The business case for in-house fab, or fabless, has > been a difficult call for the last two decades, and all I see from this > announcement is that AMD reached the point where investing in 45nm fabs > wasn't in the cards with their current volumes. When you shed your fab, > with it goes your ASIC business. > > There are still plenty of places to take your ASIC design, or there > wouldn't be the ASIC's produced by fabless FPGA vendors. >Article: 98260
austin wrote: > toys, > > That was the link to LSI logic dropping their structured ASIC business. And that link also states: "Last year, LSI Logic also said it would sell its 8-in. wafer manufacturing plant in Gresham, Ore., as it continues to transition to a fabless manufacturing strategy." It simply doesn't make sense to by and be profitable remarketing someone elses fab services.Article: 98261
austin wrote: > toys, I've objected nicely to your changing my handle from fpga_toys, to simply toys as the obvious intent in doing so was to play the childish name altering riddicule game. So, I suggest that maybe the posters here might find it equally entertaining if we play the same game with your time .... such as altering Aus-tin to be tin-Aus-wholeArticle: 98262
Hi, Don't worry. I would like to discuss your problem with you, no matter it is for FPGA and for ASIC. They are the same. There are two flags for a full condition: 1. (Going full and write ptr = read ptr), not one. Going full means full only when write ptr = read ptr. The condition you described is just the full condition. And Going full can be used as almost full signal in the design at the 3/4 contents of AFIFO. It is very useful. 2. Same thing is with Empty. You have to really understand the paper, otherwise your ASIC design will become catastrophy! Based on the paper, I re-designed my own asynchornous logic, but it's never been used, because all my design is synchronous. WengArticle: 98263
Well, I'm not sure if anyone here has had the same problem, but I have, and it has been driving me nuts. My primary machine is a laptop, which has no parallel port, so I am stuck with USB. Also, I am in a class where we are doing projects using the Spartan-3 Starter Kit from Digilent. Since I have no parallel port, I have been using Digilent's JTAG-USB cable, which, for the most part, works great. However, there are two problems. 1. You cannot use Xilinx IMPACT to program the Spartan-3 2. The external SRAM does not work when using a .bit file Well, #2 seems awfully strange. I know it did for me, I thought I was having a problem with VHDL, and that's why I thought it wasn't working. Well, I spent a long time tinkering with it over our winter break (I know, I know, but it's what I did) and just today I came up with the solution. A little explanation for this is probably needed. Basically, anything I write and compile in IMPACT would work fine. LEDs light up, the 7-segment display works fine, everything I've done works great. However, every time I tried to write to the SRAM, nothing changed, I simply got back garbage/random data. Every time, no questions asked, it just didn't work. To make a long story short, here's a solution I discovered (which, is a whole another story to how I figured it out). 1. Start IMPACT 2. Edit -> Add Device -> Xilinx Device 3. Loaded c:\Program Files\Xilinx\spartan3\data\xc3s200_ft256.bsd 4. Right-Clicked Device, Assigned Configuration File 5. Mode -> File Mode 6. Clicked SVF-STAPL-XSVF tab, clicked "Yes" when it asked to load from Boundary Scan 7. Chose to generate a new SVF file, named it 8. Right-Clicked Device, chose Program. 9. Output -> SVF -> Stop Writing to SVF File 10. Quit Impact 11. Started Export, did Device Scan, loaded SVF into the xc3s200, set the prom to bypass, hit program. Everything worked right. Seems like a strange solution, but what I want to know, has anyone here had a problem like this? I have a feeling that loading a different .BSD file for other Xilinx chips should work just as well with the JTAG-USB cable/Digilent's ExPort software, but I couldn't tell you. Hope this helps people out. If anyone wants to contact me with any more information via email, please use: skroll at gmail dot comArticle: 98264
hi thanks a lot man i knew ther has to be a easy way out util_reduced_logic is the way out thank you G=F6ran Bilski wrote: > sachink321@gmail.com wrote: > > HI > > how would i use internal signals in XPS for microblaze on spartan 3 > > fpga board. > > > > let me explain my project > > in opb_emc > > im using 2 memory banks > > so im having two Output enable signals > > but i have only one external pin > > so i need to AND these two output signals and produce a single output > > this output will be given to the external signal. > > > > but i cant understand how can we produce a logic > > for these internal signals? > > > > any ideaz > >=20 >=20 > Put a util_reduced_logic core in the .mhs >=20 > G=F6ranArticle: 98265
Check out Universal Scan, it's fairly cheap ($500, I believe), but it has a 14-day trial so you can test it out to see if you like it. Matt Clement wrote: > Can anyone recommend some rea$onable software for doing JTAG boundary scan? > I have a design with some CPLD's that are Boundary scan capable so I thought > it would be a nice way to look for shorts or opens on the boards. But I > certainly am not looking to pay thousands of dollars for it. I have > downloaded the files defining the boundary from Altera's site, but now I > need the software to use it......preferably windows based. I could boot > linux if that is the only option. > > Thanks > >Article: 98266
I need help about controlling the speed of an ac trifasic motor, thanksArticle: 98267
Hi all, Alreay asked a few questions on this issue.. the problem is i want to implement a register read logic input is from 20 4bit registers and the output is 10 4bit wide bus. Each 4 bit element at the output can take values from any of the registers. I have implemented this with a simple indexing in the verilog like for (i=0 to 9) out[i] = reg[index[i]]; This is implimented as mux. But i want to know is there any better way to do this. I am working on the virtex E processor. What will happen if i implement this decodeing by using the RAM. That is to create a 20bit x 10 RAM and AND the RAM output with the register bit and then OR it together. Will that save area considerably. I think no. but i just want to know all of your expert openions on this. Also i am wondering which coding style will be suited for the ASIC migration (no experiance in that). Please comment on this. regards Sumesh V SArticle: 98268
Austin Lesea wrote: > http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 > > Well, I guess that about wraps it up for the attempt to disguise ASIC > design as something different... In the '80s small ASIC designs (large TTL designs) became PLD's. In the '90's small ASIC designs (large PLD designs) became FPGAs. In this decade small ASIC designs are still becoming FPGAs, just larger ones. ASIC are now system level integration, not logic subsystems. And the ASIC market continues to grow: http://www.eetimes.com/conf/dac/showArticle.jhtml?articleID=164302400 ASIC sales in 2005 are estimated to be about $20B, while Xilinx's sales are about $1.3B. ASIC's have always been something different .... bigger, faster, and larger market.Article: 98269
I don't know about your particular problem, but with regard to the parallel port, you can buy a PCMCIA to Parallel port converter. http://www.quatech.com/catalog/parallel_pcmcia.php They should work for any FPGA board that needs parallel port since the converter works at lower hardware level and it fools the operating system to think that it really has a parallel port. From the device manager, it would appear that you really have a native parallel port. If you buy it , make sure you got rev. F or later. It fixed incompatibility problem with some newer laptop. If you have the earlier rev, contact them for the RMA and they will exchange it for you. HendraArticle: 98270
fpga_toys@yahoo.com wrote: > Different than the ASIC's that a number of fabless vendors produce that > we call FPGA's? The business case for in-house fab, or fabless, has > been a difficult call for the last two decades, and all I see from this > announcement is that AMD reached the point where investing in 45nm fabs > wasn't in the cards with their current volumes. When you shed your fab, > with it goes your ASIC business. Mr Anonymous, who hides his name, but doesn't want to be called "toys": Why do you bring up AMD, which was not at all mentioned in the press release. Just to stir the pot and create additional controversy? There is understandable glee in the FPGA camp when one of the most ardent proponents of "Structured ASICs" (the "FPGA-killer technology") finally, after many unsuccessful money-losing years, throws in the towel. Basta, finito, kaput. So it is now clear again, as it has always been: There are ASICs (with their well-known technical advantages and economically-based disadvantages) and there are FPGAs (not as big, not as fast, and not as frugal, but increasingly popular for reasonable designs in reasonble volume, and far less risky). Both camps will survive, but the trend is in favor of FPGAs. Please, don't throw any more of your venom at this newsgroup. You have stopped being entertaining or informative, a long time ago. Peter Alfke, from home.Article: 98271
Hello Aurash, Thanks for you time. Well, by C i mean the complete pakage/knoledge of C from A to Z at SW engineer, by functional C i mean some knowlege to be able to programme CPU Knoledge for HW programming. So, what's knowlegde should i have to be able to wrire device driver? Thank you. ThomasArticle: 98272
How exactly is crosstalk analysis performed on a FPGA (in particular Xilinx Virtex series). Are there particular tools available for a particular FPGA or a single tool can be used to perform crosstalk analysis on various FPGAs. Also, in industry currently what tools are used to perform this analysis. Thanks regards, ManishArticle: 98273
#1 there is no way (til today) to create impact compatible 3rd party programmers other than those that are cable III compliant, (unless usb platform cable is integrated fully in the design) - hence the digilent cable is not supported by impact #2 this what I dont understand - FPGA and all connected stuff (SRAM whatever) will work same way no matter what means are used to configure the FPGA given the FPGA is really configured properly. So configuring the FPGA with .bit file using impact or SVF file and some 3rd party tool, should get the FGPA into same working condition. If you had some trouble then its must some trick bug of the digilient export software I guess btw jtag config is a bit tricky, namly it is possible have DONE=1 when FPGA is not configured at all etc.. AnttiArticle: 98274
On Tue, 07 Mar 2006 17:01:31 GMT, Duane Clark <dclark@junkmail.com> wrote: >Subhasri krishnan wrote: >> Hi all, >> I am trying to modify some code and I came across these constraints. >> 'clk_in' is the input clock and 'clk' is generated using a DCM (its is >> the Divide By 2 output). >> >> NET "clk_in" TNM_NET = "clk_in"; >> TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %; >> >> TIMEGRP "rising_ffs" = RISING "clk"; >> TIMEGRP "falling_ffs" = FALLING "clk"; >> TIMESPEC "TS_pos_to_neg" = FROM "rising_ffs" TO "falling_ffs" 5 ns ; >> >> Is there something wrong with the last FROM : TO statement? Can the >> same condition be specified using the Period statement? I think its >> supposed to mean "delay between the rising and falling edge is to be >> kept to 5ns". > >Yes, the same condition can be specified with a period statement. When >ISE sees that opposite edges of the clock are being used, it will >automatically cut the period in half (assuming a HIGH 50 % is >applicable). So you just need: >TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %; A period of 20ns and a rising to falling time of 5ns would give a duty cycle of 25%, not 50%. I've never liked the way the duty cycle is specified in UCF, as it's impossible to describe a worst case range. For example, if the duty cycle can vary between 40 and 60%, then one would need to decrease the period spec by 20% to adequately cover the rising to falling and falling to rising paths, but this results in an unnecessarily tight spec for the rising to rising and falling to falling paths. Xilinx, take note. Regards, Allan
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