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Gabor, HSWAP_EN controls the pullup on the I/Os during configuration and in this stage I want to have the CCLK (configuration clock, dedicated pin) working, while the serial_clock (another pin used after initialization for serial communication with the DSP) has to be set to a high logic level at the AND port. Then, when all done and the FPGA has been programmed, I need the CCLK to be high and the serial_clock to be enabled, so that in both situations I get the correct clock out from the AND port and going into the same pin of the DSP. Do I need external pullups for that? Thanks, MarcoArticle: 98151
I see something but I am not sure.. am i dreaming? Can LatticeXP be supplied with only 3.3V linear voltage regulator? yusufArticle: 98152
no you are not dreaming yes it can be powered from single 3.3V supplyArticle: 98153
kent.mou@gmail.com wrote: >I met problem while doing place for Spartan-3 in ISE 7.1 .They said. > Number of BUFGMUXs 2 out of 8 25% > Number of External IOBs 31 out of 221 14% > Number of LOCed IOBs 0 out of 31 0% > > Number of Slices 9643 out of 13312 72% > Number of SLICEMs 52 out of 6656 1% > WARNING:Place:119 - Unable to find location. SLICEL component > ins_rsa_core_combine/U_reg[768] not placed. >...... >...... >..... > 0,256 ins_rsa_core_combine/U_reg[1024] >ERROR:Place:120 - There were not enough sites to place all selected >components > >I used large width register and adder in this design, the reg will map >into FF with the SLICES? And I can see SLICEM only used 52. If the >silces is not enough, why the tools did not use SLICEM? Do you use local or gated clocks? In other words, does your design have FFs that are not clocked directly by the main two clocks? If so, then the limit to your design may be the amount of low skew routing for clocking, the lack of which may limit the number of usable slices for registers using different clocks. Local and gated clocks are very useful in ASIC designs. To convert to a FPGA, you may need to convert some or all of these to using the clock enable inputs. -- Phil HaysArticle: 98154
The temptation is great, Austin Simon Peacock wrote: > but sarcasm is so much better than a pointy stick. > > Simon > > "austin" <austin@xilinx.com> wrote in message > news:dude5h$ar25@xco-news.xilinx.com... > >>Duane, >> >>Yes, I apologize for my sarcasm. >> >>I had just read the posting concerning newsgroups, and how to get the >>best answers from them. This post was a classic example of someone who >>had not even had the foresight to do any research on their own. >> >>Given that everyone who posts here has access to google (or any other >>search engine), it is generally annoying to see questions that could be >>answered by three minutes of browsing and reading. >> >>Sarcasm is the weapon of the weak, and I should have been more civil, >> >>Austin >> >>Duane Clark wrote: >> >> >>>Hendra wrote: >>> >>> >>>>Austin Lesea wrote: >>>> >>>> >>>>>Matt, >>>>> >>>>>If you use a a cpld, you need to post in comp.arch.cpld >>>>> >>>>>Austin >>>> >>>> >>>>There is no comp.arch.cpld >>>> >>> >>>I suspect he was being facetious, and just forgot the smiley ;) >>> > > >Article: 98155
Hi, I need someone more experinced to confirm me if the TPS54610 I have choosen for the 2.5V voltage supply of my Spartan3 will handle reverse current (that arises from using 3.3V signals on 2.5V dedicated pins like CCLK, TDI, TMS...). One the schematic of a Spartan3 evaluation board I saw an LM3475MF for this supply and this also should work without the need of a shunt Rpar resistor to avoid reverse current from entering the regulator. Please advice me on the TSP54610. Thanks, MarcoArticle: 98156
MM wrote:
> Duane,
>
> ...
> You got me confused. You said you started with the GPIO core and you are
> saying that you can do self-clearing bits with it somehow. Could you please
> elaborate a little bit?
I started with the GPIO core in part for historical reasons, because
initially I was adding signals to it and outputting them along the lines
of option 1 of the original post. I did this for awhile, until I finally
became tired of what a pain it was to use ;) So I made a copy of it,
stripped all the registers out of it, and moved them to a file outside
of the EDK portion of my design. And as I mentioned, then just output
the address, data, and control signals, similar to the DCR.
So in my ISE portion of the design, I have this:
-- The write registers
datai_p: process (Clk)
begin
if rising_edge(Clk) then
if RSelect = '1' and RNW = '0' then
case ABus(22 to 29) is
when MISC_REG_C =>
MISC_REG_I(15 downto 0) <= WRDATA(16 to 31);
when TIME_REG_C =>
LOAD_TIME <= '1';
when others =>
end case;
else
LOAD_TIME <= '0';
end if;
end if;
end process datai_p;
Ah, I just noticed that right there I seem to have something along the
lines of the write only bit, in the signal LOAD_TIME. I guess that is
similar to what you were looking for?
>
> I've been using a similar approach when simulating local bus of a PCI
> controller in my previous designs... However, I am again a little confused
> about what exactly you are doing. On one hand you are saying that you wrote
> a simple model of your own that handles basic PLB read/write operations. On
> the other hand you are saying that you are using Xilinx supplied bus
> models... I guess I am missing something, perhaps because I haven't looked
> at the Xilinx models yet... But I would appreciate if you could explain what
> you are doing in a little more detail...
The EDK code outputs a bunch of wrapper files, including a wrapper for
the PPC. The wrapper just instantiates the PPC. I wrote my own PPC
module. Many of the signals I don't care about, so I set them to
constant values, for example:
-- Clock and Power Management Interface / CPU Control Interface
C405CPMCORESLEEPREQ <= '1';
C405CPMMSRCE <= '1';
C405CPMMSREE <= '1';
C405CPMTIMERIRQ <= '1';
C405CPMTIMERRESETREQ <= '1';
C405XXXMACHINECHECK <= '1';
The important signals are the ones controlling reads and writes on the
bus, and they are driven (and read) from my test code:
TST: entity work.bd_test
generic map (
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH
)
port map (
M_ABus => M_ABus(0 to C_PLB_AWIDTH-1),
M_BE => M_BE,
M_RNW => M_RNW(0),
M_abort => M_abort(0),
M_busLock => M_busLock(0),
M_compress => M_compress(0),
M_guarded => M_guarded(0),
M_lockErr => M_lockErr(0),
M_MSize => M_MSize,
M_ordered => M_ordered(0),
M_priority => M_priority,
M_rdBurst => M_rdBurst(0),
M_request => M_request(0),
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst(0),
M_wrDBus => M_wrDBus(0 to C_PLB_DWIDTH-1),
PLB_MAddrAck => PLB_MAddrAck(0),
PLB_MRdDAck => PLB_MRdDAck(0),
PLB_MRdDBus => PLB_MRdDBus(0 to C_PLB_DWIDTH-1),
PLB_MWrDAck => PLB_MWrDAck(0),
PLB_Clk => PLB_Clk
);
The test code has procedures for reads and writes:
testit: process is
procedure sread(addr : in std_logic_vector(0 to C_PLB_AWIDTH-1)) is
-- data : in unsigned(7 downto 0)) is
begin
end procedure sread;
procedure swrite(addr : in std_logic_vector(0 to 31);
data : in std_logic_vector(0 to 31)) is
begin
end procedure swrite;
Along with some helper procedures:
procedure reg_read(reg : in std_logic_vector(0 to 7)) is
begin
sread(REG_BASE_C & "00" & reg & "00");
end procedure reg_read;
procedure reg_write(reg : in std_logic_vector(0 to 7);
data : in std_logic_vector(0 to 31)) is
begin
swrite(REG_BASE_C & "00" & reg & "00", data);
end procedure reg_write;
Then I can write very simple statements to test things:
-- test writing and reading some registers
reg_write(MISC_REG_C, X"00000000"); -- clear
reg_write(TIME_REG_C, X"12345678"); -- clear
wait for 500 nS;
reg_read(MISC_REG_C);
-- assert RD_DATA=X"00000000" report "Bad register readback 1";
reg_read(TIME_REG_C);
assert RD_DATA=X"12345678" report "Bad register readback 2";
Back to the EDK top level system file, it instantiates the PPC wrapper,
along with all the other EDK pieces. The PPC is now using my code. I
don't care about things like the plb_bram_if_cntlr, so I write a dummy
entity that doesn't do anything except tie outputs to constant values
(the constant values need to be the right value so that the PLB/OPB
buses will not hang). In many cases, I am not interested in the stuff on
the OPB bus, so I write a dummy plb2opb bus module.
In most cases I have devices on both the PLB and OPB buses that I am
interested in, so I include in my project the Xilinx supplied models for
plb_v34, opb_v20, plb2opb_bridge, etc, along with the other pcore models
of interest such as the opb_emc for external memory uses. And so I have
a fairly complete system with a good level of fidelity, but not at the
level of complexity of the Xilinx BFM.
Article: 98157<kent.mou@gmail.com> wrote in message news:1141652004.656514.165870@j33g2000cwa.googlegroups.com... > Hi John, > Thanks a lot for your suggestion. And I tried not to add any > constraints on it. But it didn't work.and It seems there are enough > SLICEMs. Because it show in report and FPGA editor graph that all the > SLICELS are used up, and only 1% SLCEMs are used. The par error comes > from there are not enough SLICELS to place register bit. I don't konw > why the tools can't place them into SLICEMS. Is there any contraints in > default? And It is strange Slices number from x0 to x 72 are all > SLICELS, and from X74 to X102 are half SLCIEMs and half SLCIELS. It is > not the same as Spartan datasheet said. What I used is x3s1500. The statement "Because it show in report and FPGA editor graph that all the SLICELS are used up" isn't what I saw in the lines you copied from your report. The tool should have no problem placing SliceLs in SliceM locations. If Sylvain Munaut's though of a carry chain that's too long doesn't pan out (U_reg[768] is a lot of bits!) then opening a case with Xilinx support or contacting your FAE may be the next best step. The resources as they're stated in the lines of the report suggest there is no raw resource problem so the issue should be specific to some aspect of your design.Article: 98158
On Mon, 06 Mar 2006 03:58:20 -0800, prav wrote:
> I have my VHDL modules which access the processor bus.
> I have one more third party core wher in at also uses the processor bus
> , now i have no access to their source code.
>
> Now my doubt is how to go about integrating these two since the
> tristaing of the processor bus should happen at only one place.
If two or more "devices" can each drive a bus, each of them should be
tristateable to avoid bus contention.
~Dave~
Article: 98159
In article <1141648469.373291.38320
@z34g2000cwc.googlegroups.com>, mrand@my-deja.com says...
[ ... ]
> I'm not sure if you are talking about laptops in general, or just his
> laptop. His laptop is obviously too slow for medium to large designs,
> but more modern ones, with Pentium M processors, are faster than many
> P4's, including the 2.6 GHz unit in your machine. And that is despite
> the Pentium M being based on the Pentium III design!
Anymore, just about any CPU is fast enough to be
reasonable. RAM and (particularly) hard drives make a
much bigger difference. Even the "desktop replacement"
notebooks rarely have anywhere close to the RAM capacity
of a decent desktop.
As far as hard drives go, see:
http://www.storagereview.com/articles/200511/notebook_
8.html
for one example of a direct comparison of notebook drives
to desktop drives. In this comparison, the notebook
drives lose by a fairly wide margin -- and these aren't
even particularly high-performance desktop drives.
--
Later,
Jerry.
The universe is a figment of its own imagination.
Article: 98160Hi all, I would like to create a simulation for a v4fx design containing a ppc. My instrutions memory is located on external sram. I would like to know if such a design can be behavioraly/structurly simulated. If you have done this before I would realy like to know if it is possible and if so how ? e.g. how do you recommend to initialize the external sram ? p.s. my simulator is NCsim Thanks in advance, Mordehay.Article: 98161
<me_2003@walla.co.il> schrieb im Newsbeitrag news:1141549248.324091.136550@p10g2000cwp.googlegroups.com... > Hi all, my question is as follows, > I am now going through a ppc design that I would like to run as follows > : > I need to use a internal BRAM for boot sequence and a NAND FLASH to > contain all the code. the code will be placed and run on external SRAM. > My question are as follows: > 1) what should I choose as internal BRAM IF OCM or PLB_CTLR ? doesnt really matter > 2) Are there any better ways to design such a system ? what is your question? if NAND is the cheapest NV memory ? or what? if you need more than 8MB of NV memory then NAND is a good choice AnttiArticle: 98162
Hi all, I am trying to modify some code and I came across these constraints. 'clk_in' is the input clock and 'clk' is generated using a DCM (its is the Divide By 2 output). NET "clk_in" TNM_NET = "clk_in"; TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %; TIMEGRP "rising_ffs" = RISING "clk"; TIMEGRP "falling_ffs" = FALLING "clk"; TIMESPEC "TS_pos_to_neg" = FROM "rising_ffs" TO "falling_ffs" 5 ns ; Is there something wrong with the last FROM : TO statement? Can the same condition be specified using the Period statement? I think its supposed to mean "delay between the rising and falling edge is to be kept to 5ns". Thanks Subhasri.KArticle: 98163
Hendra wrote: > I own a notebook 700 MHz PIII / 256 MB / 10.4" / 1024*768. I am > thinking of upgrading because ISE 6.3i runs very slooooowwwww with this > notebook. Not to mention that at 1024*768, nothing much that I can see > on the screen. I need higher resolution and faster CPU. > 1. What screen resolution is the ideal one for ISE? > 2. Which screen resolution that you usually use at work? > 3. What is the ideal CPU speed and RAM if I limited my self to an FPGA > less than 1.5 M gates with little constraint in the design. > > Hendra I have 2 machines: 1. IBM Thinkpad T23, P3M 1.13Ghz, 512MB RAM, 16MB VC (running at 1024x768x32-bit since that is max resolution of my LCD panel). WinXP SP2. 2. AthlonXP 2500+ @ 2.2Ghz, 768MB DDR, 9600XT 128MB at same resolution, Win2K SP4. Both machines do well. I use my AthlonXP for Xilinx ISE and my P3 does simulations in ModelSim. My P3 performs very well with simulations, not far off from my AthlonXP machine. Might be that your chip is the older P3. I have the Tualtin core which has 512KB of L2, it still IMHO is a decent performer.Article: 98164
Dear Abby, I have a coworker who is calculating the FPGA power required for a rather low speed design we are doing. The data sheet lists the quiesent currents below... XC3S1000 35 200 315 mA - the part the estimate was done on XC3S1500 45 260 410 mA - the part that is on our schematic (but that can change) The designer did an estimate using the Web Power Tool Version 8.1.01. Using the XC3S1000 and a temperature of 85C the Vccint came in at 84 mA with quiessent power of 96 mW (80 mA). Isn't this a disconnect from the data sheet??? I am trying to get the designer to spec 1 Amp each for the three supplies to the FPGA, but for whatever reason this power estimate is being used instead to justify a much lower current. Am I being overly conservative or are the numbers in the data sheet from left field? signed, Concervative and ConcernedArticle: 98165
Duane, Thanks a lot for sharing your ideas. I will certainly be using some of your them:) The main thing is that it helps me to overcome initial fear of ripping the EDK portion of the design up :) In the meantime I decided to try a DCR approach. One of my concerns with DCR was that it woud require using special assembler commands to access the registers, however apparently Xilinx has thought of that too and they created the OPB-to-DCR bridge to make devices on the DCR bus addressable in a normal way. All of this is nice and good but so far I couldn't figure out how to properly use the core... I added the bridge to my design and then I figured (perhaps wrongly?) that I had to add the DCR bus as well. I made the bridge a slave on the OPB and a master on the DCR bus. I made the slave DCR signals of the DCR bus module external in my design and tried generating the netlist. The thing complains that there are no slaves on the DCR bus... Can someone point me to an example and/or an appnote describing how this is supposed to be done? Thanks, /MikhailArticle: 98166
Marco, why do you not just put in the external pull-up resistor and figure out later whether it is redundant? A resistor costs almost nothing, and takes very little room. I suggest to worry about more important things. Maybe I am just pragmatic... Peter AlfkeArticle: 98167
Simon Peacock wrote: > OK.. I admit there are a few minor players who have flash based or fuse > based FPGA's.. but then they aren't by definition field Programmable are > they? Certainly they are. Devices that are not "field programmable" are "mask programmable" at the time the chip is manufactured. That's been standard semiconductor industry terminology for more than thirty years. The original field-programmable devices used NiCr fuses, which later gave way to TiW fuses, floating gate EPROM and EEPROM cells, and now flash memory and RAM-based parts.Article: 98168
Brendan, it really does not? It is mentioned in the PCI compiler user guide, that it can generate PCI interrupts... MartinArticle: 98169
Matt Clement wrote: > What are the advantages and disadvantages of using a CPLD instead of using > an FPGA for a design? Are some CPLD's more compatible with low-cost PCB's using fewer layers, than certain FPGA's? (memories of the spartan3 on four layers thread, where officially six was rated minimum)Article: 98170
Peter, yours seems a good suggestion, I was just wondering how and when to use internal pullups or pulldowns. MarcoArticle: 98171
"MM" <mbmsv@yahoo.com> wrote in message news:473eqgFdm132U1@individual.net... > > I added the bridge to my design and then I > figured (perhaps wrongly?) that I had to add the DCR bus as well. I made the > bridge a slave on the OPB and a master on the DCR bus. I made the slave DCR > signals of the DCR bus module external in my design and tried generating the > netlist. The thing complains that there are no slaves on the DCR bus... In case someone is following this thread, it looks as I was actually wrong when adding the DCR bus on the secondary side of the bridge. It seems that all I had to do was to pull the bridge DCR pins out... /MikhailArticle: 98172
Hi all,
I'm trying to use the ac97 codec on the virtex-ii pro development
system for a project.
The ac97 codec is attached to the base system as "MYIP", and I see the
driver is
developed by BYU. Anyhow, I wrote a small program that outputs a sound
file just to
test the codec. It seems to me that for every function call I made to
the ac97_l.h file,
the program failed at that point. For example,
printf("calling init audio...\n");
XAC97_InitAudio(XPAR_AUDIO_CODEC_BASEADDR, 0);
printf("init audio done\n");
The second printf was never reached. I also added a printf statement at
the beginning
of XAC97_InitAudio() function, but it never showed on the screen. I
assumed this
function was never entered. I wonder if this has anything to do with
the fact it is
attached as "MYIP". Has anyone worked with the audio codec on the board
before?
If anyone can point me out what I've done wrong, I'd really appreciate
it!
-Eric
Article: 98173Internal pull-up resistors are meant to provide a defined High on the unbonded or unused pin. They have also been (ab)used to form a "wired OR" (=wiredAND), which you seem to have in mind. But the wide variation of the internal resistor value (sometimes even outside the very loose specification) have given these tricks a bad name. You do not want to get into hard-to-find crosstalk issues, for the lack of penny-resistor ! Peter Alfke, Xilinx Applications.Article: 98174
Marco wrote: > Peter, yours seems a good suggestion, I was just wondering how and when > to use internal pullups or pulldowns. > Marco Don't forget that internal Pullups/Pulldowns in FPGAs that are configurable, will usually be undefined during load : ie they are Time Conditional. If your system relies on the pullup during non-operate states, then external pullups are the safest. -jg
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