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Hi, group
I generated a IPIC interface with the "Create and Import Peripheral
Wizard" in EDK's XPS to acces BRAM on the PLB bus.
I chose the user logic Master Support mode. And then try to develop my
own logic based on the generated files. I have made a small FSM to test
a single read and write (at the bottom of the message is my VHDL-code)
My states are:
a state (PrepareWr_State and PrepareRd_State) to make sure all the
addresses are correct
a state (ReqWr_State and ReqRd_State) for the request =>
IP2Bus_MstWrReq and IP2Bus_MstRdReq
a state (AckWr_State and AckRd_State) for the ack that the IPIF can
read/write from/to my ip => IP2Bus_WrAck and IP2Bus_RdAck
a state (OkWr_State and OkRd_State) so I know everything went well
But there must be something wrong because it doesn't work at all. When
I want
to write something, my FSM stays in the ReqWr_State, and when I want to
read something it also doesn't do what it should do (or atleast what I
think it should do)
Can anyone help me please?
Mich
-- TRANSITION_STATE_LOGIC
STATE_TRANSITION_LOGIC: process (ACTUAL_STATE, pushR, pushL,
pushU,
pushD, Bus2IP_MstLastAck, Bus2IP_WrReq, Bus2IP_RdReq)
variable counter_Rd : integer range 0 to 15;
variable counter_Wr : integer range 0 to 15;
begin
case ACTUAL_STATE is
when idle =>
if (pushR = '0') then
-- pushR is active low
NEXT_STATE <= PrepareWr_State;
counter_Wr := 10;
elsif (pushL = '0') then
-- pushL is actief laag
NEXT_STATE <= PrepareRd_State;
counter_Rd := 10;
else
NEXT_STATE <= idle;
end if;
when PrepareWr_State =>
if (counter_Wr = 0) then
NEXT_STATE <= ReqWr_State;
else
NEXT_STATE <= PrepareWr_State;
counter_Wr := counter_Wr - 1;
end if;
when ReqWr_State =>
if (Bus2IP_MstLastAck = '1') then
NEXT_STATE <= AckWr_State;
else
NEXT_STATE <= ReqWr_State;
end if;
when AckWr_State =>
if (Bus2IP_MstLastAck = '1') then
NEXT_STATE <= OkWr_State;
else
NEXT_STATE <= AckWr_State;
end if;
when OkWr_State => --
Writing is ok
if (pushU = '0') then -- PusU
is active Low
NEXT_STATE <= idle;
else
NEXT_STATE <= OkWr_State;
end if;
when PrepareRd_State =>
if (counter_Rd = 0) then
NEXT_STATE <= ReqRd_State;
else
NEXT_STATE <= PrepareRd_State;
counter_Rd := counter_Rd - 1;
end if;
when ReqRd_State =>
if (Bus2IP_WrReq = '1') then
NEXT_STATE <= AckRd_State;
else
NEXT_STATE <= ReqRd_State;
end if;
when AckRd_State =>
if (Bus2IP_MstLastAck = '1') then
NEXT_STATE <= OkRd_State;
else
NEXT_STATE <= AckRd_State;
end if;
when OkRd_State =>
-- Reading is ok
if (pushD = '0') then
-- pushD is actief laag
NEXT_STATE <= idle;
else
NEXT_STATE <= OkRd_State;
end if;
when others => NEXT_STATE <= idle;
end case;
end process STATE_TRANSITION_LOGIC;
-- TRANSITION_STATE_LOGIC
-- OUTPUT_LOGIC
OUTPUT_LOGIC: process (ACTUAL_STATE)
begin
case ACTUAL_STATE is
when idle =>
led <= "1110";
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when PrepareWr_State =>
led <= "0001";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when ReqWr_State =>
led <= "0010";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '1';
when AckWr_State =>
led <= "0011";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '1';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '1';
when OkWr_State =>
led <= "0100";
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when PrepareRd_State =>
led <= "1000";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when ReqRd_State =>
led <= "1001";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '1';
IP2Bus_MstWrReq <= '0';
when AckRd_State =>
led <= "1010";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '1';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '1';
IP2Bus_MstWrReq <= '0';
when OkRd_State =>
if (D_out = Bus2IP_Data(0 to 3)) then
led <= "1011";
else
led <= "1100";
end if;
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when others =>
led <= "1111";
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "00000000";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
end case;
end process OUTPUT_LOGIC;
-- OUTPUT_LOGIC
Article: 97601I was under the impression that the JTAG pins were multiplexed and could be used for IO after the programming cycle is complete. While I never implemented this so I didn't really investigate, I always figured that the "mode" that the device came up in would depend on the status of certain pins at reset and multiplexing these pins would require external logic. Hopefully somebody with more knowledge of the subject will answer your inquiry. If not, I would suggest reading the configuration manual very thoroughly and you could also contact Altera and or a local FAE.Article: 97602
On Thu, 23 Feb 2006 17:50:15 +0000 (UTC), Brian Drummond <brian_drummond@btconnect.com> wrote: >On 22 Feb 2006 16:30:02 -0800, "Nju Njoroge" <njoroge@stanford.edu> >wrote: > >>Hello, >> >>I have set-up checkpointing in ModelSim 6.0b (also using EDK 7.1 SP2). >>ModelSim complains that "two foreign architectures are missing save and >>restore callbacks" when I checkpoint. These "foreign architectures" >>happen to be the PPC swift models. When I restore the checkpoints, the >>waveforms are fully restored. However, I cannot continue the simulation >>because it makes the following complaint: >> >># ** Fatal (SmartModel): >># SWIFT protocol: >># The first call to lsm_Model_DCEvaluate must occur at time 0. >># Time: 424875000 ps >>Instance:/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst >># ** Fatal: Foreign module requested halt. >># Time: 424875 ns Iteration: 0 Foreign Process: >>/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst/SmartModel >>File: Foreign >># Fatal error at an unknown location >># >> >>Anyone encountered this issue? > >Not quite; but I am having problems AT time 0ps; with the message > ># ** Fatal (SmartModel): ># SWIFT protocol: ># Call to lsm_Model_DCEvaluate must be preceded by a call ># to lsm_Model_SetSimTimeUnit. > >May be related; I don't have any answers yet. (I have had other projects >simulate correctly with SwiftModels; but this is my first of any >complexity, as opposed to EDK projects with one toplevel ISE module) > Mine appears to be related to starting ModelSim from within another tool (HDL Designer). The SmartModels don't seem to play well with the other stuff involved (cross-probing with the block diagrams). I don't know if this sheds any light on the checkpointing problem; suspect it doesn't. - BrianArticle: 97603
Hi, I want to implement IP and TCP Layer in FPGA. I don't know if some of you have done something about this implentation. I need some advice. What can you think about this project? (the bandwith is 10Gb ethernet). Thank you PierreArticle: 97604
On Thu, 23 Feb 2006 13:27:23 -0600, Fabio Rodrigues de la Rocha <frr@uiuc.edu> wrote: > Hello, > > I have two some basic questions about the use of variables inside >processes in VHDL and about the processes execution. > > Also, I would like to confirm if when the FPGA starts all my >processes will execute once and then each time an event occurs on any >signal in their sensitivity list. It might be better to say that all processes are continuously executing all the time in an FPGA; the sensitivity list merely restricts the number of times they execute in simulation, to reduce simulation time. For a combinational process, changing an input will result in appropriate output changes, even if the input is NOT in the sensitivity list XOR:process(b) begin output <= a xor b; end process XOR; will react to changes on input A. If you want a process to only react to positive edges on "clk", it had better have an "if rising_edge(clk)" or equivalent clause... (It is of course possible to write a process that cannot be synthesised; one that responds to both clock edges is an example that would actually be useful, and I believe it is under consideration for a future VHDL standard) - BrianArticle: 97605
Hi, I am doing a project on a 10GB Ethernet. I am going to use a FPGA with a 10Gb Ethernet Mac Core. If I use a NIOS II, it's not necessary for me to purchase a development board supporting the SPI (System Packet Interface)? This interface is used between a FPGA and NPU. Thank youArticle: 97606
Hello all, I'm using the XilNet library on a Virtex-II Pro (PPC), and my objective is to send quite large amounts of data via an external MAC/PHY (SMSC 91c111) to a computer running Windows XP. The server application on the PPC is quite simple, it waits for the client to connect and then it starts streaming the data as fast as the PC is able to receive it. The protocol used is TCP. The throughput is very poor, about 800 kbps at the moment. And I can't really figure out why. Using Ethereal I have seen that it takes about 15 ms for the PC to acknowledge the data packages from the FPGA, while the ACKs from the FPGA is sent much quicker. Every once in a while, though, the ACK is sent directly after received data packet. Has anyone seen similar symptoms with XilNet? Should I swap to LwIP instead? How much work (approximately) is needed to port LwIP to work with an external MAC/PHY chip? Not very surprisingly Xilinx only provide ports to theirs own MAC IPs. The reason I used XilNet in the first place is that I'm in a bit of time shortage... Also, I have no external memory, would it be possible to run XMK and LwIP from BRAM on a Virtex-II Pro-40? -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defense Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. ----------------------------------------------- I'm looking Califorina, and feeling Minnesota. -----------------------------------------------Article: 97607
"freechip" <freechip@hotmail.fr> wrote: >I want to implement IP and TCP Layer in FPGA. >I don't know if some of you have done something about this implentation. >I need some advice. >What can you think about this project? (the bandwith is 10Gb ethernet). Short answer, it is a big project. A very big project. IP is fairly easy. TCP for a very limited list of connections (like 1 to 16) isn't too bad, as long as the odd cases are ignored. This can work very well as long as you only talk to "well behaved" remote hosts over "well behaved" networks. Unless you need to send a lot of data, a local CPU with a network stack is probably a better choice. Full TCP, at wire speed, with hardware to handle most of the odd cases, is very hard. Will require lots of gates, lots of internal and external memory, lots of simulation and testing. -- Phil HaysArticle: 97608
You can download the rc20x reference design for Celoxicas board. It works with the new debug interface and caches. It run uClinux with net support using SMC91111 lan chip. You can find it in or1k/rc203 directory in the OpenCores CVS. The design is for a Virtex2 but it should work without much modifications in another board Regards Javier Castillo On Thu, 23 Feb 2006 10:21:09 +0100, Thomas Oehme <toehme@gmail.com> wrote: >Hi there, >i`m trying to get a SoC runinng, which is based on a OR1200 >soft-processor in an Spartan 3 device. >At the moment the system is working (25 MHz, with UART, external SRAM >and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). >If i`m trying to re-synthesize the whole system with little changes or >removed peripherals, the processor seems to get very instable and the >execution of the formerly proper working code fails. >I`ve also tried to enable the caches for instructions and data, but the >result is the same. >I guess, the whole system and the processor is very sensitive for timing >problems caused by disadvantageous place and route. > >My questions: >Does anyone have experience with implementing OR1200 on spartan 3 ? >Is there any reference-desing available, which works with the new >debug-interface (i doesnt get it to work) and /or enabled caches ? >Any hints for getting better implementation-results (settings of ISE, >maybe manually place and route)? > >any hint would be helpful > >.. thanks > >Th. OehmeArticle: 97609
Pszemol wrote: > Anybody here with experiences with syntetising some 8051 core > with JTAG debugger in FPGA ? What core can you recommend ? Check out the Roman-Jones PB8051 controller core. http://www.roman-jones.com/PB8051Microcontroller.htm I would recommend contacting them directly about your JTAG debug needs. http://www.roman-jones.com/contact.htm --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 97610
This feature is intended for PCI and PCI-X applications, specifically the Xilinx PCI and PCI-X IP products. To use it, you not only need to apply the BYPASS attribute but you also need to be using a PCI or PCI-X SelectIO configuration (such as PCI33_3, PCI66_3, or PCIX). Hope that helps, Eric To use it, you not only have to apply the BYP "Brannon" <brannonking@yahoo.com> wrote in message news:1140561136.446288.138330@o13g2000cwo.googlegroups.com... > I'm using ISE 8.1.02. I seem to be having trouble making the BYPASS > attribute work on nets. As I understand it, it is supposed to go on the > net that is the output of an OBUFT. This should cause the TFB/OFB in > the ILOGIC block to be activated. FPGA Editor, though, shows no change > between building with or without the BYPASS attribute. Putting the > BYPASS attribute on any other line (including the inputs for the OBUFT) > or object gives me a warning about bad attribute placement. > > I don't understand why Xilinx doesn't provide raw primitives for ILOGIC > and OLOGIC. It seems to me that would be just as easy as using the > IDELAY element, and it would allow me to connect the TFB/OFB directly. > > I tried using IOPAD directly. IOPAD doesn't even show up in the > documentation as a valid primitive these days. NGDBuild seems to handle > it okay, though it does throw an INFO about raising that net to the > status of port. It did not, however, help with my BYPASS issue. > > Another frustrating issue is that the BYPASS attribute doesn't even > show up in the standard documentation. I had to get it from here: > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=22137 >Article: 97611
Hello all, I'm using the Xilinx Viterbi decoder IP (V5) in serial mode with standard parameters (conv 7 1/2 with codes 0 and 1 default, input soft 8-bit words signed, traceback length 42, no treillis, no puncturing). I've made a convolutional bit encoder (7 1/2) for making patterns to test the viterbi decoder and I switched to 8 bits by coding '1' as strongest ones (FF) and '0' as strongest zeros (7F). The Xilinx Viterbi decoder is decoding fine in RTL simulation with Modelsim but when I launch the simulation after P&R, I don't get the same results, and those I get are completely different from what I should get. I tryed to launch the simulation with lower clk period (60 MHz), but the results are the same, so the problem is not coming from timing errors. I have also tried to switch from serial to parallel mode, using the CE input as the input enable signal. It's still working fine in RTL simulation, but the problem remains the same after P&R, and the IP becomes much bigger (2380 slices instead of 730 in serial mode) and doesn't hold the timing anymore (XST estimation is 103 MHz vs 148 in serial mode; my design constraint is 140 MHz, my target is a V2P70-6). As anyone experienced the same problem and know how to solve it ? Thanks a lot for your answers. Regards, ArnaudArticle: 97612
Nial Stewart wrote: > Not every design has the need for million gate device functionality, > Altera and Xilinx's low cost families seem to be selling in big > numbers. Sometimes it's important to push the performance of these > lower cost devices to keep costs down. Getting the same functionality > into a smaller device can also be important if power consumtion is > critical (my original point). > > How many power supplies do you need for your big devices? Who said anything about C based HLL's NEEDING a large FPGA? ... The only NEED for a large FPGA is if you are doing reconfigurable computing on a grand scale. C based HLL's work just fine for small devices too. Since devices get bigger in 100% size jumps for most product lines, and the cost penalty for using a C based HLL is under a few percent, the window for justifying an HDL on device fit is pretty small, or non-existant. Any project which is crammed into a device with zero headroom, probably needs the next large size just to make sure that minor fixes don't obsolete the board or force an expensive rework replacing the chip with the next larger device in the middle of the production run. > > The days of FPGA's being only for hardware design are slipping away. > > While this group has been dominated by hardware designers using FPGA's > > for hardware designs, I suspect that we will see more and more > > engineers of all kinds here doing computing on FPGA's, at all levels. > > That's probably true, and I expect to be using other tools as well as > VHDL in 5 years. However as John posted above, there's alot more to > implementing an FPGA design than the description used for the logic > and I think we'll still be using HDLs to get the most out of them for > a long time to come (to a bigger extent than with C/asm). Probably the biggest change is that EE's will still be putting the chips on boards as they have always done, and the FPGA programming will shift to systems programming staff, which are frequently Computer Engineering folks these days (1/2 EE and 1/2 CSc, or CSc types with a minor in the digital side of EE). Similar to the 70's transition where EE's were doing most of the low level software design and drivers, and it shifted to a clearer hardware/software split over time. With that, tools that expect a designer to mentally be doing gate level timing design are less important that higher level tools which handle that transparently.Article: 97613
On Fri, 24 Feb 2006 04:40:21 -0600, "freechip" <freechip@hotmail.fr> wrote: > >Hi >I am working on 10 Gb Ethernet project. >I am going to use a NIOS II in a Stratix II or a Stratix GX. I don't know >yet. >I have seen 2 development boards for this high bandwith. >Normally, the interface SPI (System Packet Interface) is used between the >fpga and a NPU. > >I don't use a NPU but a NIOS II in the fpga! >So I think I can choose a development board whose within the SPI is not >supported. > >Are you agree with that? Yes. I know from experience that it is possible to implement 10GbE interfaces without SPI-4. If *I* was designing a 10GbE board, I would use an XFP, a 10GbE SERDES with an XSBI to an FPGA, and avoid the MSA-300 connector that the evaluation boards you mentioned in another thread use. That's me though; your needs may be totally different. MSA-300 would have been a good solution four to five years ago (when 10GbE was young), and may still be a good solution if you don't feel confident working with 10Gb/s serial signals on your board. Yet another option to consider is a XAUI (since this is supported by a fewl FPGA families without needing an external SERDES), however my reading of the market is that XFP will completely replace XAUI. BTW, how do you expect a NIOS II to be able to keep up with sending or receiving almost 30 million packets per second? Regards, AllanArticle: 97614
On Fri, 24 Feb 2006 09:11:02 -0600, "freechip" <freechip@hotmail.fr> wrote: > >Hi, >I am doing a project on a 10GB Ethernet. >I am going to use a FPGA with a 10Gb Ethernet Mac Core. >If I use a NIOS II, it's not necessary for me to purchase a development >board supporting the SPI (System Packet Interface)? >This interface is used between a FPGA and NPU. >Thank you No, thank you for starting four different threads in this group with the same topic. See my reply to the "Need a SPI 4?" thread. AllanArticle: 97615
Hi I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. I want to interface this to a FPGA, then place the samples into a DDR memory. Then send the samples from memory via ethernet to a PC. Can you recommend an FPGA from either Xilinx or Altera to do the job. Thanks JonArticle: 97616
If you are using a Xilinx cable, you need to make certain that the board voltage is connected to the cable to ensure that the drive levels are suitably adjusted. If you are using some other cable, I suspect that the cable drive level would be to blame. mughat wrote: > Thanks you for the reply. > > I got it to work! Strange solution. > By mounting a CPLD on my board and routing FPGA_TDO into CPLD_TDI and > connecting the JTAG cable to: FPGA_TDI og CPLD_TDO > > Maby the CPLD is more tolerent? > My JTAG system is running 2.5V > > > Andreas Beier > > > >Article: 97617
Hello,
I'm a newbie in partial reconfiguration and I'm using the tutorial
by Gregory Mermoud "A Module-Based Dynamic Partial Reconfiguration
tutorial". However, I'm facing some problems following the tutorial
using the Xilinx tool ISE Webpack.
In ISE Webpack 6.3 there is no "fpga_editor" tool so, after update
to ISE webpack 8 I thought the problem would disappear. However, I
couldn't use the bus macros files (provided in xapp290 and also
provided with the tutorial) because there some kind of incompatibility.
So, I would like to know if someone had success using the webpack for
partial reconfiguration and which version did you use.
Thank you in advance,
Fabio
Article: 97618Jon, Anything newer than Virtex II/Spartan 3 (Xilinx), or Cyclone/Stratix (Altera). Your choice, Austin maxascent wrote: > Hi > > I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. I > want to interface this to a FPGA, then place the samples into a DDR > memory. Then send the samples from memory via ethernet to a PC. Can you > recommend an FPGA from either Xilinx or Altera to do the job. > > Thanks > > JonArticle: 97619
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:dtnstk$o8m5@xco-news.xilinx.com... > Jon, > > Anything newer than Virtex II/Spartan 3 (Xilinx), or Cyclone/Stratix > (Altera). > > Your choice, > > Austin > > maxascent wrote: > >> Hi >> >> I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. I >> want to interface this to a FPGA, then place the samples into a DDR >> memory. Then send the samples from memory via ethernet to a PC. Can you >> recommend an FPGA from either Xilinx or Altera to do the job. >> >> Thanks >> >> Jon Austin, you say 'newer than Spartan-3' - does it mean that Spartan-3 is now really on the non-recommended list of Xilinx devices, or ? Spartan-3e is not fully covering all the Spartan-3 range so it can not be considered as replacement as there are no real large S3e devices at all. AnttiArticle: 97620
Antti, You are correct. What I mean is this new, or newer. Anything older is probably not capable of doing what they want. Anything this new, or newer should be capable of doing what they want, and is also available at reasonable prices in a reasonable time. Thanks, Austin Antti Lukats wrote: > "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag > news:dtnstk$o8m5@xco-news.xilinx.com... > >>Jon, >> >>Anything newer than Virtex II/Spartan 3 (Xilinx), or Cyclone/Stratix >>(Altera). >> >>Your choice, >> >>Austin >> >>maxascent wrote: >> >> >>>Hi >>> >>>I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. I >>>want to interface this to a FPGA, then place the samples into a DDR >>>memory. Then send the samples from memory via ethernet to a PC. Can you >>>recommend an FPGA from either Xilinx or Altera to do the job. >>> >>>Thanks >>> >>>Jon > > > Austin, > > you say 'newer than Spartan-3' - does it mean that Spartan-3 is now really > on the non-recommended list of Xilinx devices, or ? > > Spartan-3e is not fully covering all the Spartan-3 range so it can not be > considered as replacement as there are no real large S3e devices at all. > > Antti > >Article: 97621
Just a thought. I think it would be very useful if there was a section of the Xilinx website for exchanging reference designs and sub blocks. Similar to what is done on the Mathworks site. I know I would definitely use it :)Article: 97622
I believe 4links in the UK implemented a product like that, do a search for 4links+TCP+FPGA and you will find the press releases, Hans www.ht-lab.com "freechip" <freechip@hotmail.fr> wrote in message news:oIWdnWFOYbMTlGLeRVn_vQ@giganews.com... > > Hi, > I want to implement IP and TCP Layer in FPGA. > I don't know if some of you have done something about this implentation. > I need some advice. > What can you think about this project? (the bandwith is 10Gb ethernet). > Thank you > PierreArticle: 97623
Augast15 wrote: > I have xilinx 95108 > I am clocking by 555 timer and testing for some small project. the > 95108 is getting heated up when I connect 555 output to an IO pin(1 > number). > Then i dont understand what to do about it, this is a problem because > it rendered my previous chip non programable when I was doing same > thing? circuit is > > (Dip)555 ---> 95108 (plcc 84)-----> cro > > I have hand soldered everything on a general purpose board What is the 555's power-supply voltage? -aArticle: 97624
Have a look at the oregano 8051 design, http://www.oregano.at/ip/ip01.htm For the generic JTAG debugger look at Temento's Dialite product (http://www.temento.com/solutions/fpga.php), they provide vendor independent JTAG debuggers (they instrument at the RTL level). Hans www.ht-lab.com "Pszemol" <Pszemol@PolBox.com> wrote in message news:dtkhc7.d90.0@poczta.onet.pl... > "Robert F. Jarnot" <jarnot@mls.jpl.nasa.gov> wrote in message > news:dtl22v$73q$1@nntp1.jpl.nasa.gov... >> quickcores has become SiliconLaude -- www.siliconlaude.com -- and >> interesting 8051 cores with real-time JTAG debug are available. > > I have just visited their website and could not find IP cores available. > Instead they offer radiation-hardened silicon... > I am looking for an IP core to be put into a generic FPGA device.
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