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I am trying to connect rocket io with yet another ASIC, which send out data that are compliant with IEEE 802.3ae standard. But my effort has failed. When I debugging my design, I found that rocket IO core pop up an TXKERR error, when I input the standard idle K character 07 into it. So I read appendix B of ug024.pdf, and found that 07 is not a valid K character for rocket io. So how should I deal with this?Article: 100926
I would like to use a FPGA to create some simple test patterns. One of which is a circle with a variable diameter. I'm not sure where to start. Can this be realistically be done in an FPGA using minimal resources?Article: 100927
Fred wrote: > I would like to use a FPGA to create some simple test patterns. One of > which is a circle with a variable diameter. I'm not sure where to start. > Can this be realistically be done in an FPGA using minimal resources? As long as you only want one circle, this can be done fairly easily. For each generated pixel, calculate x^2 + y^2, and compare with r^2. If smaller than r^2, you're inside the circle, otherwise you're outside. Updating x^2 + y^2 is simple because you can use the previous result: (x+1)^2 = x^2 + 2x + 1, so it only involves an addition. r^2 can be supplied as a pre-calculated parameter. For multiple circles, you can instantiate multiple copies, and mix the outputs.Article: 100928
Morten Leikvoll wrote: > > Whenever I try to change something in a DCM, a non-reversible error appears <snip> > Also, trying to edit diff outputs causes non-reversible problems. > > I can not find anything about these issues. Any clues? > The latest versions of FPGA_editor clobber component info on edits. Start with Answer Records 22469, 23035, 21667, 22217 BrianArticle: 100929
Dear all of my friends, I need help please... Can I using another crystal oscillator instead of using SG8002DC / SG8002JF for clocking Xilinx Spartan3/3E chips? Please give me other alternatives which can be easily obtained on the ordinary electronic components store. Thanks. Best regards, EKAArticle: 100930
aymmmm@gmail.com wrote:
> hi everybody,
>
> I am in the last year of communications department, faculty of
> Engineering, and I need help for my graduation project.
>
> The final stage is to interface the Spartan-3 to a USB Bluetooth dongle
> to support wireless voice and/or data communications modulated with
> DSSS (IS-95 CDMA).
>
> I need to interface the USB dongle to the PS/2 port of Spartan-3 using
> a PS/2-to-USB converter.
>
> I have tried to find data sheets and timing diagrams of a USB dongle in
> order to understand how it works but found nothing.
Howdy,
For very standard interfaces, it is common to not find much useful
timing or datasheet type information on a particular vendors device.
You need to search for the USB specification. Google finds it.
Good luck,
Marc
Article: 100931On 21 Apr 2006 02:29:46 -0700, "aymmmm@gmail.com" <aymmmm@gmail.com> wrote: >hi everybody, > >I am in the last year of communications department, faculty of >Engineering, and I need help for my graduation project. > >The final stage is to interface the Spartan-3 to a USB Bluetooth dongle >to support wireless voice and/or data communications modulated with >DSSS (IS-95 CDMA). > >I need to interface the USB dongle to the PS/2 port of Spartan-3 using >a PS/2-to-USB converter. > >I have tried to find data sheets and timing diagrams of a USB dongle in >order to understand how it works but found nothing. > >Can anyone help? > >Thanks You will find is MUCH easier to use something other than USB - apart from the complexity in doing USB host, info is likely to be scarce on accessing the device. One of the many serial bluetooth OEM modules would be a LOT easier, and will be properly documented.Article: 100932
Hi, I am using xilinx ISE 8.1 webpack version.In my design i have used spartan2,xc2s200 fg256 family of FPGA.After routing is complete,i generate the IBIS model for FPGA.But the model doesn't show all the pins of FPGA,though all the pins are locked. Can anybody suggest me,why this is happening?IS anybody from XILINX core team suggest me solution?Article: 100933
Jeff Brower wrote: > Rick- > > If it's any consolation, we went through S3 pull-up/pull-down hell last > summer. We ended up putting a few additional values on the board that > we thought the S3 should have been able to handle internally. We also > found significant variation between S3 devices. > > We also found issues with multi-FPGA configuration from platform Flash > vs. temperature that required some undocumented FPGA-related board mods > that my company won't disclose, as it took us nearly 6 weeks to get it > nailed down. Thanks for the info, but your troubles are never consolation for mine. Considering that the Spartan 3 pullups are so stiff, I find it negligent that Xilinx would not document the fact that they put them on the mode pins. Unless you typically use *very* stiff resistors or just plain use 0 ohm jumpers for pulldowns, the mode pins will not work. Xilinx knows this and still has not put it in the data sheet that I can find. I just downloaded the data sheet and it was just updated this month. The answer record that describes the pulldown problem is over a year old! Don't you think a year is enough time to get the facts straight in a data sheet, especially on such a basic and important issue???Article: 100934
Sorry, no new clue there (but thanks for trying). I see there is a problem which supposedly should be fixed in 8.1.3, but it hasn't. "Brian Davis" <brimdavis@aol.com> wrote in message news:1145617881.615337.292890@t31g2000cwb.googlegroups.com... > Morten Leikvoll wrote: >> >> Whenever I try to change something in a DCM, a non-reversible error >> appears > <snip> >> Also, trying to edit diff outputs causes non-reversible problems. >> >> I can not find anything about these issues. Any clues? >> > > The latest versions of FPGA_editor clobber component info on edits. > > Start with Answer Records 22469, 23035, 21667, 22217 > > Brian >Article: 100935
Martin Thompson wrote: > "srini" <g.shrinivasan@gmail.com> writes: > > > Hi, > > I am new to designing with FPGAs. I have an enable_output pin in my > > FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z > > state. I would like to know how to make these o/p pins as Hi-Z by using > > the control input (i.e) enable_output. I using Verilog and Synplify Pro > > for synthesis and Xilinx ISE7.1 for PAR. > > > > It's straightforward in VHDL: > > buspins <= value when OE = '1' else (others => 'Z'); > > I guess in verilog it's something like: > > assign buspins = (OE) ? drive : 32'bz; To be equivalent to VHDL code it would be assign buspins = OE ? value : 32'bz; (parentheses are not required) > > but I'm not a verilog expert. > > I'm sure the Synplify help tells you all about inferring tristate > pins, but I can't find it myself :-( > > Cheers, > > Martin > > > -- > martin.j.thompson@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technology > http://www.trw.com/conektArticle: 100936
There are tons of them. Go to digikey.com and pick one that matches your IO voltage levels. aan.woodz@gmail.com wrote: > Dear all of my friends, > > I need help please... > > Can I using another crystal oscillator instead of using SG8002DC / > SG8002JF for clocking Xilinx Spartan3/3E chips? Please give me other > alternatives which can be easily obtained on the ordinary electronic > components store. Thanks. > > > Best regards, > EKAArticle: 100937
allanca@gmail.com wrote:
> Hi,
>
> I'm trying to create an array of Virtex-II BlockRam instances in
> verilog using
>
> RAMB16_S36_S36 BRAM[ram_modules-1:0] (.ADDRA(ADDRA), .ADDRB(ADDRB),
> ..., .DOPA(), .DOPB());
>
> This works perfectly fine, even when I add parameters like:
>
> RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST")) BRAM[ram_modules-1:0]
> (.ADDRA(ADDRA), ...
>
> However, when I add the initialization parameters, it doesn't work:
>
>
> RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST"), .INIT_A(36'h012345678))
> BRAM[ram_modules-1:0] (.ADDRA(ADDRA), ...
>
>
> Compiling is ok, but trying to simulate gives one of these for each
> module in the array:
>
> # ELAB2: Warning: ELAB2_0048 increment.v (22): Actual value is
> incompatible with formal "INIT_A" (mixed simulation) - actual value
> will be skipped.
>
> in Aldec Active-HDL.
>
> I've tried a bunch of different ways to get this to work.
> Initialization using the defparam statements with just one BRAM
> instance works fine (but not on an array, at least that I can figure
> out). I guess I could just unroll the whole thing by hand, but by now,
> I'm interested in just figuring out what's going on and how to make it
> work.
>
> Anyone else run into this or have any ideas?
>
> Much thanks
> -Allan
Is it possible that the initialization values are not replicated like
the module ports? i.e. for an array of 2 BRAMs maybe you
need to give 72 bits of INIT_A instead of 36?
RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST"),
.INIT_A(72'h012345678012345678)) BRAM[ram_modules-1:0] (.ADDRA(ADDRA),
...
Good luck,
Gabor
Article: 100938Fred wrote: > I would like to use a FPGA to create some simple test patterns. One of > which is a circle with a variable diameter. I'm not sure where to start. > Can this be realistically be done in an FPGA using minimal resources? For a single line, the Y distance from center is known - it's from your line count - and you know the desired radius so your unknowns are the leading and trailing edges for either a filled circle or an outline. X^2+Y^2=R^2 or X = +/-sqrt(r^2-Y^2) Here you just need to think of the center as 0,0 and make adjustments accordingly. The calculation only needs to be done once per line rather than for each generated pixel which means you have a full scan line's worth of time to do a calculation; serial aritmatic anyone? If you don't need to ultra-tiny solution, the raw math is pretty simple in an FPGA with embedded multipliers and a simple square root algorithm.Article: 100939
Morten Leikvoll wrote: > > >> I can not find anything about these issues. Any clues? > > > The latest versions of FPGA_editor clobber component info on edits. > > Start with Answer Records 22469, 23035, 21667, 22217 > > Sorry, no new clue there (but thanks for trying). I see there is a problem > which supposedly should be fixed in 8.1.3, but it hasn't. > Well, those Answer Records describe exactly the problems you are having in editing components, and give workarounds for ISE 7.x If for some reason you can't drop back to 7.x, you could try exporting the ncd design into XDL, changing the DCM/IOB settings in XDL, and converting it back again. BrianArticle: 100940
Fred wrote: > I would like to use a FPGA to create some simple test patterns. One of > which is a circle with a variable diameter. I'm not sure where to start. > Can this be realistically be done in an FPGA using minimal resources? > > Yes, it can. In fact, it doesn't take much logic if you think outside the box a little bit. Google "Bresenham circle" to find Bresenham's circle drawing algorithm. No need for multiplies and square roots...this does it with adds and subtracts by taking advantage of the incremental algorithm for drawing a circle on a raster.Article: 100941
Falk Salewski schrieb: > I am doing some research on the reliability of microcontrollers software in > comparison to hardware description languages for PLDs (CPLD/FPGA). > > Another interesting point is whether there are general benefits of one > hardware regarding reliability, e.g. in an automotive environment. This all depends on the type of errors you are talking about. To get an overall estimate will be really difficult. E.g. in automotives a big issue are real time constraint violations when many things happen at once. You can easily specify the timing of most hardware implemented algorithms with a granularity of nanoseconds because there is real concurrency in the implementation. For uC it is hard to get below tens of microseconds. Also, error detection and correction on ALUs, busses and memory is just not available for commercial uC, while you can easily implement it for your FPGA circuit. In theory a uC using all these techniques would be more reliable, but if you can not buy it.... (BTW: I talked to Bosch about that topic, and apparently the volume of their orders is not big enough to have Motorola design such a uC for them.) Formal model checking and property checking are becoming mainstream for hardware development but are hardly ever used for software development. These are all factors in favor of FPGAs that are often not considered, but I am sure that you come up with many reasons why uCs are more reliable. (Less transistors for example) Kolja SulimmaArticle: 100942
Hi Fred,
"Fred" <fred@nowhere.com> wrote in message
news:4448b5a2$0$209$db0fefd9@news.zen.co.uk...
> I would like to use a FPGA to create some simple test patterns. One of
> which is a circle with a variable diameter. I'm not sure where to start.
> Can this be realistically be done in an FPGA using minimal resources?
Circle are in fact very easy to draw (or "scan convert", in the lingo). You
can do it without any square-roots or even multiplies (except by 2). The
algorithm due to Bresenham has been around for some time. Here's a good
tutorial page:
http://www.cs.unc.edu/~mcmillan/comp136/Lecture7/circle.html
The basic algorithm can easily be adapted to do filled circles.
Have a lot of fun,
-Ben-
Article: 100943I've not ever been successful using the Xilinx Map options that use Pysical Synthesis. I've tried it with several version of the Xilinx tools (including Webpack 8.1 with SP3) and it always seems to crash with an error message. Am I just unlucky, or does Maps Physical Synthesis just not work? Anyone else having problems or luck with this feature? John ProvidenzaArticle: 100944
The "-global_opt on" is busted in all versions. Supposedly it will be fixed in 8.2i. However, I have had some success with "-timing -logic_opt on" as long as all your timespecs would pass otherwise. It seems to crash on tight OFFSET constraints especially. Try using From/To constraints instead if possible. I've filed seveal bug reports with Xilinx on the matter and sent them my files. Send them your files in a webcase and insist that they pass them on to the developers.Article: 100945
Hi John,
"johnp" <johnp3+nospam@probo.com> wrote in message
news:1145633046.127326.14050@u72g2000cwu.googlegroups.com...
> I've not ever been successful using the Xilinx Map options
> that use Pysical Synthesis. I've tried it with several version
> of the Xilinx tools (including Webpack 8.1 with SP3) and it
> always seems to crash with an error message.
> Am I just unlucky, or does Maps Physical Synthesis just
> not work?
It sounds like you are unlucky either way. And if it doesn't work for you,
then it doesn't work and it needs to be fixed.
> Anyone else having problems or luck with this feature?
I have used it succesfully, and I know other people round here who have too.
I would suggest the first thing to do is open a case with tech support.
Questions:
What exactly is the error message?
What other options are you using with MAP?
What part are you targeting?
What features of the chip are you using (e.g. RAMs, DSPs, EMACs, etc)?
Are you using any interesting constraints?
Cheers,
-Ben-
Article: 100946John_H wrote: > "Roger Bourne" <rover8898@hotmail.com> wrote in message > news:1145558140.602899.117160@t31g2000cwb.googlegroups.com... > > Hello all, > > > > I would like some feeback : > > > > I am planning to make a design in FPGA that has 4 2nd-order cascaded > > IIR filters. > > Now the question/feedback/advice which I am seeking is the following: > > > > To what resolution can I have the input and output databuses of the > > IIRs ? > > Assume there is nothing else but the IIRs in the FPGA > > > > P.S the FPGA is spartan 3 (400k gates) > > > > I made a rough estimate : > > I would be needing ~800-1000FFs (there is atotal of 8k) > > ~14 16-bit adders (do not know the total) > > ~8 18x18 dedicated multipliers (there is a total of 16) > > and a whole bunch of muxes. I estimate about ~2000 4:1 muxes/demuxes > > > > The above bunch of logic is for > > 4 2nd order IIRs > > 16 bit input databus for each IIR > > 16 bit output databus for each IIR > > 64 bit feedfwd & feedbck coeeficients for each IIR > > An input DC gain of 2^12 for each IIR > > One, and only one, 96 bit adder responsible for all the sums > > One, and only one, 27x64 bit multiplier responsible for all the > > multiplication > > The adder and the multipler will function at a much higher frequency > > than the sample rate, hence permitting them to do all the operations > > for all the IIRs, > > Sample rate is 1MHz. I am assuming that the sample rate can be > > multiplied up by a factor of at least of 50. 50 would give at LEAST > > 1cycles/operation. There are 20 sums and 20 multiplication to be done > > per sample period. > > > > Hence, I arrived to the conclusion that such a digital filter design > > will take me ~25% of the space of the FPGA. Does this sound accurate ? > > However I do not know how to account for routing overhead. > > > > I would appreciate previous projects citiings and how much % of the > > FPGA they occupied. > > > > Thx in advance > > -Roger > > You could reduce your resource requirements significantly by implementing a > multi-channel, multi-stage mechanism that manipulates your data and > coefficients through one BlockRAM - eliminating most of the multiplexers - > and pipelines some of the operations such as the multiply to use fewer > resources overall. > > For these kinds of things, a little pseudocode and a spreadsheet can help to > visualize how to break up the problem and verify the soultion. > > Are you looking specifically for a tiny solution? > Are you looking specifically for a tiny solution? I am looking for a solution that fits in the FPGA. Tiny?, not really, as long as every thing fits. >...ism that manipulates your data and coefficients through one BlockRAM BlockRAM. Great idea! I checked the timing specs of the blockram module, and it seems pretty fast.1clock cycle to write and 1 clock cycle for read. max freq of ~160MHz. No need for a complex multiplexing network. In fact, there is no need for delay elements (FFs)alltogether!. However, I never used RAM on an FPGA (that is the reason I did not initially lean towards that solution). Is there some obvious, flagrant , blatant drawback when using RAM , instead of FFs ? Especially since there is 36 times more RAM bits than available FFs (288K vs 8K). And in RAM, ALL the bits can be used! According to the timing waveform in the specs, it only requires 1 cycle for read and 1 cycle for write --so I do not think loss of cycles between data transters will be an issue, especially if the data rate is ~150 times slower than the fastest clock available. The module that performs the multiplication can thus be time-multiplexed. It is sounds like it is working on a DSP, rather than a FPGA, if one foregoes the use of FFs...:-) -RogerArticle: 100947
I have an application that has 300 pins on a tri-stated bus. They have a tight offset constraint for the output time. Driving the T on the OBUFT for all those off the same line fails time spec because the fanout (of 300) stretches the time a little too long. In Synplicity, you turn on the duplicate register option, and it will duplicate the last register on the T line 300 times so that the timespec will pass. XST is clueless. It seems to not even care that it is failing timespec; it does no register duplication to fix failed OFFSET constraints. I had to duplicate the register myself by declaring a bunch of them. Anyone else seen the same issue?Article: 100948
Hi, I am working on a 10 Gb Ethernet project (deep packet inspection) and need to implement CAM in my FPGA. I am using a Stratix GX and I don't think I can use CAM (internal or external) in the stratix GX Dev Board. Let me know your thoughts about that. Thanks a lot.Article: 100949
In article <4448b5a2$0$209$db0fefd9@news.zen.co.uk>, Fred <fred@nowhere.com> wrote: >I would like to use a FPGA to create some simple test patterns. One of >which is a circle with a variable diameter. I'm not sure where to start. >Can this be realistically be done in an FPGA using minimal resources? If you already have an X and Y register from your video driver, and a starting-new-line signal, then you can manage with two adders and a comparator. Have a register initialised to cx^2+cy^2 at the start of the frame. At the start of each line, add 2*(y-cy)+1 to the register. At every pixel, add 2*(x-cx)+1 to the register. If the register value is less than a threshold, light the pixel, otherwise don't. Tom
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