Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 102225

Article: 102225
Subject: Re: clock multiplier in spartan 2
From: Ico <usenet@zevv.nl>
Date: 12 May 2006 07:31:37 GMT
Links: << >>  << T >>  << A >>
Ashish <ashish.shringarpure@gmail.com> wrote:
> how to implement a clock multiplier in spartan2 from ref clock. I have
> input clock of 25 mhz and need to generate 50 Mhz clock.

You can use a DLL or DCM for that; You could also search for Peter
Alfkes paper 'six easy pieces', chapter 4

-- 
:wq
^X^Cy^K^X^C^C^C^C

Article: 102226
Subject: Re: reverse engineering ?
From: fpga_toys@yahoo.com
Date: 12 May 2006 00:35:49 -0700
Links: << >>  << T >>  << A >>

David Brown wrote:
> It sounds like rubber hose cryptoanalysis would be faster, cheaper, and
> more reliable, and it's easier to get hold of experienced staff.

The human factor has been exploited for some attacks :(


Article: 102227
Subject: Re: JTAG tutorial
From: MikeShepherd564@btinternet.com
Date: Fri, 12 May 2006 08:44:39 +0100
Links: << >>  << T >>  << A >>
>I created a small tutorial about JTAG...
http://www.fpga4fun.com/JTAG.html
>
>...happy to hear about mistakes/suggestions...

I haven't read it in detail, so I won't comment on the content, but I
like the style.  It's well-paced.  It's concise.  It doesn't have
unnecessary and confusing repetition.  It's laid out clearly with good
diagrams.  Most articles fail on all these points.

I'd only say that it's best to avoid writing small numbers (1-10) and
non-exact numbers as digits.  E.g. it's easier to read "a few
thousand...three inputs and one output" than "a few 1000...3 inputs,
and 1 output".

Mike

Article: 102228
Subject: Re: Synplify - Not satisfactory results with re-timing option
From: "srini" <g.shrinivasan@gmail.com>
Date: 12 May 2006 00:58:22 -0700
Links: << >>  << T >>  << A >>
Hi,
Thanks for the detailed explanation Phil.
Can you tell me how to do Physical synthesis and bring in the routing
delays for synthesis. I am using Xilinx ISE 7.1 for PAR. Can physical
synthesis be done with it. How to bring in the routing delays from
Xilinx PAR and use it for synthesis in Synplify Pro?

Thanks & Regards,
Srini.


Article: 102229
Subject: Re: clock multiplier in spartan 2
From: "Ashish" <ashish.shringarpure@gmail.com>
Date: 12 May 2006 01:00:21 -0700
Links: << >>  << T >>  << A >>
>You can use a DLL or DCM for that; You could also search for Peter
>Alfkes paper 'six easy pieces', chapter 4

Yes thats simple trick. Thanks for your input.


Article: 102230
Subject: How to check IOB register packing?
From: "srini" <g.shrinivasan@gmail.com>
Date: 12 May 2006 01:06:59 -0700
Links: << >>  << T >>  << A >>
Hi,
I am using the "syn_useioff = 1" directive in my top module to pack the
Input/Output registers into the IOB and synthesizing using Synplify
Pro. For PAR, I am using Xilinx ISE 7.1
I would like to know how to check and see whether the input and output
registers are packed in the IO blocks after PAR.
Also, I am tri-stating my outputs based on a control signal by using
the following syntax in verilog : out_data = 16'bz. So, I want to check
whether the tri-state buffers and the output registers are placed in
the same IOB. Can this be done? Some people are telling that this
verilog syntax will not actually tri-state the outputs in
implelementation and I have to specifically instantiate the tri-state
buffers from Xilinx. Can anyone clarify me about this?

Thanks & Regards,
Srini.


Article: 102231
Subject: difference of variable and signal
From: "YiQi" <yiqihuang@gmail.com>
Date: 12 May 2006 02:19:17 -0700
Links: << >>  << T >>  << A >>
What's the different between variable and signal?

                                                     variable
              signal
assignment operator:                         :=
        <=
share between  process:              key word"shared"
yes

what else?


Article: 102232
Subject: Re: JTAG tutorial
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Fri, 12 May 2006 10:12:11 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Fri, 12 May 2006 04:08:46 GMT) it happened "Jean Nicolle"
<jean.nicolle@sbcglobal.net> wrote in
<iTT8g.69949$_S7.49845@newssvr14.news.prodigy.com>:

>I created a small tutorial about JTAG.
>See http://www.fpga4fun.com/JTAG.html

Very nice!
Just learned a bit more about JTAG.

Article: 102233
Subject: Re: How to check IOB register packing?
From: Joseph Samson <user@example.net>
Date: Fri, 12 May 2006 10:31:52 GMT
Links: << >>  << T >>  << A >>
srini wrote:
> I would like to know how to check and see whether the input and output
> registers are packed in the IO blocks after PAR.

Look in xilinx's map report file (*.mrp). Near the end there is a table 
with a row for each IO signal and its characteristics including what IOB 
registers are used (OFF - output flipflop, IFF - input flipflop, ODDR - 
output double datarate, IDDR - input double datarate, ENFF - tristate 
enable flipflop,....)

> Also, I am tri-stating my outputs based on a control signal by using
> the following syntax in verilog : out_data = 16'bz. So, I want to check
> whether the tri-state buffers and the output registers are placed in
> the same IOB. Can this be done? Some people are telling that this
> verilog syntax will not actually tri-state the outputs in
> implelementation and I have to specifically instantiate the tri-state
> buffers from Xilinx. Can anyone clarify me about this?
Here's an example of inferring tri-state IOs:
    assign   EthMiiDat    = EthMiiDatT ? 1'bZ: EthMiiDatO;
    assign   EthMiiDatI   = EthMiiDat;

The IO Pin is EthMiiDat. Three signals go to the FPGA fabric: EthMiiDatO 
is the output, EthMiiDatI is the input and EthMiiDatT is the tri-state 
enable.

---
Joe Samson
Pixel Velocity

Article: 102234
Subject: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
From: "Trainee" <billg@microsoft.com>
Date: Fri, 12 May 2006 12:59:32 +0200
Links: << >>  << T >>  << A >>
Thank you



Now I have read the CORDIC FAQ at dspGuru. I read how to calculate the 
magnitude of a complex number with the CORDIC. And I have tried it in Excel. 
So now I'm going to implement it in VHDL.



I have heard about CORDIC before but newer sat down to read about it.



Thank you all for your help on this.





"Ray Andraka" <ray@andraka.com> wrote in message 
news:KuK8g.18376$ZW3.2280@dukeread04...
> Marko S wrote:
>> Thank you all. I will have a look at "Dijkstra's square root". I have 
>> 2000 clock cycles at 40 Mhz to complete the calculation (It should be 
>> enough). It is used for calculating the AM envelop after demodulating the 
>> signal with a coherent detector
>>
>>
>>
>> You can se the principle of the detector at 
>> http://www.cycom.co.uk/art1.html.
>>
>>
>>
>>
>>
>> "Symon" <symon_brewer@hotmail.com> wrote in message 
>> news:4462fbb4$0$15793$14726298@news.sunsite.dk...
>>
>>>"Michael Sch÷berl" <MSchoeberl@mailtonne.de> wrote in message 
>>>news:4462f354$1@news.fhg.de...
>>>
>>>>Marko S schrieb:
>>>>
>>>>>How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL?
>>>>>The signals a and b are 32 bit signed fix point numbers 
>>>>>(std_logic_vector (31 downto 0)).
>>>>
>>>>how accurate? how fast? latency?
>>>>
>>>>just for the sqrt(x) I once worked an idea to take len=ceil(log_2(x)) by 
>>>>counting the length of x (leading 0s) ...
>>>>then you shift x>>(len/2) or something (+1?) ... this worked as a good 
>>>>approximation and I added only one or two stages of a newton-raphson
>>>>
>>>
>>>Hi Marko,
>>>For square root, you could use  modified Dijkstra's square root.
>>>
>>>http://lib.tkk.fi/Diss/2005/isbn9512275279/article3.pdf
>>>
>>>One clock per output bit. No multipliers.
>>>
>>>HTH, Syms.
>>>
>>
>>
>>
>
> You aren't really looking for square root, you are looking for vector 
> magnitude.  Vector magnitude can be computed without computing the square 
> root.  For arbitrary precision, you can use the cordic algorithm in 
> vectoring mode.  It basically rotates the vector to the I axis using a 
> series of progressively smaller fixed angle rotations selected so that 
> each elemental rotation is done with a shift and add operation. After 
> rotating the vector the I axis, the magnitude is read directly from the 
> non-zero (I component) of the rotated vector.  If you don't need a lot of 
> precision, there are table methods and linear approximations (the most 
> famous is "larger plus half smaller" that will often get you a good enough 
> answer with less computation.  Either way, computing magnitude using a 
> square root is going about it the hard way (hardware-wise anyway).  For 32 
> bit arguments, CORDIC is going to be your best bet. 



Article: 102235
Subject: Re: How to check IOB register packing?
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 12 May 2006 04:35:10 -0700
Links: << >>  << T >>  << A >>
Another way to verify this is to open the ncd file in FPGA_EDITOR and
see what are put in the IOBs.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/


Article: 102236
Subject: Re: JTAG tutorial
From: Eli Hughes <emh203@psu.edu>
Date: Fri, 12 May 2006 08:40:16 -0400
Links: << >>  << T >>  << A >>
Jean Nicolle wrote:
> I created a small tutorial about JTAG.
> See http://www.fpga4fun.com/JTAG.html
> 
> I'd be happy to hear about mistakes/suggestions.
> Thanks. 
> 
> 


You mentioned that some external Flash manufacuturers make versions that 
can be ISP via JTAG?   I have been looking for such a Chip!  Do you know 
of any off hand?  Most are programmed through the SPI or Parrallel 
interface, it woulds be nice to have some JTAG capable for faster debug.

Thanks,
ELi

Article: 102237
Subject: Re: CoolRunner XPLA3 getting axed?
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 12 May 2006 12:49:59 GMT
Links: << >>  << T >>  << A >>
On 11 May 2006 10:14:45 +0100, Martin Thompson <martin.j.thompson@trw.com> wrote:

>Falk Brunner <Falk.Brunner@gmx.de> writes:
>
>> Eli Hughes schrieb:
>> 
>> > I guess my frustration goes beyond the Cool Runnerm.  Take the
>> > Spartan 3e.  Its been advertised on the website as the greast thing
>> > since sliced bread for *over* a year now.  I am sure its a nice
>> > chip.  I have been wanting to use it.   Click on the online store
>> > and select say the
>> 
>> What can a Spartan 3E do what a Spartan 3 can't? 
>
>Configure itself from parallel flash...

Or cheap SPI flash


Article: 102238
Subject: Re: CoolRunner XPLA3 getting axed?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 12 May 2006 13:51:13 +0100
Links: << >>  << T >>  << A >>
Falk Brunner <Falk.Brunner@gmx.de> writes:

> Martin Thompson schrieb:
> 
> >> What can a Spartan 3E do what a Spartan 3 can't?
> > Configure itself from parallel flash...
> 
> OK, nice feature. But not the killer.
> 

No indeed - but I thought I'd better at least one thing :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt  
   

Article: 102239
Subject: Re: Xilinx 3s8000?
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 12 May 2006 12:54:11 GMT
Links: << >>  << T >>  << A >>
On Wed, 10 May 2006 10:24:26 +0200, Michael Sch÷berl <MSchoeberl@mailtonne.de> wrote:
>> Would a VM like VMWare or VPC do the trick, keep your OS with ISE
>> version installed in different virtual boxes. As long as only one runs
>> all the machine resources are available to that VM guest, whether its
>> Linux or Windows.
>
>Do you say that this would still run at full speed?
>has anyone tried this?
>
>I suspect the emulation takes quite some ressources ...
>bye,
>Michael

VMWare is an excelent solution to not only the

   "tool version" + "OS version"

problem, but also the

   "I don't trust the service packs to not break something I depend on"

I maintain multiple versions of OS + tool + service pack, and all they
require is disk space. The following all live on one disk drive.
Each VM includes an OS, Xilinx tools, other tools I depend on (such
as editors, schematic packages, etc...) and all the projects that I
maintain with that combination.

Xilinx_5.2.1_on_DOS_6.22   0.3 Gb
Xilinx_ISE_4.2i            1.9 Gb
X_ISE_ALI_5.2_SP3          3.9 Gb
X_ISE_FND_6_1_SP3          4.3 Gb
X_ISE_FND_6_2_SP3          3.2 Gb
Xilinx_7_1_1               4.0 Gb

I have also had mutiple additional virtual machines, with different
number of service packs applied, such as

X_ISE_FND_6_1
X_ISE_FND_6_1_SP1
X_ISE_FND_6_1_SP2

With disk drives now running as low as $0.33 per Gb

   http://www.newegg.com/Product/Product.asp?Item=N82E16822148131

My X_ISE_FND_6_1_SP3 computer costs under $2.0

Even older drives at $1.00 per Gb still make this a great solution.

On that 300 Gb drive, I can have about 70 computers, each with a
specific version of OS, OS service packs, tools and their service
packs. And my 70 unique computers all fit inside 1 tower PC case.

VMware Workstation 5.5 is $189

As for performance, I have found that the performance on the PAR
software is around 95% or better of the hos machine's performance.

In the past, my machines have always been dual processor motherboards,
and VMware has only emulated single processors. When it is running,
one of the CPUs is at 100%, and the other is idle or doing what ever
else I am doing on the machine (freecell, cruising the web, reading
c.a.f, ...). The latest version of VMware has experimental/beta
support for VMs that use both CPUs. I have not tried it.

It is important to have enough memory to support the VM on your system.
For example if the VM is setup with 500 MB of memory, and you plan
to be doing other work on your system while the VM is running, I would
recommend 1Gb or 1.5 Gb of memory for the system.


Philip Freidin






Philip Freidin
Fliptronics

Article: 102240
Subject: Re: Xilinx 3s8000?
From: "John McGrath" <tails4e@gmail.com>
Date: 12 May 2006 06:04:03 -0700
Links: << >>  << T >>  << A >>
I'm really surpised by people having so much problems running different
versions of the Xilinx SW on the same machine.
I've only come to use it sinxe the 6.x timeframe, but I have multiple
versions running side by side without a problem.

I install to places like:
c:\xilinx\ISE_61
c:\xilinx\ISE_71
c:\xilinx\ISE_81

Etc, so there is a different hierarchy for each install

For my windows machines, I simply then have batch files which start the
correct version, by definig the XILINXenvironment variable, and calling
the executable
This works for the EDK too.

like:
set XILINX c:\xilinx\ISE_71
set path %XILINX%\bin\nt;%PATH%
ise.exe

It also works a treat in my linux machines in a similar way as I use
shell scripts to do the same thing. Again, multiple versions
co-existing just fine.

One thing, as ISE always attempts to open the last project when it
starts, sometimes I find after running 8.1 that 6.1 then would try open
that project. But it ususally causes a few "cannot read project"
warnings, which you just click through, and then open the project you
want.

Hope this helps a few guys out. I'm not sure about migrating the
exitsing installs of old versions to a new box, due to licences, but if
you can figure that out, give it a try, just copy the entrie directory
contents from one of those dinosaur machines, and try what I suggested
above to see if it works.
Again, I don't know how the pre 6.1 versions will behave. But if its
causing SO much trouble, It's worth a shot to see if it works.

John

Jeff Brower wrote:
> David-
>
> > Is that a licensing thing or a functionality thing?
> >
> > When I got my Spartan 3e starter kit a few days ago, I installed the
> > included ISE 8.1 under E:\Program Files\Xilinx .
> >
> > When I found out that some things Do Not Work in paths that have spaces
> > in them, I uninstalled it and re-installed it under
> > E:\ProgramFiles\Xilinx .
> >
> > Have I set myself up for a lifetime of pain until I get a new computer?
>
> No you're fine.  I tell my engineers:  back up the hard drive
> completely, try it once, and if you get lucky and *everything* works,
> then go ahead.  But when the first thing fails, then restore the
> original drive, and keep the machine pristine.  That's our lab rule,
> believe it or not.
> 
> -Jeff


Article: 102241
Subject: How to decide Fanout limit?
From: "srini" <g.shrinivasan@gmail.com>
Date: 12 May 2006 06:05:40 -0700
Links: << >>  << T >>  << A >>
Hi,
In Synplify Pro, there is a 'Fanout Guide' option. What is the
reasonable value for this option? How to decide the Fanout value. Is
there any thumb rule sort of thing for this?

Thanks & Regards,
Srini.


Article: 102242
Subject: Re: Multiple Write Port Register Files
From: John_H <johnhandwork@mail.com>
Date: Fri, 12 May 2006 13:15:11 GMT
Links: << >>  << T >>  << A >>
JJ wrote:
> Luke wrote:
> 
>>I'm working on a project that needs four write ports in a number of
>>different register files.  I'm already aware of time-multiplexing and
>>partitioning.  Generating a flop-based register file would take far too
>>many resources.
>>
>>Are there any other methods of implementing multiple write ports on a
>>single register file?  Any nifty workarounds people have done?  Any
>>paper ideas?
> 
> 
> Google this group back a few weeks, the solution was presented in
> detail to the exact same same question.
> 
> John Jakson

Bottom line: If you're using distributed memory (async read) rather than 
BlockRAM style memory and don't want to time multiplex, you'll need 4 
memories per independent port (4 write ports, one read -> 20 memories) 
and as many XORs.  Registers might not be so resource intensive after all.

Article: 102243
Subject: Re: 64-point complex FFT with 32 bit floating-point representation
From: Ray Andraka <ray@andraka.com>
Date: Fri, 12 May 2006 09:34:38 -0400
Links: << >>  << T >>  << A >>
Franco Tiratore wrote:
> Hi, Ray.
> Thanks for your suggestions.
> What do you mean with the following two phrases?
> 
> 
> 
>>Floating point trades accuracy for dynamic range.
> 
> 
> 
> and
> 
> 
> 
>>In the case
>>of OFDM, you have 64 point FFT, so at most you'll have a growth of 6
>>bits in your data.  
> 
> 
> 
> Ciao,
> Franco
> 

Floating point is a numeric representation to fit a larger dynamic range 
into a fixed number of bits.  32 bits can represent 2^32 unique values 
regardless of the format.  For fixed point representation, those 2^32 
values are equally spaced between 0 and 2^32-1 for unsigned.  Floating 
point reserves some of the bits to indicate a scale factor to extend the 
range of values that can be represented, but that comes at the price of 
minimum resolution that varies depending on the scale.  IEEE single 
precision floating point gives you 24 bits of accuracy (instead of 32), 
but that is scaled so that the msb of the 24 bit field is always 
significant.

The FFT conserves energy, it can be looked at as redistributing the 
input signal in time.  If you have a full scale input that is at a 
single frequency that has a period that is an integer sub-multiple of 
the FFT size, all the energy from that signal will fall into a single 
FFT bin.  For an N point FFT, the output at that bin will be N times the 
input signal amplitude.  Since the input is at full scale already, there 
is nothing you can do to the signal to increase the output at that bin 
more than N* the full scale input.  Adding any other frequency content 
will move some of that energy to another FFT bin, diminishing the 
spectral content in that bin.  What I am saying, is the maximum output 
value from an N point FFT is N times the maximum input value.  For a 64 
point FFT, the maximum output is no more than 64 times the maximum 
input.  For a fixed point representation, that would require the output 
to have at most six more bits than the input to represent all possible 
outputs without either overflowing or truncating the lsbs.

Article: 102244
Subject: Re: How to check IOB register packing?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 12 May 2006 09:36:12 -0400
Links: << >>  << T >>  << A >>
Jim Wu wrote:

> Another way to verify this is to open the ncd file in FPGA_EDITOR and
> see what are put in the IOBs.
> 
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
> 
Or look at the pad report, there is a column there indicating whether 
the signal is registered or not for each pad.

Article: 102245
Subject: Re: JTAG tutorial
From: "Ad" <adam.taylor@eads.com>
Date: 12 May 2006 06:49:24 -0700
Links: << >>  << T >>  << A >>
Eli

most flash devices do not have a JTAG port but can still be programmed
via JTAG by ensuring all the pins of the flash chip which are required
address, data, and control signals are connected to a device which does
have a boundary scan port. Unused fpag pins are good for this. The JTAG
software can then control the FPGA pins connected to the flash to write
data into the flash device. If you are going to do it this way it is
often necessary to take the WE pin to a spare pin on the JTAG header to
enable the speed of the programming to be quicker.

hope this helps

Ad


Article: 102246
Subject: Re: How to check IOB register packing?
From: "srini" <g.shrinivasan@gmail.com>
Date: 12 May 2006 06:54:17 -0700
Links: << >>  << T >>  << A >>
Hi,
In the map report file, all the input and output signals are listed
under the IOB name column in the IOB properties section. But under the
reg(s) column, only my clock outputs have the OFF1 entry and all other
input and ouput signals have no entry of IFF/OFF/ENFF. What does it
mean?


Article: 102247
Subject: Re: How to decide Fanout limit?
From: Rene Tschaggelar <none@none.net>
Date: Fri, 12 May 2006 17:14:48 +0200
Links: << >>  << T >>  << A >>
srini wrote:

> Hi,
> In Synplify Pro, there is a 'Fanout Guide' option. What is the
> reasonable value for this option? How to decide the Fanout value. Is
> there any thumb rule sort of thing for this?

Yes, I'd guess the fanout limit to be reached when
the signal becomes marginal at the targetted inputs,
meaning the driver is at its limit.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 102248
Subject: Re: How to decide Fanout limit?
From: "Brannon" <brannonking@yahoo.com>
Date: 12 May 2006 08:16:49 -0700
Links: << >>  << T >>  << A >>
I don't know about the Synplify fanout support, but here's my $.02 on
fanout. Set it really high, like 10000. Then, after something fails
timespec, go back and manually increase registers on a per-register
basis for any register outputs that failed timespec. It is mostly an
issue with offset constraints on output data where the tristate switch
driver has to be there in < 2ns. The problem with it is that not all
tools will automatically duplicate registers to meet the fanout
constraint, and some will duplicate to meet it when it was not
necessary to meet the time constraint, thus wasting resources.


Article: 102249
Subject: Re: 64-point complex FFT with 32 bit floating-point representation
From: "Franco Tiratore" <trapule@googlemail.com>
Date: 12 May 2006 08:17:40 -0700
Links: << >>  << T >>  << A >>

Ray Andraka ha scritto:
> The FFT conserves energy, it can be looked at as redistributing the
[cut]


More than clear!
Anyway, after my question I started to write down some formulas and I
found exactly what you have just explained me. :o)

Ciao,
Franco




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search