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John_H, I disagree your opinion. PCI traffic and performance heavily depends on chipset system. We observed that board with same PCI designs may have dramatic speed changes on different chipsets. Chipsets from some manufactures have a better performance, some have bad performance. Usually the latest version of chipsets will have a better performance over older versions for the same manufacture. It is first time to hear that in a new chipset system, there is a 20% speed decrease. It means to me that most likely the new chipset has a different schedules than before that may put PCI transactions 1 level of order of delay. For example, for older version of chipset, the schedule algorithm in the chipset selects next request to go based on their arrival time from a incoming queue; for newer version of chipset, the schedule algorithm in the chipset may change to response PCI request after 4 CPU requests are answered. If so, it would appear and report that CPU gets faster performance while sacrificing PCI environment that nobody pays attention to. I don't know why 20% speed reduction really is. That must be confirmed by PCI bus analyzer. But the reason John_H indicated is the least likely real reason. You can imagine with faster DDR/DDR II system, possible two channels of them and much higher working frequency, a 20% performance decrease cannot be blamed on the board side. WengArticle: 100551
Hello, Again, thx for everyones input > Perhaps you need to discuss what it is you are trying to do, and in what > context (homework, tinkering, work, ?) I'm trying to create a simple link/testbed for some frontends in our lab. One of the requirements for the protocol is to support framing/streaming interface. So as a starting point, I am trying to use the Aurora design core to demonstrate a link between 2 transceivers. I cant figure what to do once I have created the design core from Coregenerator. I would think, I have to integrate the Aurora core design w/ some HDL code that instructs the board to setup a link between 2 specific transceivers say MGT4 & MGT9, is that right. How can I monitor this link (is it possible to create an app similar to XAPP661 or something simpler) Is there any sample code that does something like this? Thanks, BalajiArticle: 100552
I'm attempting to an EDK project containing some custom logic to decode an NTSC video stream. When I implement using EDK, I get a number of errors during the map stage, refering to logic that has been trimmed. To deal with this, I've attempted to export the project to ISE, and generate the bit file using that tool. When I leave "trim unconnected signals" checked I get errors of the following nature: ERROR:MapLib:661 - LUT2 symbol "opb_filter_0/opb_filter_0/XNor_stagelut" (output signal=opb_filter_0/opb_filter_0/N2) has input signal "opb_filter_0/opb_filter_0/NTSC0/hpos<9>" which will be trimmed. See the trim report for details about why the input signal will become undriven. When I then go and uncheck "trim unconnected signals", I get the following error: ERROR:LIT:144 - Only STATUS0, STATUS1 and STATUS2 can be used in DCM symbol "dcm_0/dcm_0/DCM_INST" (output signal=dcm_0/dcm_0/CLK0_BUF). I have attempted to synthesize and implement *only* my custom video decoding module using ISE, and none of the used signals get trimmed. However, when I instantiate it in EDK and use that project, the vast majority of my logic gets removed (even the signals coming in from FPGA pins). Any suggestions would be much appreciated. -MattArticle: 100553
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:443b28e3@clear.net.nz... > shawnn@gmail.com wrote: >> We are using a Lattice LC4256V CPLD for a new design and we're having >> some problems with open drain outputs + 5V pullups. We've debuged and >> removed items from the system to the point where we have the single >> CPLD (pins configured 3.3v CMOS open drain) connected to a 4.7K >> resistor to +5V. >> >> We configured the pins to output a 4MHz square wave for testing. When >> we hook a scope up to the pins, we see that the voltage rises at a very >> slow rate at the high edge of the clock pulse and only makes it to >> about 2V before the falling edge takes the output low. When we remove >> the pullups and set the pins to normal 3.3V mode we get a clean square >> wave, it is only when using pullups that problems are created. >> >> Any ideas on why the pullup is taking so long to bring the pin voltage >> to 5V? We have used 4.7K pullups with other FPGA / CPLD designs before >> in designs faster than 4 MHz without any problems. Doing the math, it >> seems the acting capacitence from the CPLD is something like 15uF to >> have the pullup rise so slowly. Am I doing something wrong here? > > The maths is suspect if you get 15uF. > > 4MHz is 125ns H/L, and a 125 ns Tau, is 26pF/4K7 > > So, your symptoms indicate ~26pf system c : That is highish, > but not outlandish. What else is this connected to : > Loads, track etc ? > > Simple solution is to lower the pullup... I would suggest a 1K pullup. Also, a conventional 10x passive scope probe can add 10 to 12pF of capacitance to the circuit. You should use a 10x active probe with less than 1pF of input capacitance to see what is going on. Daniel LangArticle: 100554
Hi,
I have a design with 2 components, each of which implement a small
but non trivial state machine. Each one has an associated area estimate
reported by Xilinx, say A1 and A2. Now I realized that both of these
components would never execute their state machine concurrently so I
combined both state machines into one larger state machine, with the
idea that I might be able to save some area since states in both
individual state machine might use the same resource. At the very least
I thought the new area of the larger state machine would be A1 + A2. I
was actually expecting something smaller than an additive area ( due to
the resource sharing), but instead I was surprised to note that Xilinx
reported an area larger than (A1 + A2). Whats going on here? Are
additional LUT components being used for routing purposes? Im somewhat
confused as it did the exact opposite of what I expected. Any help or
explanation would be appreciated!
Scott
Article: 100555ssirowy@gmail.com wrote: > Hi, > I have a design with 2 components, each of which implement a small > but non trivial state machine. Each one has an associated area estimate > reported by Xilinx, say A1 and A2. Now I realized that both of these > components would never execute their state machine concurrently so I > combined both state machines into one larger state machine, with the > idea that I might be able to save some area since states in both > individual state machine might use the same resource. At the very least > I thought the new area of the larger state machine would be A1 + A2. I > was actually expecting something smaller than an additive area ( due to > the resource sharing), but instead I was surprised to note that Xilinx > reported an area larger than (A1 + A2). Whats going on here? Are > additional LUT components being used for routing purposes? Im somewhat > confused as it did the exact opposite of what I expected. Any help or > explanation would be appreciated! What exactly did you expect to share ? Think of a state machine as a Set of registers, and a ROM. The registers that hold the present state, clearly cannot share. The ROMs will individually logic-reduce to pack into logic fabric, but how would sharing help shrink 2 ROMs ? Suppose a portion of the 2 roms does match, then you will need decoders and MUXs to switch in the shared portion - so you go backwards before you go forwards ( and expect a very smart synthesis tool !) Then a later state-edit could undo all this.... Generally, you make state-machines smaller by doing the opposite of what you seem to propose : ie sometimes nested machines can be smaller. -jgArticle: 100556
Hi, FPGA are already provided on-chip oscillator. If user don't want to use ext oscillator as a clock source;he can use internal,but the limitation is of the frequency of onchip oscillator. Is ur question get answer? if not then pls elaboarate more.Article: 100557
I use the XUPV2P dev. board which contains XC2V30 chip. It contains flash memory interface (ACE controller) and DDR Memory interface. I thought of using the Flash as my boot loader to copy the image (application) from PC and put it in RAM and execute from it. I'm using my own controllers & processor. Now since I 've some area unfilled, I feel, to synthesize ROM in that and put the boot loader, which on reset, recieves the data from PC (serial) and just put it in RAM and execute from the RAM. or Is it better to program the flash offline, the image, copy them to RAM on reset and execute from there. I feel running from FLASH is too slow, as I can access only ACE controller, not the FLASH directly and only 16x16 bits data buffer is there in ace controller, which makes fetching the data from it takes more time. Please comment anyother ways if anyone used xilinx flash card / ace controller / DDR memory in the board. My image can be of 128Mb. PrakashArticle: 100558
I was finally able to order a Spartan 3E Starter Kit from Avnet late
last week. (Before that the Xilinx site said that it was orderable
from Avnet, but the Avnet site said that it was not.) It arrived
today, and the preprogrammed demo works fine. I haven't yet loaded
any of the other demos, or tried to program any of my own designs.
The kit does noot come with a printed copy of its user's guide, but
that's not a problem since the PDF is available for download from
the Xilinx site, as are the schematic and gerber files:
ttp://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?&key=HW-SPAR3E-SK-US
A DVD of Webpack (and demo of ISE) is included, as well as a demo of
the EDK.
The kit comes with book "Introduction to Programmable Logic" of about
200 pages, which in not specific to the kit but appears to be a good
general introduction to Xilinx CPLDs and FPGAs, and the tool chain.
Nine demo designs with doucmentation are also available for download:
http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
I'm thinking about having some prototyping boards made with a connector
to mate with the 100-pin Hirose expansion connector on the Starter Kit
board. I'll include a 3.3V regulator on my board. Aside from a 0.1
inch hole grid, would anyone have any specific requests for reasonably
general-purpose things to add? Most of the common I/O that I want
is already on the Starter Kit board, so I mostly intend to use the
prototyping boards for very application-specific things.
It appears that the mating connector would be the Hirose
FX2-100S-1.27DS, but I haven't confirmed this. If so, it's available
from Digikey for $7.07 quantity one.
I think I might add two 270-ohm resistors to the starter kit, between
two FPGA pins and the "reserved" pins 2 and 6 of the PS/2 connector.
This would allow using both a mouse and keybaord at the same time,
with a common laptop "PS/2 splitter cable". I haven't yet chosen
which FPGA pins to use.
I hope that Digilent will offer a version of this board with an
XC3S1600E chip in the near future. :-)
Eric
Article: 100559"nimayshah" <nimayshah@gmail.com> wrote in message news:1144693869.452038.114940@z34g2000cwc.googlegroups.com... > Also a stark difference in > the synthesis report is that my core's lut synthesizes into a Block RAM > and the Xilinx core uses nothing like that. > So my questions are: > 1. What does the core use for storing LUT contents? Are you using 'LUT' here as a general abbreviation for Look Up Table, ie where you store co-efficients etc? In FPGA parlance a LUT is a (usually) 4 input single output combinatorical logic module. If you want to store hard assigned values in the FPGA you can use the flip- flops, these can be initialised to specific values on power up. These will operate much faster than Blockrams, but will use a lot more of the FPGA fabric. What do the P&R reports of the two cores show the logic usage as? The speed your design runs at can also be down to the way you've structured the design, the amount of combinatorial logic between registers etc. This is the sort of thing a more experienced designer will take into account when doing the initial hardware architecture design. (It's a Hardware Description Language remember, not software). Sorry if this is teaching you to suck eggs but it's not clear exactly what you mean in your question. NialArticle: 100560
I think the bus functional model exists because Xilinx want Aurora to become a Standard, rather than just used by their FPGAs. ColinArticle: 100561
"Sander & Stieneke Odekerken" <sanderA_en_stienekeB@wanadooC.nlD> wrote in message news:443be5db$0$117$dbd4d001@news.wanadoo.nl... > Another problem I'm facing is that I can't read/write any information > from/to the configuration space of the internal PCI master/target device or > any other (external) PCI device (actually I didn't tried that because I first want to know if it > works before I blow up the device :-) ). Should configuration be done in VHDL or can > it be done in software? If it is possible using software, do I have to write > to the Avalon bus or directly to the PCI Bus Access slave port? Do you have > any examples or reference of how to do a configuration by software? Sander, I presume this is so you can insert a board with a NIOS core into a system that has a PCI bus? The configuration registers are normally initialised by whatever's driving the PCI bus. As an example in a PC when it boots up it walks down the PCI bus detecting devices and allocating memory addresses etc to them. You probably shouldn't be trying to write to these from the other side of the PIC interface. Nial.Article: 100562
Ricardo schrieb: > Hi. > > I have a PCI board developed and I have little acess to the FPGA PCI > core, since it was not developed in house. I can say it makes no burst > accesses. Is your board handling the transactions as initiator or target? If it is a target, the burst length is controlled by the CPU. AFAIK the best you can do with IA32 is a burst of length four by using SSE 128 bit moves. If your board is the initiator, it controls the burst length, but the chipset could abort or retry transaction to enforce shorter burst. But I doubt that it will do that below a length of four. Use chipscope to have a look at what happens on the bus. Kolja SulimmaArticle: 100563
"Ricardo" <spamgoeshere1978@yahoo.com> wrote in message news:4a2fkaFqo01qU1@individual.net... > Hi. > I have a PCI board developed and I have little acess to the FPGA PCI core, since it was not > developed in house. I can say it makes no burst accesses. My proble is that I used to have a > reasonable speed with these boards with athlon/semprom boards, regardless of chipset. After the > chipsets/processors changed to socket 754 and 939 (and got HyperTransport, but I don't know > whether it's related) i got a 20% speed drop, a little too much. With the nForce4 chipset I may > get to the same speed as before, but I can't achieve it with a stable bandwidth. I don't have any > intel boxex around to test with it. > Does anyone has any clue on what's going on (even better, a solution)? Have you played about with the BIOSs of the two systems to see how the PCI inerfaces are configured? This might be worth looking at, from memory there are a few PCI parameters that you can play about with here and this might improve your performance somewhat. Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 100564
"John_H" <johnhandwork@mail.com> wrote in message news:ddQ_f.6732$tT.3171@news01.roc.ny... > > considered black market. > What about colour printers? I'll get my coat....Article: 100565
On 8 Apr 2006 02:07:39 -0700, burn.sir@gmail.com wrote: >Having seen way too much spam on this newsgroup lately, I have come >with a possible solution that just might work. The people that spam our news group do not read this news group. >Add a section to FPGA FAQ where the known names on the newsgroup will >list the companies they recommend (plus some explanation). Next time >someone spams the list about "high quality PCB", or what the hell it >is, we post a polite response saying that no one should support spammer >companies and we suggest you choose another manufacture from the list >below (link to FPGA-FAQ follows). Given that spammers only care about >money, seeing they are loosing customers might stop them from spamming >the list. And they certainly don't read the FPGA FAQ at www.fpga-faq.org >This way, you will also support the local companies that you think are >doing a good job ;) > >We could also add another section about newsgroup netiquette, 3leet >English and what we think about doing other peoples homework. This is >of course not as big problem as spammer, but it is still a little bit >annoying sometimes. People with poor net hygiene don't read FAQ's either. >Furthermore, someone should contact Google, notifying them about the >existence of a group FAQ. I think the biggest problem with the FAQ is >that the ones that dont know about it are the ones that really need to >read it :) Actually I think the real problem with the FAQ is the poor coverage of Frequently Asked Questions. The content of the FAQ web site can be roughly broken down into 3 pieces: The archive of the news group (about 88.1% of all visitors, 13 GB/month) The list of FPGA boards (about 10.4% of all visitors, 1.2 GB/month) The FAQ questions and answers (about 0.5% of all visitors, not worth measuring) The FAQ section has been open to anyone to write up articles that they feel would enhance this area. There have been very few participants. Writing good articles takes time and most of us have schedule pressures that means that as soon as we get a resolution to a problem, we move on to the next issue. Taking time to write it up for the FAQ is not on anyone's radar. Fortunately, we have the news group, which though it does not present condensed answers to FA questions, there are enough keywords, and high quality search engines, so that the collected wisdom can be re-used. About 34 mainstream search engines crawl the archive per month (and generate about 1/2 the total bandwidth), and so questions that have enough key words often get you into the archive pretty close to a discussion on your topic. This leads to about 3500 to 4500 visitors a day. Anyone who would like to contribute to the FAQ section is VERY welcome, email me with your topics! >regards > - Bruns Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 100566
It appears that the Stratix II is not going to be fast enough for the first stage. The primary problem is the lack of being able to support a synchronous parallel bus. Looking in the October 2005 Stratix II GX handbook, the fastest reference clock appears to be 622MHz, far below where I want to run at. I could run a slower clock, use the SERDES to multiply it up and resync the data and expand it out as you suggest, but this really does not make a lot of sense. The clock already has phase noise under 5pS rms (from testing) and the data would be matched going to the device. I tried the SERDES approach you mentioned with the Quartus tools using the Stratix II as a target device (even though we have a full license for Quartus the tool requires TalkBack spyware when targeting a GX device) and it seems to work. I tried to set the clock to the frequency I am interested in and the tool barks back with an error. I then tried a very simple approach of just using clocked register but no luck. I have seen a few Virtex 4 designs now that directly run a parallel bus at the speeds I am interested in. I am a bit gun shy after all the problems we have seen with Xilinx over the years, but they seem to be a better fit for this application. If you have any other ideas, I would be interested in hearing them.Article: 100567
vssumesh wrote: > Hi all, > Is it possible to use the adder and multiplier in the DSP48 block of > the virtex4 FPGA separately but simultaniously. From the user guide i > get a feeling "No" but i wanted to know your expert openion on this > issue. > Thanks and regards > Sumesh V S > No, in fact the adder is always used with the multiplier. The adder is actually a tree adder that combines the multiplier partial products and an additional term from the C input. It is still used to combine multiplier partial products even if you don't use the C input (not using it forces a 0 into that input of the adder tree.Article: 100568
Hi Im trying to access the FAT table in a compact flash. from what i have understood i have got sandisk 256mb compact flash compact flash memory starts with - a boot sector of 512 bytes - then FAT 1 of 512 bytes - FAT 2 - Data i want to print the FAT table how iam i doing that is like this Read a sector using LBA mode set command register to 0x20 and then i need to give LBA logical block address LBA usually starts from 0 so i assumed that LBA for FAT table is gonna be at address 1 so i gave LBA address as 1 this program is made of assumptions and the program is not working CAN ANYONE TELL ME HOW TO PRINT THE FAT TABLE FROM MY COMPACT FLASH ???????????????Article: 100569
Greetings, I'd like to program my Spartan3E with an SPI memory normally. For development at my desk, I understand I can add a header to allow IMPACT to configure the SPI flash memory. We have many legacy designs that bit-bang the FPGA to program it in slave serial mode allowing (re)configuration by software, typically with no configuration RAM in the first place. Rather than getting the software folks to write the SPI driver to reprogram the SPI memory through an equivalent bit-bang, I'd be interested in a readback of a slave-serial programmed FPGA by the FPGA while the FPGA is active to directly program the SPI memory with my own internal routines. --> Any ideas on whether I can accomplish this or how best to approach it? While writing this post I came to realize the external readback would be on the passive slave port, not the SPI side so the SPI persistence setting isn't an issue. But will I need to double-up the passive serial port to do the readback through other I/O pins?Article: 100570
it all works (should work) with S3e, but you would still to write your own software to handle the SPI memory anttiArticle: 100571
billu wrote: > Hello, > > Again, thx for everyones input > >> Perhaps you need to discuss what it is you are trying to do, and in what >> context (homework, tinkering, work, ?) > I'm trying to create a simple link/testbed for some frontends in our > lab. One of the requirements for the protocol is to support > framing/streaming interface. So as a starting point, I am trying to use > the Aurora design core to demonstrate a link between 2 transceivers. I > cant figure what to do once I have created the design core from > Coregenerator. I would think, I have to integrate the Aurora core > design w/ some HDL code that instructs the board to setup a link > between 2 specific transceivers say MGT4 & MGT9, is that right. How can > I monitor this link (is it possible to create an app similar to XAPP661 > or something simpler) Is there any sample code that does something like > this? I guess part of the reason I asked that question is that you stated elsewhere "(dont have any experience w/ hdl)". This is a bit of a complex starter project. There is no setting up of the link needed with the Aurora core. The core handles all this for you, and all you care about is getting a channel_up signal, which indicates the Aurora core is "finished" setting up the link. In your simulation, you should see this behavior, and that is just how the real hardware operates. If you don't get that, it is the first problem to fix. For simple testing, I normally just implement a counter in the FPGA. Send that data out one end of the link, and test for the correct pattern at the receive side. I typically make the counter roll over at a non-power of 2 count. At the receive end, have a counter that counts errors. How you get that information out depends on how much work you want to do, and what is available on the ML321 (I have not used that particular board). I like to use the PPC with an RS232 link to control the test and obtain results. But that can be a substantial amount of work by itself if you don't already have a working PPC system.Article: 100572
Dear Guru, The recipe works as you told. Tank you very much for your help. regards, jmarianoArticle: 100573
I wrote the FSM's ina very high level way, to allow the tools to generate their own data path as necessary. Therefore different states may have mulitply operations within them that might be able to share the same multiplier resource, since the two states are disjoint.Article: 100574
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1144859088.483052.301100@u72g2000cwu.googlegroups.com... > it all works (should work) with S3e, but you would still to write your > own software to handle the SPI memory > > antti The information I've gathered so far suggests readback is available through Slave Parallel or JTAG modes. I don't seem to find internal readback capability. To read back through the JTAG port, I'd expect to have to interface to the JTAG pins externally through four other I/O. Can I configure with Slave Serial and do the readback through JTAG? If I'm trying to do this on board as opposed to through the Xilinx tool suite I don't see how "it all works" with the info I've perused so far.
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Compare FPGA features and resources
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