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The whole system is intended for a quick check if self-made PCI devices work. The goal is to use Nios as the Host processor and to use a PCI Host-Bridge to interface Nios to the PCI bus. The board should be working without a PC (standalone). This means that the Nios core is the only bus master in the system and should do the configuration cycles etc. in software. You can interpret this as if I'm making my own mini motherboard, only using PCI. The software running on the Nios core should walk down the PCI bus to detect any attached device and do the rest of the configuration and other read/write cycles. Sander "Nial Stewart" <nial@nialstewartdevelopments.co.uk> schreef in bericht news:4a3rr7Fr53b6U1@individual.net... > "Sander & Stieneke Odekerken" <sanderA_en_stienekeB@wanadooC.nlD> wrote in > message news:443be5db$0$117$dbd4d001@news.wanadoo.nl... >> Another problem I'm facing is that I can't read/write any information >> from/to the configuration space of the internal PCI master/target device >> or >> any other (external) PCI device (actually I didn't tried that because I >> first want to know if it works before I blow up the device :-) ). Should >> configuration be done in VHDL or can >> it be done in software? If it is possible using software, do I have to >> write >> to the Avalon bus or directly to the PCI Bus Access slave port? Do you >> have >> any examples or reference of how to do a configuration by software? > > > Sander, > > I presume this is so you can insert a board with a NIOS core into a > system that has a PCI bus? > > The configuration registers are normally initialised by whatever's driving > the PCI bus. > > As an example in a PC when it boots up it walks down the PCI bus detecting > devices and allocating memory addresses etc to them. You probably > shouldn't be > trying to write to these from the other side of the PIC interface. > > > > Nial. >Article: 100576
What happens to Xilinx ftp with the following URL ftp://ftp.xilinx.com/pub/ftpfiles.htm Most of the files can not be downloaded. Have they been moved? If they have, where is the new URL? HendraArticle: 100577
John_H wrote: > The information I've gathered so far suggests readback is available through > Slave Parallel or JTAG modes. I don't seem to find internal readback > capability. To read or write the SPI eeprom after config, you bit-bang the SPI pins from the fpga like any other IO pin. All of the SPI pins are general purpose IO pins. Or perhaps I don't understand the question. Alan NishiokaArticle: 100578
Hendra wrote: > What happens to Xilinx ftp with the following URL > ftp://ftp.xilinx.com/pub/ftpfiles.htm > > Most of the files can not be downloaded. Have they been moved? Works for me. Are you sure your firewall isn't blocking ftp access? google "passive ftp" for information on active vs. passive ftp and firewalls. Alan NishiokaArticle: 100579
"Alan Nishioka" <alan@nishioka.com> wrote in message news:1144865199.566139.147490@u72g2000cwu.googlegroups.com... > John_H wrote: >> The information I've gathered so far suggests readback is available >> through >> Slave Parallel or JTAG modes. I don't seem to find internal readback >> capability. > > To read or write the SPI eeprom after config, you bit-bang the SPI pins > from the fpga like any other IO pin. All of the SPI pins are general > purpose IO pins. > > Or perhaps I don't understand the question. > > Alan Nishioka To bit-bang the SPI pins through external software that's used to configuring FPGAs through Slave Serial configuration, a new software driver that's SPI NAND capable would heve to be developed to provide "new" bit banging. If I left it in the hardware realm, reprogramming the SPI based on the FPGA's *own configuration* would be desirable, leaving the NAND programming details to me in the hardware. My need becomes reading back the configuration from the device itself by the device while the device is operating.Article: 100580
sachink...@gmail.com wrote: > Im trying to access the FAT table in a compact flash. > compact flash memory starts with > > - a boot sector of 512 bytes > - then FAT 1 of 512 bytes > - FAT 2 > - Data > CAN ANYONE TELL ME HOW TO PRINT THE FAT TABLE FROM MY COMPACT FLASH > ??????????????? There may be reserved sectors between the boot sector and fat1. http://www.compuphase.com/mbr_fat.htm has lots of good information. I found it with google "compact flash partition table" Alan NishiokaArticle: 100581
basically if you just keep generating CCLK from FPGA then the original bitstream will appear after the spi flash "wraps around" so if you just toggle cclk and monitor for the bitstream signature then you get the original fpga bitstream read back :) anttiArticle: 100582
John_H wrote: > If I left it in the hardware realm, reprogramming the SPI based on > the FPGA's *own configuration* would be desirable, leaving the NAND > programming details to me in the hardware. > > My need becomes reading back the configuration from the device itself by the > device while the device is operating. So you want to have an fpga read its own configuration from itself and program an SPI eeprom? Won't that allow it to program itself, and eventually take over the planet? Isn't a lot of information missing from such a readback, such as all the register init states and the bram init? Alan NishiokaArticle: 100583
I think you have totally missed the point. posting a link to the FAQ in answer to questions is (1) smarter if the same question pops every now and then (2) makes it show up less often in future (3) can give a more comprehensive answer (4) makes more people aware of the FAQ. It works like this in many other groups, and it works rather nice for Mike Treseler in this newsgroup too :) about the spam part, well... if you start posting things that hurts their business, believe me they gonna notice. and even if they dont, it is still better to have a list of good suppliers at hand > People with poor net hygiene don't read FAQ's either. Saying that was very stupid of you. Back to the subject. In either case, it is always nice if people contribute and try to extend the FAQ. BrunsArticle: 100584
On 12 Apr 2006 12:07:17 -0700, burn.sir@gmail.com wrote: >> People with poor net hygiene don't read FAQ's either. > >Saying that was very stupid of you. Nice. You've managed to insult a person who's not only maintained a high-quality FAQ, but who's spent considerable time posting valuable information to this newsgroup. Stop worrying about newsgroup spam; I think you need to get your own house in order first. Bob Perlman Cambrian Design WorksArticle: 100585
Was the Xilinx powerpc core ever produced for the Vertex II device?Article: 100586
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1144867908.073506.152680@e56g2000cwe.googlegroups.com... > basically if you just keep generating CCLK from FPGA then the original > bitstream will appear after the spi flash "wraps around" so if you just > toggle cclk and monitor for the bitstream signature then you get the > original fpga bitstream read back :) > > antti 1) set switch to Slave Serial 2) (re)configure device with software 3) tell device to reprogram SPI flash with current configuration 4) set switch to SPI programming 5) no software programming required I don't want to reprogram the SPI memory with the original SPI contents.Article: 100587
noway! you cant cheat! there is software programming involved! xilinx is maybe adding indirect spi flash programming in ISE 9 or 10, so if you wait... Antti PS both Altera and Lattice support direct SPI flash programming from Quartus/ispLEVERArticle: 100588
"Alan Nishioka" <alan@nishioka.com> wrote in message news:1144867944.717365.44000@j33g2000cwa.googlegroups.com... > John_H wrote: >> If I left it in the hardware realm, reprogramming the SPI based on >> the FPGA's *own configuration* would be desirable, leaving the NAND >> programming details to me in the hardware. >> >> My need becomes reading back the configuration from the device itself by >> the >> device while the device is operating. > > So you want to have an fpga read its own configuration from itself and > program an SPI eeprom? Won't that allow it to program itself, and > eventually take over the planet? > > Isn't a lot of information missing from such a readback, such as all > the register init states and the bram init? > > Alan Nishioka *visions of Terminator dance in my head* Whether there's missing readback info is an *excellent* question. I just assumed that the configuration chain included all the original info; the BlockRAM is one point where my assumption wouldn't make a lot of sense. So, readback without the CAPTURE... does it include the initial REG values? Does it include the current (not initial) contents of SRLs and CLB SelectRAM? Does it include current BlockRAM contents? ______ I'm suspecting I would do much better to have software interface to the FPGA as if it were bit-banging in the Slave Serial mode but without reprogramming the device. This gives me a system-sourced .bin file that I can push into the SPI through my own FPGA routines.Article: 100589
Scott Willis wrote: > Was the Xilinx powerpc core ever produced for the Vertex II device? > Yes, this family was called Virtex-II Pro and has been in volume production for quite some time now. EdArticle: 100590
"Scott Willis" <scot.willis@gmail.com> wrote in message news:1144869827.134075.105090@i40g2000cwc.googlegroups.com... > Was the Xilinx powerpc core ever produced for the [Virtex] II device? See Virtex-IIProArticle: 100591
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1144871856.409373.98500@e56g2000cwe.googlegroups.com... > noway! you cant cheat! > > there is software programming involved! ----- I realize what I'll be implementing in the FPGA to interface between the existing FPGA programming drivers in our operating system and the SPI will be "software" in a sense. I don't maintain and expand the OS and those folks are sometimes too burdened to take on extra "nice to have" tasks, hence my desire to find a reprogramming interface that supports both bit-bang Slave Serial and reprogramming of the SPI flash for development (dozens of platforms). ----- > xilinx is maybe adding indirect spi flash programming in ISE 9 or 10, > so if you wait... > > Antti > PS both Altera and Lattice support direct SPI flash programming from > Quartus/ispLEVER ----- Direct programming from the parallel cable or direct programming through some FPGA interface? I'm looking for a solution on everyones' desks, not just the FPGA developer's. I can use the XSPI utility separate from Project Navigator without concern.Article: 100592
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:q8d%f.5598$kg.1095@news02.roc.ny... > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1144871856.409373.98500@e56g2000cwe.googlegroups.com... >> noway! you cant cheat! >> >> there is software programming involved! > ----- > I realize what I'll be implementing in the FPGA to interface between the > existing FPGA programming drivers in our operating system and the SPI will > be "software" in a sense. I don't maintain and expand the OS and those > folks are sometimes too burdened to take on extra "nice to have" tasks, > hence my desire to find a reprogramming interface that supports both > bit-bang Slave Serial and reprogramming of the SPI flash for development > (dozens of platforms). > ----- >> xilinx is maybe adding indirect spi flash programming in ISE 9 or 10, >> so if you wait... >> >> Antti >> PS both Altera and Lattice support direct SPI flash programming from >> Quartus/ispLEVER > ----- > Direct programming from the parallel cable or direct programming through > some FPGA interface? I'm looking for a solution on everyones' desks, not > just the FPGA developer's. I can use the XSPI utility separate from > Project Navigator without concern. > direct means from vendors tools using standard jtaga no that X_SPI s*** - whatever you are looking for you have out-smarted me! what is that magic thing that is one everones desks and what could allow SPI programming ?? anyway nomatter what it is, as I have said its its very likely NO NO NORWAY. AnttiArticle: 100593
"Antti Lukats" <antti@openchip.org> wrote in message news:e1jrgd$59j$1@online.de... <snip> > whatever you are looking for you have out-smarted me! what is that magic > thing that is one everones desks and what could allow SPI programming ?? > > anyway nomatter what it is, as I have said its its very likely NO NO > NORWAY. > > > Antti The magic thing I have is the target FPGA in a system that has a processor with our own OS drivers with ethernet and USB connectivity that are live before the FPGA is ever programmed. I couldn't reconfigure the FPGA's SPI configuration memory on everybody's desk without external tools (JTAG, ByteBlaster, Parallel Cabe IV) if the FPGA were the only smarts on the board.Article: 100594
Reading this in a different way, Xilinx does not supply a soft PPC core. The 405PPC core is a full ASIC implementation by IBM, for Xilinx, in the Virtex II Pro Family of devices. This hard core is also the lowest power 405PPC in 130nm technology of all of the cores available in 130nm. Austin Ed McGettigan wrote: > Scott Willis wrote: > >> Was the Xilinx powerpc core ever produced for the Vertex II device? >> > > Yes, this family was called Virtex-II Pro and has been in volume > production for quite some time now. > > EdArticle: 100595
Hello,
I'd just like to announce, that I've published three Verilog modules,
which use a common FIFO to create another, modified FIFO. These modules
are actually wrappers.
There are two objectives for this:
1. Improving timing by putting registers on rd_en and dout, while
presenting the same signal interface to the design which uses the
wrapped FIFO. In other words, if a FIFO becomes involved in critical
paths, this could be a quick solution (at the cost of some extra
logic).
2. Using a regular FIFO to make a FWFT (First Word Fall Through) FIFO.
I wrote these wrappers as a result of abandoning the Virtex-4's FIFO16,
being left with sliced-based FIFO's, which were too slow.
The material can be found at http://www.billauer.co.il/reg_fifo.html
Regards,
Eli
Article: 100596sachink321@gmail.com wrote: > Hi > Im trying to access the FAT table in a compact flash. > from what i have understood > > i have got sandisk 256mb compact flash > > compact flash memory starts with > > - a boot sector of 512 bytes > - then FAT 1 of 512 bytes > - FAT 2 > - Data > > > i want to print the FAT table > > how iam i doing that > is like this > > Read a sector using LBA mode > set command register to 0x20 > and then i need to give LBA logical block address > LBA usually starts from 0 > so i assumed that LBA for FAT table is gonna be at address 1 > so i gave LBA address as 1 > > this program is made of assumptions > and the program is not working > > CAN ANYONE TELL ME HOW TO PRINT THE FAT TABLE FROM MY COMPACT FLASH > ??????????????? > First off, you need to set the parameter registers (sector count, the the LBA registers (aka cylinder lo, cylinder hi and sector, and the drive/head register) BEFORE you issue the read sector command. The command uses the values present in the registers at the time the command is issued. The location of the FAT table depends on the file system under which the CF was formatted. The FAT is not an inherent characteristic of a CF card, rather it is data written to the card when the card is formatted.Article: 100597
John_H wrote: > Greetings, > > I'd like to program my Spartan3E with an SPI memory normally. For > development at my desk, I understand I can add a header to allow IMPACT to > configure the SPI flash memory. > > We have many legacy designs that bit-bang the FPGA to program it in slave > serial mode allowing (re)configuration by software, typically with no > configuration RAM in the first place. > > Rather than getting the software folks to write the SPI driver to reprogram > the SPI memory through an equivalent bit-bang, I'd be interested in a > readback of a slave-serial programmed FPGA by the FPGA while the FPGA is > active to directly program the SPI memory with my own internal routines. > > --> Any ideas on whether I can accomplish this or how best to approach it? > > While writing this post I came to realize the external readback would be on > the passive slave port, not the SPI side so the SPI persistence setting > isn't an issue. But will I need to double-up the passive serial port to do > the readback through other I/O pins? I'm sorry, I don't follow what you're trying to do here. However, if it helps, I can point to a couple of potential "helper" designs. For the Spartan-3E Starter Kit board, there is a reference design that allows you to program the SPI serial Flash via the 9-pin RS-232 port on the board. The FPGA contains an embedded PicoBlaze controller that performs the actual programming. The reference design and a short overview presentation are available at the following link. PicoBlaze SPI Flash Programmer for the Spartan-3E Starter Kit Board http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm#picoblaze_spi_flash_programmer The board documentation, if it helps, is available at the following link. The chapter on SPI Flash also talks about the XSPI option, which uses an external header and a parallel-to-JTAG cable. The document is rather large because it also contains the board schematics. UG230: Spartan-3E Starter Kit Board User Guide [11 MB] http://www.xilinx.com/bvdocs/userguides/ug230.pdf This is also a reference deisgn using MicroBlaze, linked below. Using SPI Serial Flash on the Xilinx Spartan-3E Starter Kit Board http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm#serial_flash Does any of this help your cause? --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100598
Eric Smith wrote: > I was finally able to order a Spartan 3E Starter Kit from Avnet late > last week. (Before that the Xilinx site said that it was orderable > from Avnet, but the Avnet site said that it was not.) It arrived > today, and the preprogrammed demo works fine. I haven't yet loaded > any of the other demos, or tried to program any of my own designs. > > The kit does noot come with a printed copy of its user's guide, but > that's not a problem since the PDF is available for download from > the Xilinx site, as are the schematic and gerber files: > ttp://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?&key=HW-SPAR3E-SK-US [ ... snip ...] I'm happy ot hear that these boards are finally make their way through the pipeline! I just wanted to provide a few updated links. The links that you mentioned work, but these are a little more direct. Spartan-3E Starter Kit Board Landing Page http://www.xilinx.com/s3estarter User Guide (it's 11 MB because it contains annotated board schematic drawings) http://www.xilinx.com/bvdocs/userguides/ug230.pdf Spartan-3E Reference Designs http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm There are more reference designs on the way. Stay tuned. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100599
Roger Bourne wrote: > Hmmm.... > > Timing constraints ? Are *.ucf files created for a *typical* FPGA > design ? > I cannot seem to > recall if timing constraints (*.ucf file) are user-entered OR IF > timing-constraints entry is typically ignored and the fpga typically > generates it for the user. > (...I am in the process of going over the help files as I am typing > this post...) > Please advise > -Roger Here's an old "buried gem" on the Xilinx website: ftp://ftp.xilinx.com/pub/documentation/M1/timingcsts1.5.zip Slide 45 of that document answers your question. Timing constraints can be entered by the user in two places: 1) Pre-synthesis ( in .xcf for XST, ??? for your synth tool ). These constraints are propagated forward to the back-end tools (via .ngc for XST, via .ncf for edif flows). 2) Post-synthesis in the .ucf Post-synthesis UCF constraints have priority over pre-synthesis (NGC or NCF) ones. Here's a caution if you're going to use UCF constraints, from a toe-stub I ran into a short time ago. (http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/fb6b0258a515c5bc/#) Nobody here at c.a.f. had anything to suggest (even our FAE was stumped), I finally worked it out (like most things, it's obvious in hindsight). I had a clock enable (CE_10MHz), derived from a decode of a counter running at 80MHz, and constrained in the UCF as shown on slide 36 of the ppt document referenced above. The trouble I had was that the TNM timegroup for the CE_10MHz signal was missing many elements it should have had. The reason was that synthesis re-partitioned logic such that for those missing elements, the CE_10MHz signal had been absorbed into a LUT, and no longer existed. Thus, the path tracing process could not find it and add those elements to the time group. This was fixed by changing the source of CE_10MHz to be a FF's output, instead of a decode from a counter, which prevented it from being absorbed. This was not the entire fix though... the synthesis tool may introduce register duplicates, which will have different net names. I'd assume pre-synthesis constraints are properly expanded by synthesis tools to cover any register duplication or balancing that may occur, but have not tested this yet. The manuals don't explicitly say they do. Does anyone have any experience there?
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