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Falk Brunner <Falk.Brunner@gmx.de> wrote: >Nico Coesel schrieb: > >>>I wish they'd tell us a little more about the actual electrical >>>behavior of the i/o bits. I mean, Altera and Actel and everybody else >>>has snooped all this out already. >> >> >> Xilinx is good with keeping information under their hat. One of the > >Really? I doubt it. And NO, Iam not paid by Xilinx ;-) Another example: Several years ago I made JTAG programming routines for a Spartan 2 according to Xilinx application notes (verified bit by bit with a logic analyzer). For some reason these routines didn't work on a Spartan 2E device. I got it working in the end by thinking logically on how the device should be initialized to accept a configuration, but the result is definitely not according to Xilinx's documentation. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 99976
You can keep both, since you can set up the correct environment variables using shell scripts located at the root directory of you're installation. On the other hand, I strongly recomend you to make a backup of your 7.1 projects before opening them with version 8.1, since the project files are upgraded and there's theoricaly no way back if something bad happens... Manu Nitesh a écrit : > I want to upgrade my EDK and ISE to 8.1 version from 7.1 versions.I am > using linux OS. > I want to ask those who have already upgraded to edk 8.1 in linux.Do I > need to uninstall the 7.1 version before going ahead with the 8.1 > installation or can I just go ahead and install 8.1 and then change the > $XILINX and $XILINX_EDK Paths? > Thanks, > Nitesh >Article: 99977
I just found where they spec the IO signals used for configuration. In the table for the various IO standard, the row for LVCMOS25 has a footnote that says this is the standard used for the dedicated configuration IOs. So it is in the data sheet, but you have to know where to look for it. Someone might consider making this easier to find. It should be somewhere that it can be found when looking for the signal group rather than having to know to look for the IO standard and then finding the footnote. rickman wrote: > I just had a design review on my board and I was zinged for using > resistors to pull the M[2:0] pins to power or ground. I have always > done it that way and do not see a reason to change. But the Xilinx > documents were shown to me, specifically XAPP453, where they clearly > show the pins being pulled hard to power or ground. > > I can't find any info in the data sheet on the threshold levels on > these pins (or JTAG), so I can't dispute the argument that I should > follow the app note. > > The same person is saying that an XAPP (which I can't find) indicates > that the various JTAG signals need to be pulled low by resistors rather > than high. I have always used resistors to pull TCK and TMS high to > assure that the JTAG port was not put in an invalid state. The TDI and > TDO signals were not important. I am aware that these pins are 2.5 > volts. Is that why they are shown pulled to ground, to avoid any > confusion about *which* high? Any official source of info on this? > > I have looked on the Xilinx web site, but there are dozens of documents > that score a hit on JTAG and Spartan and I don't see any that answer > the questions.Article: 99978
zhangxun0501@gmail.com wrote: > but in the sit of xilinx , it said the hwicap support the virtex4-fx Have you tried adding virtex4 to the list of supported architectures in: EDK/hw/XilinxProcessorIPLib/pcores/opb_hwicap_v1_00_b/data/opb_hwicap_v2_1_0.mpd That is, change OPTION ARCH_SUPPORT = virtex2:virtex2p to OPTION ARCH_SUPPORT = virtex2:virtex2p:virtex4 I don't have 8.1 and am not using hwicap, so I have not tried this and don't know if it will work. Alan NishiokaArticle: 99979
Can anybuddy tell me what are the most common methods of grabing discrete from out side world. These signals have no vaid and are asynchronous ThanksArticle: 99980
RobJ wrote: > You're right about the M[2:0] pins. No reason to get rid of the resistors, > but they're not needed. The only caveat for pulling high is that these pins > are powered by VCCAUX, so pull (or tie) them to 2.5V. As for pull downs, > these pins are weakly pulled up internally, so if you pull them low just > don't use a huge value. Don't read too much into XAPP453. Those are just > logical drawings anyway. (By the way, in Spartan-3E the M[2:0] pins are > general-purpose I/O and are not powered by VCCAUX.) But if M[2:0] can be outputs, you really *should* use resistors, right? If you misconfigure the FPGA you could have outputs driving gnd or power. Alan NishiokaArticle: 99981
Hi Alan, This would only work if the ICAP in Virtex4 operated the same way as in Virtex2/Virtex2p. Maybe they are not the same and this is why the ARCH_SUPPORT doesn't include Virtex4. Paul Alan Nishioka wrote: > > zhangxun0501@gmail.com wrote: > > but in the sit of xilinx , it said the hwicap support the virtex4-fx > > Have you tried adding virtex4 to the list of supported architectures > in: > EDK/hw/XilinxProcessorIPLib/pcores/opb_hwicap_v1_00_b/data/opb_hwicap_v2_1_0.mpd > > That is, change > OPTION ARCH_SUPPORT = virtex2:virtex2p > to > OPTION ARCH_SUPPORT = virtex2:virtex2p:virtex4 > > I don't have 8.1 and am not using hwicap, so I have not tried this and > don't know if it will work. > > Alan NishiokaArticle: 99982
"Alan Nishioka" <alan@nishioka.com> wrote in message news:1143844931.843840.279800@i39g2000cwa.googlegroups.com... > RobJ wrote: >> You're right about the M[2:0] pins. No reason to get rid of the >> resistors, >> but they're not needed. The only caveat for pulling high is that these >> pins >> are powered by VCCAUX, so pull (or tie) them to 2.5V. As for pull downs, >> these pins are weakly pulled up internally, so if you pull them low just >> don't use a huge value. Don't read too much into XAPP453. Those are just >> logical drawings anyway. (By the way, in Spartan-3E the M[2:0] pins are >> general-purpose I/O and are not powered by VCCAUX.) > > But if M[2:0] can be outputs, you really *should* use resistors, right? > If you misconfigure the FPGA you could have outputs driving gnd or > power. > > Alan Nishioka > That only applies to Spartan-3E. On Spartan-3, which the OP was asking about, the M[2:0] pins are dedicated configuration inputs powered from VCCAUX. But even in Spartan-3E, the pins can only be outputs if you use them in your design as outputs. If they are not used they default to inputs with weak pullups after configuration like all other unused I/O, in which case direct connection to power or GND is fine. And if they ARE used as functional pins you obviously would NOT tie them to power or GND. It all works out in the end. RobArticle: 99983
Hi Billu, The "Using High Speed Serial MGTs with the Aurora IP" Quickstart for the XUPV2P board at http://www.xilinx.com/univ/xupv2p.html does use Chipscope to monitor the data being sent and received over the Aurora link. There is a Chipscope evaluation available for download at http://www.xilinx.com/ise/optional_prod/cspro.htm Paul billu wrote: > > Hi There, > > I've managed to compile a sample aurora protocol design using > Coregenerator, and simulated it using ModelSim. I have a couple of > questions at this point. > > I'm trying to download the design onto the board using IMPACT. All the > processes (Program, Get Device ID, Read Status Register.. ) seem to > work except the Verify process. Is that something that I should be > concerned about.Can I assume that design has been uploaded to the > board, once I run program, and it says program successful? > > How do I test the design on the board. Is there a simple to way to > demonstrate a link between two transceivers and monitor the status. I'm > guessing theres something possible with Chipscope, but I dont have > access to the program. > > Thx in advance, > BilluArticle: 99984
Hello John, > > And we sure will be more careful about oscillators and clock > distribution in the future... everything's getting too fast. It was > probably the move of the ground plane to layer 5 of 6 (the clock is > mostly routed on 6), and the fast/weak xo, that caused the problem. > Clock-on-the-bottom isn't ideal for noise immunity, either. > If you don't have one already get a fast FET probe. I find that an indispensable tool to check fast clocks and stuff. The usual resistive divider into a coax works as well but it's more clumsy. Good FET probes come with neat low inductance connection tools. > Here's the gadget, but you can't see anything relevant in this pic, > just barely the last FPGA in the clock string at the top... > > http://www.highlandtechnology.com/DSS/V470DS.html > > The xo is near the bottom, between the metal cover and the eprom, the > dark thing poking out. > Nice. You guys sure do clean mechanical designs. At one client we provided a phone jack at the front through which the boards could be diagnosed and SW-upgraded. We even had some where you could connect a touch-tone phone and use its keypad to change some settings. That was in the early 90's. Nowadays I guess it would be a USB jack or, gasp, a Bluetooth link. Regards, Joerg http://www.analogconsultants.comArticle: 99985
Hi all,
I want to open a lot of files and read data to reg.
something like
//-----code--------
$readmemh(".\pattern\0.dat",inmem0);
$readmemh(".\pattern\1.dat",inmem1);
...
$readmemh(".\pattern\49.dat",inmem49);
//-----code end----
I want to use something like strcat() in C to concatenate the string.
So, I can use a loop to replace large block of code above.
Is there any method to do this work in Verilog?
Any suggestions will be appreciated!
Best regards,
Davy
Article: 99986Hi all, I am new to hierarchical FSM design. Is there any paper or guideline for design hierarchical FSM? Any suggestions will be appreciated! Best regards, DavyArticle: 99987
"Davy" <zhushenli@gmail.com> wrote in message news:1143855889.597080.95870@v46g2000cwv.googlegroups.com... > Hi all, > > I am new to hierarchical FSM design. > Is there any paper or guideline for design hierarchical FSM? > > Any suggestions will be appreciated! > Best regards, > Davy > Google. KenArticle: 99988
Stratix has fast fabric on two sides of the chip for handling the SERDES interface. The internal logic fabric can NOT handle these high serialized data rates. One must de-serialize the data, do whatever logic is necessary, and send it through a SERDES transmitter on the other side of the FPGA. Altera provides these SERDES transmit and receive functions within their Mega Wizard tool box. These packaged functions take care of all of the timing needed to either receive or transmit the high speed serial data. It sounds like you have 2 SERDES channels coming in and one going out; and you need to select which input gets routed to the output--the FPGA is the right solution for his situation. If the input and output SERDES channels have the same make up (lanes and bits / lane) and there is nothing you have to do with the data, then the design is fairly staright forward. Deserialize both of the input SERDES channels (using the MegaWizard function) into a mux; and then connect the output of the mux to the input of the SERDES transmitter (MegaWizard function). Take care, Rob "pinku" <praveenkumar.bm@gmail.com> wrote in message news:1143824706.197533.207620@u72g2000cwu.googlegroups.com... > Hello Groups, > > I have a 1Gbps SERDES output from the Network processor. But as i have > 2 SERDES signal coming from the back plane, depending of SEL line i > have to connect one of the SERDES to network processor. So i am using > FPGA to interface this, which takes a SERDES input and I have FIFO for > transmit FIFO, recieve FIFO and FIFO controller and this FIFO is again > connected to another SERDES which in turn connect to the Backplane. So > i need 4 SERDES for implementing it. Will this intermediate Logic > create for end to end SERDES data transfer ? Is there any other way of > implementing this logic? I am planning to use Stratix GX FPGA. > > Please let me know your suggestion, > waiting for your reply, > Kumar >Article: 99989
On Sat, 01 Apr 2006 01:17:27 GMT, Joerg <notthisjoergsch@removethispacbell.net> wrote: >Hello John, > >> >> And we sure will be more careful about oscillators and clock >> distribution in the future... everything's getting too fast. It was >> probably the move of the ground plane to layer 5 of 6 (the clock is >> mostly routed on 6), and the fast/weak xo, that caused the problem. >> Clock-on-the-bottom isn't ideal for noise immunity, either. >> > >If you don't have one already get a fast FET probe. I find that an >indispensable tool to check fast clocks and stuff. The usual resistive >divider into a coax works as well but it's more clumsy. Good FET probes >come with neat low inductance connection tools. We have a TDS3052 (500 MHz) scope with the 1 GHz fet probes. Next would be the big ole 7104 (1 GHz) analog scope, with a 1 GHz fet probe. Our ultimate weapon is an 11801 with an SD-14 sampling head, .25 pF and 3 GHz at the probe tip. I love scopes. Interestingly, the fpga glitch stopped when the TDS probe was touched on the clock pin of the 2nd FPGA, which added about 0.5 pF. JohnArticle: 99990
I can't tell if you are still asking something or got it all figured out. Hope its the latter. Since no one else is chiming in, I'll just suggest again, if necessary, to get one of your processors to have it enitre address space on chip, then you don't need an elf file for it. If it all lives on chip just make sure the program you want is set to initialize the BRAMs of that PPC. Now that program will be part of the bitstream. Use the other ppc's elf to make the ace file you want. That should do it. Hope it all works out for you...Article: 99991
Hi all, I have a question pertaining to an Atmel microcontroller. I have a AT89C2051 flash microcontroller. I just wanted to verify that once I program the chip with a universal programmer I have, I can turn off all power to the chip without losing the data right? So the next time I apply power to the chip, it will still function as programmed right. thank you. Regards, PhilArticle: 99992
In article <p6nq22l4nf53kqanjhu7d4ojn70nb933nm@4ax.com>, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: [....] >I wonder if anyone has ever kluged a bga layout, sort of like one of >those jellyfish with a thousand tentacles. More likely it would be a costly blind-via PCB that sits between the BGA and the base PCB. (Vomit) When I do a board with CPLD on it, I sometimes wire the unused pins together in some random arrangement. You can't get fast signals out and back but you can do a few slow ones. On my current project I'm up to 380 out of 512 used. This is making me nervous. -- -- kensmith@rahul.net forging knowledgeArticle: 99993
swimmerphil1@gmail.com wrote: > Hi all, > I have a question pertaining to an Atmel microcontroller. I have a > AT89C2051 flash microcontroller. I just wanted to verify that once I > program the chip with a universal programmer I have, I can turn off all > power to the chip without losing the data right? So the next time I > apply power to the chip, it will still function as programmed right. > thank you. Yes. If that was NOT true, how do you imagine they would be used ? :) -jgArticle: 99994
Ken Smith wrote: > In article <p6nq22l4nf53kqanjhu7d4ojn70nb933nm@4ax.com>, > John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > [....] > >>I wonder if anyone has ever kluged a bga layout, sort of like one of >>those jellyfish with a thousand tentacles. > > > More likely it would be a costly blind-via PCB that sits between the BGA > and the base PCB. (Vomit) > > When I do a board with CPLD on it, I sometimes wire the unused pins > together in some random arrangement. You can't get fast signals out and > back but you can do a few slow ones. > > On my current project I'm up to 380 out of 512 used. This is making me > nervous. Then I'll put the hex on this, by asking : " What could marketing possibly dream up, that could use more than the 132 spare pins !?" :) -jgArticle: 99995
faraz.khan@nssi.us wrote: > HI, > > Q1.What does FIFO depth mean. How many meters under water it's operating. ( Feet in US ) > Q2.How can i use FIFO to register the signals comming out of FPGA. Be sure it signs in before giving it the key to the memory pool. > Q3.How would i address the FIFO. Hello FIFO! > Q4.Can i use Shift register to save incomming outside signals. Only if they really want to be saved. Prayer helps. > Q5.How can i address Shift registers. Howdy! (Shift registers are far less formal) > Q6.What is the difference b/w FIFO and shift register About 2 pounds. ( 1 Kg outside US ) No Homework! > I am trying to design a I/O logic how can i use FIFOs or shift > registers in it Review the excellent app notes to be found on vendors web sites. For Xilinx, you might start with xapp465, then go on to xapp256...they have a very good pile of useful information. You might end up learning more than just the answers to your questions. (sorry folks, it's been a 65+ hour work week) > Thanks > > FarazArticle: 99996
> Interestingly, the fpga glitch stopped when the TDS probe was touched > on the clock pin of the 2nd FPGA, which added about 0.5 pF. I hate when that happens :) "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:0fqr2215rti8fahr3s1li78ppg9pbqf19t@4ax.com... > On Sat, 01 Apr 2006 01:17:27 GMT, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >>Hello John, >> >>> >>> And we sure will be more careful about oscillators and clock >>> distribution in the future... everything's getting too fast. It was >>> probably the move of the ground plane to layer 5 of 6 (the clock is >>> mostly routed on 6), and the fast/weak xo, that caused the problem. >>> Clock-on-the-bottom isn't ideal for noise immunity, either. >>> >> >>If you don't have one already get a fast FET probe. I find that an >>indispensable tool to check fast clocks and stuff. The usual resistive >>divider into a coax works as well but it's more clumsy. Good FET probes >>come with neat low inductance connection tools. > > > We have a TDS3052 (500 MHz) scope with the 1 GHz fet probes. Next > would be the big ole 7104 (1 GHz) analog scope, with a 1 GHz fet > probe. Our ultimate weapon is an 11801 with an SD-14 sampling head, > .25 pF and 3 GHz at the probe tip. I love scopes. > > Interestingly, the fpga glitch stopped when the TDS probe was touched > on the clock pin of the 2nd FPGA, which added about 0.5 pF. > > John > >Article: 99997
Sorry Davy, but I don't know the answer to your problem, and I may be criticized for posting but.... What are you talking about Jamie? Windows registry? Did you happen to read the question? Or did you happen to notice the forum you were in? Dave is posing a Verilog question and the reg he is referring to is not the Windows registry what so ever!! So please don't do US any favors by replying with something totally off base! And it's noob, not nob. And it's might, not mite. Mites are bugs. Not software bugs! Good luck with your query Davy!! There is probably some SystemVerilog or PLI stuff that would do the trick...Article: 99998
I have a digital receiver module needed in a MicroBlaze system that I coded in Verilog. The module is responsible for accepting, parsing, and storing receive data from a part our company makes. The part is responsible for driving the clock and data at 26 MHz. Our internal clock on our MicroBlaze embedded system is 38.4 MHz. I desinged the block as two separate modules. The first module is basically a shift register that clocks in the serial data from the part when an enable line goes high (also driven by the external part). This module works in the 26 MHz clock domain. The second module is a state machine that accepts 96-bit chunks of data from the previous module, parses that data based on the format being sent (a MBlaze software register setting), and stores it in 32-bit chunks in internal block ram. This module works in the 38.4 MHz clock domain. So the part sends the enable signal and that tells the 26MHz shift register to start clocking in data. After 96-bits are received, the module sends a trigger to the state machine logic. The state machine is in a WAIT condition - having already intitalized the data format via a software write. The state machine grabs the 96-bit chunk, parses it into 1 or 2 32-bit chunks (depends on format), discards the rest, and stores the data in block RAM. I threw it in our MicroBlaze project, built the design, and started testing. I have a pattern generator set up to simulate the protocol that the extrenal part will be responsible for providing (our part is in fab). I have to use the EDK software debugger in order to see the data stored to memory. Everything appeared to be working fine. However, after increasing the data in the pattern, it was obvious that random errors were occuring in the data stored to RAM. There would occassionlly be incorrect values stored. I had the data coming in as a binary count and sometimes the count would glitch. It didn't occur often, but we can't have any errors. So, I tried two things. The first was to put some synchronization flip flops in the state machine. Initially I had my concerns about crossing clock domains, but since I was going from a slower one to a faster one I didn't worry much. I put a couple each for the data being passed from the 26 MHz clock domain, and for the trigger being passed from the 26 MHz clock domain. After building this, the problem still occurred. I then put a KEEP_HIERACHY constraint on the top level module that instantiates the two modules discussed. Low and behold, that worked. I have tested extensively and there have been no errors. Does anyone have any insight into why keeping the hierarchy intact works? I always try to design correct hierarchies in my modules...meaning hierarchy that makes sense. And all signals are registered at module boundaries. To me, the design discussed above is well-partitioned. I don't know what XST would "optimize" when the KEEP_HIERACHY was NOT specified. Just curious if anyone had any input. I didn't check to see what area penalties, if any, occured after placing the constraint. I doubt it would make much difference. Thanks!Article: 99999
Davy wrote:
> Hi all,
> I want to open a lot of files and read data to reg.
>
> something like
> //-----code--------
> $readmemh(".\pattern\0.dat",inmem0);
> $readmemh(".\pattern\1.dat",inmem1);
> ...
> $readmemh(".\pattern\49.dat",inmem49);
> //-----code end----
>
> I want to use something like strcat() in C to concatenate the string.
> So, I can use a loop to replace large block of code above.
> Is there any method to do this work in Verilog?
>
> Any suggestions will be appreciated!
> Best regards,
> Davy
the registry is not your play ground.
it is not your database of life long collections.
simply put, its use should be limited to storing
data that is truly needed via other apps or tools
of yours to access information that other wise would
be hard to find..!
what this means is, you put things like file paths
to where you mite be storing large segments of data.
please don't do us any favors by passing around
bad idea's for other nobs to follow.
--
Real Programmers Do things like this.
http://webpages.charter.net/jamie_5
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Compare FPGA features and resources
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