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John Larkin wrote: > On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote: > > > >So the Fpga to Fpga routing worked - good. > > That's not what we did. We designed a clock deglitcher to go inside > the FPGA. Enough propagation delays to cover the dwell at the switching threshold, and a state machine to make sure that the clock only changes state once in that interval? -- Bill Sloman, NijmegenArticle: 99776
Hi Marco,
> If use use the linker script there is a way to "choose" which variables
> store into a certain region of memory?
Yes, you can use a linker script for this, together with
a gcc attribute to indicate which segment should receive
a given variable.
For example, somewhere in the linker script you could add
. = 0x40000000;
.ocm : { *(.ocm) }
This creates a new segment, "ocm", starting at address 0x40000000
(or wherever your OCM is mapped). To actually cause variables
to be allocated to this segment, use something like
#define __ocm__ __attribute__((aligned(32),section(".ocm")))
and then declare your variables:
int __ocm__ foo;
int __ocm__ bar[128];
You can verify that these ended up in the ocm segment with objdump.
And you'll want "ld -T my_linker_script.ld"; google linker-script
for tutorials.
Cheers,
Peter
Article: 99777iam using the dip switches to check the conditions..how should i give the input..and what should i use the push buttons for? how to do the memory interfacing?...do you have any material available in memory interfacing??Article: 99778
Art Stamness wrote:
> Please provide any evidence of this assertion :
>
> " The price you pay is very large: unmaintainable, unreadable code
> which is probably an order of magnitude larger than proper RTL."
>
> This coding style which you so clearly denegrate as sub par, is
> actually quite standard among high end chip development.
I fear you're right :-)
> Some reasons :
> ....
From this and other posts I believe you mentioned the following
tasks as arguments for the coding style in question:
1) randomization of flip-flop start-up values
2) retargeting a netlist to another technology
3) retiming for performance
My feedback would be that we face a methodology problem. Proper RTL
also means proper usage of available abstraction levels. RTL
is effective for functional description and verification, but
that's it. The task you describe can better be handled as follows:
1) gate level simulation
2) synthesis tool used in retargeting mode
3) advanced synthesis tool working at the gate level
Trying to do such things manually and at the RTL level will naturally
get you into trouble, to the point of generating self-fulfilling
prophecies ...
> Please consider that this chip was probably design by a group of
> engineers easily topping 100+, there were many compiler tools,
> synthesis, and other tools that needed to manipulate this code, and get
> meaningful information from it. Having each engineer write in what you
> describe as "proper RTL" style is not acceptable in these situations.
There you have it ;-)
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 99779Hi I want to use a networkmodule of Digilent and I downloaded a VHDL file from there website. => http://digilentinc.com/Resources/ApplicationNotes.cfm?Nav1=Design&Nav2=AppNotes This works fine if I use it als a project at ISE 8.1. When I want to use it as part of an IP under EDK 8.1 it doesn't work. I have made an IP with the create/inport wizard and I past the code in the User_Logic.vhdl file. I also adjust the vhdl file of the NET_IP. I have placed this at the PMD file of the IP PORT pdb = "", DIR = INOUT, VEC = [7:0], THREE_STATE = FALSE, IOB_STATE = BUF PORT astb = "", DIR = I PORT dstb = "", DIR =I PORT pwr = "", DIR = I PORT pwait = "", DIR = O PORT leds = "", DIR = O, VEC = [0:3] and I made these signals external then I placed this at the ucf file ## NET_IP NET NET_IP_0_pdb<0> LOC = "R8"; NET NET_IP_0_pdb<1> LOC = "R7"; NET NET_IP_0_pdb<2> LOC = "P5"; NET NET_IP_0_pdb<3> LOC = "P4"; NET NET_IP_0_pdb<4> LOC = "R2"; NET NET_IP_0_pdb<5> LOC = "T2"; NET NET_IP_0_pdb<6> LOC = "R6"; NET NET_IP_0_pdb<7> LOC = "R5"; NET NET_IP_0_pdb<0> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<1> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<2> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<3> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<4> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<5> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<6> IOSTANDARD = LVTTL; NET NET_IP_0_pdb<7> IOSTANDARD = LVTTL; NET NET_IP_0_astb_pin LOC = "R4"; NET NET_IP_0_dstb_pin LOC = "R3"; NET NET_IP_0_pwr_pin LOC = "U1"; NET NET_IP_0_pwait_pin LOC = "V1"; NET NET_IP_0_astb_pin IOSTANDARD = LVTTL; NET NET_IP_0_dstb_pin IOSTANDARD = LVTTL; NET NET_IP_0_pwr_pin IOSTANDARD = LVTTL; NET NET_IP_0_pwait_pin IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin<0> LOC = "AC4"; NET NET_IP_0_leds_pin<1> LOC = "AC3"; NET NET_IP_0_leds_pin<2> LOC = "AA6"; NET NET_IP_0_leds_pin<3> LOC = "AA5"; NET NET_IP_0_leds_pin<0> IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin<1> IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin<2> IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin<3> IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin<0> DRIVE = 12; NET NET_IP_0_leds_pin<1> DRIVE = 12; NET NET_IP_0_leds_pin<2> DRIVE = 12; NET NET_IP_0_leds_pin<3> DRIVE = 12; NET NET_IP_0_leds_pin<0> SLEW = SLOW; NET NET_IP_0_leds_pin<1> SLEW = SLOW; NET NET_IP_0_leds_pin<2> SLEW = SLOW; NET NET_IP_0_leds_pin<3> SLEW = SLOW; for some reason the pins of pdb (who are INOUT) are always 1 and never changes Can someone please tell me what I 'm doing wrong? Greets MichielArticle: 99780
"Frank" <frank@yahoo.com.cn> writes: |> I am looking for textbook with detailed information on AES encryption |> and decryption. I have Bernard Sklar's Digital Communications, but it |> contains DES only. For a detailed textbook about AES by its designers, have a look at Joan Daemen, Vincent Rijmen: The Design of Rijndael: AES - The Advanced Encryption Standard Springer, 2002, ISBN 3540425802. Most newer entry-level cryptography textbooks (e.g., Douglas R. Stinson's Cryptography: Theory and Practice, 3rd edition) contain a couple of pages on AES. What textbook is best suited for you really depends on your background and for what reason you want to learn about AES (just implement it? start a PhD project to attack it? teach a class?). Markus -- Markus Kuhn, Computer Laboratory, University of Cambridge http://www.cl.cam.ac.uk/~mgk25/ || CB3 0FD, Great BritainArticle: 99781
On 28 Mar 2006 21:58:52 -0800, "jfh" <jean-francois.hasson@fr.thalesgroup.com> wrote: >Hi, >Here is the trace when using the kernel 2.4 devel > >Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc. >(source@mvista.com) >On node 0 totalpages: 16384 >zone(0): 16384 pages. >zone(1): 0 pages. >zone(2): 0 pages. >Kernel command line: console=ttyS0,9600 root=/dev/xsysace/disc0/part3 >rw >Xilinx INTC #0 at 0x41200000 mapped to 0xFDFFE000 ... >C0002328 >Kernel panic: Aiee, killing interrupt handler! >In interrupt handler - not syncing In the above, what is "mapped to 0xFDFFE000"? If it's the interrupt vector table, be aware that the register pointing to it is only 16 bits wide, holding the 16 MSBs. So the vectors are at FDFFE000 but the PPC interrupt logic looks for them at FDFF0000. This doesn't seem to be very clearly documented. Apologies if this has nothing to do with the problem you are experiencing... - BrianArticle: 99782
Better to have 'Phase_Ctr' defined as a natural instead of a std_logic_vector since that is how it is being used i.e. signal Phase_Ctr: natural range 0 to 7; Then you have the even less cluttered Phase <= ROTATE_LEFT( "00000001", Phase_Ctr ); As long as you remember to define the range properly (i.e. the 0 to 7) then this will also synthesize to exactly the same thing. "JustJohn" <john.l.smith@titan.com> wrote in message news:1143578362.006883.143670@j33g2000cwa.googlegroups.com... > When you want a one of eight decoder, are you tired of typing in: > > with Phase_Ctr > select Phase <= > "00000001" when "000", > "00000010" when "001", > "00000100" when "010", > "00001000" when "011", > "00010000" when "100", > "00100000" when "101", > "01000000" when "110", > "10000000" when "111", > "00000000" when others; > > Then start taking advantage of IEEE.Numeric_Std: > > Phase <= ROTATE_LEFT( "00000001", TO_INTEGER( Phase_Ctr ) ); > > This is equally clear, and should sim/synth just the same. > > Other examples welcome... > > Sidebar request to Xilinx: > I love the vhdl template your ISE produces when adding a new source, > but it still starts things off with: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > That is so '90s, we're over halfway through the 00's. Is there any way > to change your ISE vhdl template to: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > Regards all, > Just John >Article: 99783
Art Stamness wrote:
> Please provide any evidence of this assertion :
>
> " The price you pay is very large: unmaintainable, unreadable code
> which is probably an order of magnitude larger than proper RTL."
A proper comparision would be to undertake the same project twice,
using the 2 design styles independently and then compare results.
Typically unfeasible of course. However, in my previous life at
the design service company I co-founded (Easics) I have had the
occasional opportunity to compare.
A good example is the following. In 1996, we had an industry-first
implementation of a complete USB slave (PHY+HUB) (Philips was
the customer.) At one point, Intel released a reference design of
the PHY part and we compared.
Their design was written in, let's say, OpenSPARC style, and
had 30+ modules with low level, incomprehensible code. It
synthesized to 4000+ gates. Ours had just 3 modules with clear
RTL code and synthesized to around 2500 gates.
Small design of course, but that is the trend. We have seen
it confirmed on a few other comparison occasions, and there
is every indication that things get only worse for larger designs.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 99784"Mich" <michiel.vanderlinden@gmail.com> wrote in message news:1143629406.275097.238120@j33g2000cwa.googlegroups.com... > Hi > > I want to use a networkmodule of Digilent and I downloaded a VHDL file > from there website. > => > http://digilentinc.com/Resources/ApplicationNotes.cfm?Nav1=Design&Nav2=AppNotes > > This works fine if I use it als a project at ISE 8.1. > When I want to use it as part of an IP under EDK 8.1 it doesn't work. > > I have made an IP with the create/inport wizard and I past the code in > the User_Logic.vhdl file. > I also adjust the vhdl file of the NET_IP. > > I have placed this at the PMD file of the IP > PORT pdb = "", DIR = INOUT, VEC = [7:0], THREE_STATE = FALSE, IOB_STATE > = BUF > PORT astb = "", DIR = I > PORT dstb = "", DIR =I > PORT pwr = "", DIR = I > PORT pwait = "", DIR = O > PORT leds = "", DIR = O, VEC = [0:3] > and I made these signals external > > then I placed this at the ucf file > ## NET_IP > NET NET_IP_0_pdb<0> LOC = "R8"; > NET NET_IP_0_pdb<1> LOC = "R7"; > NET NET_IP_0_pdb<2> LOC = "P5"; > NET NET_IP_0_pdb<3> LOC = "P4"; > NET NET_IP_0_pdb<4> LOC = "R2"; > NET NET_IP_0_pdb<5> LOC = "T2"; > NET NET_IP_0_pdb<6> LOC = "R6"; > NET NET_IP_0_pdb<7> LOC = "R5"; > NET NET_IP_0_pdb<0> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<1> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<2> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<3> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<4> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<5> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<6> IOSTANDARD = LVTTL; > NET NET_IP_0_pdb<7> IOSTANDARD = LVTTL; > > NET NET_IP_0_astb_pin LOC = "R4"; > NET NET_IP_0_dstb_pin LOC = "R3"; > NET NET_IP_0_pwr_pin LOC = "U1"; > NET NET_IP_0_pwait_pin LOC = "V1"; > > NET NET_IP_0_astb_pin IOSTANDARD = LVTTL; > NET NET_IP_0_dstb_pin IOSTANDARD = LVTTL; > NET NET_IP_0_pwr_pin IOSTANDARD = LVTTL; > NET NET_IP_0_pwait_pin IOSTANDARD = LVTTL; > > NET NET_IP_0_leds_pin<0> LOC = "AC4"; > NET NET_IP_0_leds_pin<1> LOC = "AC3"; > NET NET_IP_0_leds_pin<2> LOC = "AA6"; > NET NET_IP_0_leds_pin<3> LOC = "AA5"; > > NET NET_IP_0_leds_pin<0> IOSTANDARD = LVTTL; > NET NET_IP_0_leds_pin<1> IOSTANDARD = LVTTL; > NET NET_IP_0_leds_pin<2> IOSTANDARD = LVTTL; > NET NET_IP_0_leds_pin<3> IOSTANDARD = LVTTL; > > NET NET_IP_0_leds_pin<0> DRIVE = 12; > NET NET_IP_0_leds_pin<1> DRIVE = 12; > NET NET_IP_0_leds_pin<2> DRIVE = 12; > NET NET_IP_0_leds_pin<3> DRIVE = 12; > > NET NET_IP_0_leds_pin<0> SLEW = SLOW; > NET NET_IP_0_leds_pin<1> SLEW = SLOW; > NET NET_IP_0_leds_pin<2> SLEW = SLOW; > NET NET_IP_0_leds_pin<3> SLEW = SLOW; > > for some reason the pins of pdb (who are INOUT) are always 1 and never > changes > > Can someone please tell me what I 'm doing wrong? > > Greets > Michiel > I'm not sure but to implement a INOUT, I think you should use a tri-state buffer. MarcoArticle: 99785
I'm working on a CT-bus (H100) implementation. Can I use the SPARTAN3E DCM to (help to) generate the HOLDOVER capability for the 8MHz clocks (CT_C8_A and CT_C8_B)? They must meet Stratum4E (stability of 3.7x10^-7/day). Austin, maybe you have an advice! Luiz Carlos.Article: 99786
I am a final year engineering student, at the moment im having problems with the university eda tools, since im running out of time can anybody pls tell me ant free synthesizer to synthesize VHDL to Actel 1280XL FPGA. Thanks a lot, pls save my life !!!!!!!!!!! Prav thanks againArticle: 99787
Hi all, After I use Xilinx ISE do Place & Round and generate bit file, I am confused with a DRC warning=E3=80=82 "WARNING: DesignRules:7-Netcheck: An antenna was found on signal; this means that a branch of this signal is partially routed or has a routing stub". I found bit file with this DRC warning cannot work properly. But what's this signal connected to? A tri-state bus? Or this signal wire form a loop? Any suggestions will be appreciated! Best regards, DavyArticle: 99788
+1 for natural type on phase_ctr! Inside a process (sequential statements): phase <= (others => '0'); -- sequential statements phase(phase_ctr) <= '1'; Or if phase is a natural too: phase <= 2**phase_ctr; -- sequential or concurrent assignment AndyArticle: 99789
Hi Prav, I was surprised by your previous posting on ACTMAP (anybody still using that? I used it about 10 years ago which in terms of EDA tools is ancient :-). Are you sure your university doesn't have access to Synplify, Precision, QNS, XST or FPGA Express? I don't believe that there is a free synthesis tool for the ACT2 family but I could be wrong. I am also surprised you are targeting a 1280XL, not what I call a student friendly FPGA. If your project is in generic VHDL then I would suggest you try one of the free EDA offerings from Altera or Xilinx (or Lattice??). Hans www.ht-lab.com <praviendre@hotmail.com> wrote in message news:1143637667.175573.132760@u72g2000cwu.googlegroups.com... >I am a final year engineering student, at the moment im having problems > with the university eda tools, since im running out of time can anybody > pls tell me ant free synthesizer to synthesize VHDL to Actel 1280XL > FPGA. > > Thanks a lot, pls save my life !!!!!!!!!!! > > Prav > > thanks again >Article: 99790
And how do I use a tri-state buffer??? MichielArticle: 99791
"Peter Monta" <pmonta@pmonta.com> wrote in message
news:_qsWf.10094$tN3.3272@newssvr27.news.prodigy.net...
> Hi Marco,
>
>> If use use the linker script there is a way to "choose" which variables
>> store into a certain region of memory?
>
> Yes, you can use a linker script for this, together with
> a gcc attribute to indicate which segment should receive
> a given variable.
>
> For example, somewhere in the linker script you could add
>
> . = 0x40000000;
> .ocm : { *(.ocm) }
>
> This creates a new segment, "ocm", starting at address 0x40000000
> (or wherever your OCM is mapped). To actually cause variables
> to be allocated to this segment, use something like
>
> #define __ocm__ __attribute__((aligned(32),section(".ocm")))
>
> and then declare your variables:
>
> int __ocm__ foo;
> int __ocm__ bar[128];
>
> You can verify that these ended up in the ocm segment with objdump.
> And you'll want "ld -T my_linker_script.ld"; google linker-script
> for tutorials.
>
> Cheers,
> Peter
Many Thanks for your reply!
Marco
Article: 99792What should i do mate :). my ..... uni still uses ancient software and they are bloody hard to use. Even the operating system is Solaris. and i bloody hate it. Today i got rid of some of the components in the top design (obviously circuit doesn't work properly) and it gave me the edn file after like 30 mins. The full design still running and now its like 25 hours !!!!!!!! I thought about to move to Altera or Xilinx but university doesn't have the fabrication facilities for them. So i may have to stick to actel 1280XL. thanks anyway pravArticle: 99793
praviendre@hotmail.com wrote:
> I am a final year engineering student, at the moment im having problems
> with the university eda tools, since im running out of time can anybody
> pls tell me ant free synthesizer to synthesize VHDL to Actel 1280XL
> FPGA.
I use mentor leonardo.
You can get a time-limited eval here:
http://www.mentor.com/products/fpga_pld/synthesis/leonardo_spectrum/eval.cfm
-- Mike Treseler
Article: 997941) No, they didn't. Because I did all the synthesis without I/O package. So for the adder itself, there is no time delay for the input signals. And If I add register before that, there will be some Dff gate delay and wiring delay. 2) In XST, I didn't use register balancing but I still got less logic levels. In synplifypro, its seems there is no such option. And I don't know if the register balancing is a default operation or not. Thank you for your reply.Article: 99795
On 29 Mar 2006 01:00:59 -0800, bill.sloman@ieee.org wrote: > >John Larkin wrote: >> On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote: >> >> >> >So the Fpga to Fpga routing worked - good. >> >> That's not what we did. We designed a clock deglitcher to go inside >> the FPGA. > >Enough propagation delays to cover the dwell at the switching >threshold, and a state machine to make sure that the clock only changes >state once in that interval? We did my original #2 suggestion, a tapped delay line driven from the pin, driving an r-s flipflop. Set the flop if all the taps are 1s, clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter. The delay line is a string of eight buffers, about 10 ns overall. We'd have done Peter's circuit if we'd learned of it sooner. It's interesting that my post evoked two classes of response: 1. It can't be done, don't do it, kluge the boards (also the official Xilinx response!) 2. Yes, and here are my ideas on how you could do it/how I've already done it/interesting asides. JohnArticle: 99796
Jan Decaluwe wrote:
> Their design was written in, let's say, OpenSPARC style, and
> had 30+ modules with low level, incomprehensible code. It
> synthesized to 4000+ gates. Ours had just 3 modules with clear
> RTL code and synthesized to around 2500 gates.
Interesting story.
> Small design of course, but that is the trend. We have seen
> it confirmed on a few other comparison occasions, and there
> is every indication that things get only worse for larger designs.
Some organizations have huge monetary and cultural
commitments to certain classical cae point tools
that defy rational discussion.
-- Mike Treseler
Article: 99797Yes i was confusing triggering with registering. Thanks for helping out. MM wrote: > Subhasri, > > I believe you are confusing triggering with registering. Assuming you want > to start acquision on memory write you could use WR as your trigger signal. > The chipscope however allows for much more complex trigger events, but you > should remember to connect to the trigger ports whatever signals you want to > be a part of the triggering condition. > > /Mikhail > > > > "Subhasri krishnan" <subhasri.krishnan@gmail.com> wrote in message > news:1143564884.718634.150560@i40g2000cwc.googlegroups.com... > > Hi all, > > The design that I am working on is becoming increasingly difficult to > > debug and so I am trying to use chipscope pro. I tried some basic > > modules to familiarize myself with the tool and I have some basic > > questions about it. Can I capture more than 16384 samples? Can I > > capture more samples if I have a device with more gates than with > > lesser gates. i.e say XC3S200 Vs XC3S1500? I do not understand the > > concept of trigger ports. Suppose the whole design is based on the > > clock input to the fpga and the fpga is used as a memory controller, > > then what are the trigger ports? And should the output be triggered? I > > understand these are very basic questions and I tried to use google and > > the user guide to find the answer to this. If there are any basic > > documents that I can refer then please point me to it. > > Thanks > > Subhasri.K > >Article: 99798
Luiz, It has been almost eight years now.... But, How I solved similar problems was to choose a basic oscillator that had the necessary stability requirement (less than the 3.7E-7 drift per day), and then use a DDFS (direct digital frequency synthesizer) in the FPGA fabric to generate a frequency that tracks the incoming reference. When the reference is lost, the DDFS value is no longer updated. Then the output is whatever the last best guess of frequency and phase was, and you will drift within the specs of the oscillator. Do not get a voltage controlled oscillator: you will not use the adjustment, it cots more money, and it ruins the inherent stability of any oscillator. Do get an oscillator that is at least 2X higher frequency than is needed (I used 8X higher). Any frequency may be used, as the synthesizer can take a 20.000 MHz oscillator and generate exactly the 8 MHz reference you need. I used for the 2E clocks, the raw rubidium output, which was 50.2037(etc) MHz (basically every rubidium is shlightly different, but they don't drift very much <1E-12, and some don't drift at all! - tested them for 8 months with less than 1E-14 drift...). I used a 48 bit synthesizer (each step was 3.5E-15 of the oscillator frequency). For Stratum 4E, a smaller DDFS accumulator can be used, perhaps as few as 40 bits? Since the logic is so small, it is effectly free. The tracking algorithm needs some thought. The phase detctor needs some thought. The reasons to stop tracking needs a lot of though. The reasons to start tracking again also needs thought. There are many standards that must be met, as well. It may be that 4E has to tracking requirement, but if you don't at least start with the last best guess of frequency, you will cause slips everywhere. Just can't remember how featured 4E is. I know 3E has tracking. Stratum 4 has no tracking requirement, just a frequency accuracy. Looking at the data sheets for commercial stratum clocks will give you an idea of what is needed for features, and performance levels. Depending on how you implement your loop, there is a patent on the way I did it (uspto.gov, search on - Austin, Lesea, as inventor, and look for 'All digital locked loop'...). If you do it that way, there is a company that owns it, and will not like it. Austin oen_no_spam@yahoo.com.br wrote: > I'm working on a CT-bus (H100) implementation. > Can I use the SPARTAN3E DCM to (help to) generate the HOLDOVER > capability for the 8MHz clocks (CT_C8_A and CT_C8_B)? They must meet > Stratum4E (stability of 3.7x10^-7/day). > Austin, maybe you have an advice! > > Luiz Carlos. >Article: 99799
I can't speak for Altera but I haven't heard anything about a multithreaded/hyperthreaded NIOS core. It might be better if you asked you question at the www.niosforum.com website. Have you check Sun's website for the OpenSPARC project? I think it supports multiple cores and hyperthreading. Technology-wise it might still might be a little early to find a lot of projects or examples. Derek
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